JP2005085399A - Memory cell, semiconductor memory device, and microcomputer having semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory cell in which cell data are surely initialized. <P>SOLUTION: A memory cell 100 has a data latch circuit in which input and output of a first inverter circuit 101 and a second inverter circuit 102 are connected to each other, transfer gates 104, 106 in which gates are connected to word lines 103 to control read/write of data, and an NMOS transistor 110 for initial-value setting which is disposed between an output side of one of the inverter circuits 101, 102 and ground potential, and subjected to conduction control using a reset signal, wherein "0" is set as an initial-value data. A SRAM circuit of an initial-value setting type configured by the memory cell 100 is used as a program memory and also a data memory. Moreover, the initial-value setting is surely performed without executing the program for initial-value setting immediately after supply voltage application, resulting in a reliable memory cell. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a memory cell capable of setting fixed data, a semiconductor memory device, and a microcomputer including the semiconductor memory device.

  In a conventional random access memory (RAM), in particular, a static RAM (SRAM), the data storage content of the memory cell is determined to be “1” or “0” at the time of power-on, but what is it? The value is undefined in the sense that it is not arbitrary by the user.

  Therefore, when initializing the stored data when using the SRAM, it is necessary to write predetermined data to all SRAM cells, for example, using an initialization program. For this reason, in conventional single-chip microcomputers with a built-in SRAM, only the data and addresses can be stored in the SRAM, and fixed data such as programs are not stored in the SRAM. It was.

  Table 1 is a memory map of a general microcomputer system. The chip select signal CS0 designates the monitor program area stored in the program ROM to which the address space 0000H to 1fffH is assigned, and the chip select signal CS2 is the user stored in the user RAM to which the address space 2000H to 3fffH is assigned. The program area is designated, and the chip select signal CS6 designates the I / O register / data area to which the address spaces 6000H to 60ffH are assigned and the I / O area to which the address spaces 6100H to 6105H are assigned, The chip select signal CS8 designates the user data area stored in the data RAM to which the address spaces 8000H to ffffH are assigned.

  In the conventional technique, the memory map indicating the memory usage state in the microcomputer is not changed during the operation of the microcomputer. For this reason, the following problems have been pointed out.

  That is, program data such as an initialization program that operates only when the entire system is initialized and a test program that operates only at the time of shipment and is not used during actual operation are also read-only memory devices (ROM). They are stored above and they occupy a certain address space. However, these programs are unnecessary during actual operation, and constitute a useless address space for a central processing unit (CPU) that can access the program memory and data memory.

  Patent Document 1 described below discloses a microcomputer invention in which a main program can be stored up to the maximum ROM capacity by initializing a startup program for self-diagnosis in a RAM.

  This microcomputer is formed on the same semiconductor substrate as a RAM having a RAM cell capable of automatically performing an initial setting immediately after application of a power supply voltage without executing an initial value setting program, And a central processing unit that performs read / write control of the RAM.

In this microcomputer, when the built-in SRAM is manufactured, the stored data immediately after power-on of the two inverters in each SRAM cell corresponding to at least the startup program area is set to “1” or “0”. By manufacturing with different operating characteristics, stored data immediately after power-on of each SRAM cell corresponding to the activation program area can be automatically initialized as desired.
Japanese Patent Laid-Open No. 6-60668 (paragraph numbers [0009], [0022] and FIG. 3)

  In Patent Document 1 described above, since the operation characteristics of the two inverters constituting each SRAM cell are made different and data is to be initialized by the difference in their rise times, the reliability of the initial value setting is determined. There was a problem of poor reliability.

  In addition, it is considered that the ROM and RAM are mapped to the same address space, and switching them with an address decoder to eliminate waste of the address space. In this method, each chip constituting the SRAM and ROM areas is considered. However, there is a problem that the chip mounting area is physically increased.

An object of the present invention is to provide a memory cell that can reliably initialize cell data.
Another object of the present invention is to provide a semiconductor memory device that can be dynamically switched and used as a program memory and data memory.

  Another object of the present invention is to provide a microcomputer that eliminates waste of chip mounting area such as ROM and address space.

  The memory cell according to the present invention connects the input of the first inverter and the output of the second inverter, and connects the output of the first inverter and the input of the second inverter. The circuit and either the source or drain are connected to the output side of the first inverter, the other is connected to the first bit line, and the gate is connected to the word line, thereby reading and writing data. A first transfer gate for controlling the power source, one of a source and a drain connected to the output side of the second inverter, the other connected to a second bit line, and a gate connected to the word line By doing so, the second transfer gate for controlling the reading and writing of data and the first or second inverter are connected. Re or disposed between one of the output side and the ground potential, and a switch element of the initial value for the setting is conducted controlled by a reset signal.

  According to another aspect of the present invention, there is provided a semiconductor memory device including: a memory cell array in which the above-described memory cells are arranged in rows and columns at intersections of a plurality of word lines and a plurality of first and second bit lines; And a read / write circuit for reading and writing data by controlling the bit line of 2 and supplying a reset signal to the switch element to turn on the fixed data from the data latch circuit of the memory cell. Read out.

  Further, the microcomputer of the present invention includes a central processing unit that can access a program memory and a data memory, a read-only memory device that functions as the program memory, and a part of the semiconductor memory device that functions as the data memory. A part of the program of the central processing unit is stored as fixed data of the semiconductor memory device, and the semiconductor memory device is dynamically used as a program memory and a data memory. Switch to use.

As an effect of the present invention, it is possible to reliably set an initial value immediately without applying an initial value setting program immediately after application of a power supply voltage, and to provide a highly reliable memory cell.
Further, it is possible to provide a semiconductor memory device in which a part of memory cells can be dynamically switched and used as a program memory and a data memory only by turning on and off the switch element for initial value setting.

  Furthermore, by dynamically switching and using the semiconductor memory device as a program memory / data memory, a microcomputer can be provided that eliminates waste of chip mounting area such as ROM and address space.

  The present invention can be applied as a circuit technology for configuring a memory cell such as an SRAM or a microcomputer system using an SRAM.

  In the first embodiment, a memory cell that can use an SRAM having data of an initialization program and a test program as an initial value at power-on as a program memory and data memory will be described.

FIG. 1 is a diagram showing an initial value setting type SRAM circuit, and FIG. 2 is a circuit diagram showing a configuration of a unit memory cell of FIG.
In the following description, the signal level L is “0” and the signal level H is “1” unless otherwise specified.

  In FIG. 2, a unit of memory cell 100 is composed of a first inverter circuit 101 that holds stored data and a data latch circuit in which the input and output of the second inverter circuit 102 are connected to each other. . The connection point between the input of the first inverter circuit 101 and the output of the second inverter circuit 102 is a bit on the normal rotation side via a transfer gate 104 whose conduction is controlled by an address signal applied to the word line 103. The connection point between the output of the first inverter circuit 101 and the input of the second inverter circuit 102 is connected to the line 105 via a transfer gate 106 that is controlled to be conductive by an address signal applied to the word line 103. It is connected to the bit line 107 on the inversion side.

  Such memory cells 100 are arranged in a matrix, and form, for example, an 8-row, 4-column memory cell array as shown in FIG. An address decoder 108 to which a 3-bit address signal ad [2: 0] is supplied is connected to the memory cell 100 of the memory cell array, and in the write cycle specified by the address signal ad [2: 0] Data 3 to data 0 are written as stored data from the read / write circuit 109 to the memory cell 100 corresponding to the address (000 to 111) via the normal rotation side bit line 105 and the reverse side bit line 107.

  A timing control signal is supplied to the read / write circuit 109, and in the read cycle, the storage data stored in each memory cell 100 is transmitted through a transfer gate whose conduction is controlled by an address signal from the word line 103. The data is read to the lines 105 and 107, and output from the read / write circuit 109 as 4-bit signals of output data dat [3] to dat [0].

  In FIG. 2, the source of the NMOS transistor 110 is connected as a switch element for setting an initial value to the normal bit line 105 side, for example, bit 0 of the address (000) in the memory cell 100. Shows what it is. The gate of the NMOS transistor 110 is connected to the reset terminal 111, and the drain is grounded.

  In the memory cell 100 of FIG. 2, the H data is supplied to the reset terminal 111 when the initial value is set, so that the cell data serving as the initial value data of the memory cell 100 can be reliably set to “0”. Here, the bit line 105 (datax) on the right side of the data latch circuit has a positive polarity, the bit line 107 (datax_) on the left side has a negative polarity, and an NMOS transistor 110 for setting an initial value is on the right side of the memory cell 100. In this case, the initial value data is “0”. However, when the NMOS transistor for setting the initial value is on the left side, for example, bit 0 of the address (001), the initial value data is set to “1”. The When PMOS transistors are used as these initial value setting switch elements, the polarity of the data to be set is reversed.

  When a monitor program such as an initialization program or a test program is executed, the initial value setting type SRAM of FIG. 1 (hereinafter also referred to as SRAM with an initial value) operates as a program memory, and other actual operation programs. When is executed, it operates as a data memory. As a result, the address space of the semiconductor memory device can be saved, and the memory capacity of the SRAM that can be used during actual operation can be increased without increasing the physical memory.

The specific circuit configuration shown in FIG. 1 will be described below.
When the address is (000), the initial value setting NMOS transistors 110 are all connected to the right side in the memory cells of bit 3 to bit 0. Therefore, the initial value of all bits 3 to 0 is 0. When the address is (001), only the bit 0 is connected to the left side of the NMOS transistor 110 for setting an initial value. Therefore, the initial value of only bit 0 is “1”, and the others are “0”. In the SRAM circuit of FIG. 1, the correspondence between the 4-bit initial value data (binary number) in each 3-digit address (binary number) is as shown in Table 2 below.

  The NMOS transistors 110 for setting initial values have gates commonly connected to the reset terminal 111, and when the SRAM with initial values is reset, the transistors for setting initial values are turned on to obtain predetermined initial values. Will be set. However, when the reset signal is released, the initial value setting transistor is turned off, and therefore, it can operate in the same manner as a general SRAM. Therefore, in the semiconductor memory device such as the SRAM with an initial value shown in FIG. 1, it can be surely dynamically switched and used as the program memory and data memory.

  In order to reset the SRAM with initial value, in addition to inputting a reset signal to the reset terminal 111, for example, a method of resetting when the upper 8 bits of the 16-bit address become all zeros, or a chip select to the SRAM with initial value Two terminals can be provided, and one terminal can be realized by inputting a fixed data output command from the program area.

  FIG. 3 is a block diagram showing a circuit configuration of a microcomputer using an SRAM with an initial value. FIG. 4 shows a memory map of the microcomputer shown in FIG. FIG. 5 shows a memory map necessary for realizing the same memory function as in FIG. 4 using the conventional technique.

  The microcomputer shown in FIG. 3 includes an SRAM 31 with initial values, an SRAM 32, a ROM 33, a CPU 34, and an address decoder 35. The SRAM 31, SRAM 32, and ROM 33 with initial values include an address bus 36, a data bus 37, and a read signal (OE; The timing signal lines such as Out Enable and write signal (WE) are common. The address decoder 35 outputs chip select signals CS0, CS1, and CS2 to the SRAM 31, SRAM 32, and ROM 33 with initial values, respectively.

  If only the circuit configuration of the SRAM 31 with initial value is changed, the sense amplifier, the decoder, and the control circuit can be shared with each other, and the address decoder 35 of FIG. 3 can be eliminated.

  As shown in FIG. 4, an initialization program, a test program, and the like are stored at addresses 0000H to 007fH of the SRAM 31 with an initial value, and other actual operation programs are stored at addresses 0080H to 0fffH of the ROM 33. When the reset signal is turned on immediately after the power is turned on, an initialization program and a test program are loaded into the SRAM 31 with an initial value, and the CPU 34 executes them as necessary. At this time, the SRAM 31 with an initial value operates as a program memory.

  Thereafter, when the initialization program or the test program is completed or when it is not necessary to start from the beginning, the actual operation program is executed by jumping to an address (ROM area) from 0080H to 0fffH by a branch instruction. At this stage, since the CPU 34 does not need to access the addresses 0000H to 007fH, the SRAM 31 with an initial value can be operated as a general-purpose SRAM. Therefore, in the example of FIGS. 3 and 4, by accessing the addresses 1000H to 107fH, the CPU 34 can use the SRAM 31 with the initial value in the same manner as the SRAM 32 in the data memory area.

  On the other hand, when the initialization program and the test program are to be realized using only a general SRAM without using the SRAM 31 with the initial value, the address from 0000H to 0fffH is stored in the ROM 33 as shown in FIG. Address space, and addresses from 1000H to 10ffH must be configured by the SRAM 32.

  That is, comparing the case where the address space is configured on the memory map as shown in FIG. 4 and the case of FIG. 5, comparing the case of FIG. 5 with the ROM address of 0f80H and the SRAM address of 00ffH, FIG. In the case of the prior art, only 0 fffH of ROM and 00ffH of SRAM are required. Therefore, the microcomputer of the present invention is advantageous in terms of chip mounting area because the memory capacity of the SRAM to be used is reduced.

1 is a diagram illustrating an initial value setting type SRAM circuit; FIG. FIG. 2 is a circuit diagram illustrating a configuration of a unit memory cell in FIG. 1. It is a block diagram which shows the circuit structure of the microcomputer using SRAM with initial value. It is a memory map figure of the microcomputer of FIG. It is a memory map figure required in order to implement | achieve the memory function similar to FIG. 4 using a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory cell 101,102 Inverter circuit 103 Word line 104,106 Transfer gate 105,107 Bit line 108 Address decoder 109 Read-write circuit 110 NMOS transistor 111 Reset terminal

Claims (4)

A data latch circuit configured to connect the input of the first inverter and the output of the second inverter and connect the output of the first inverter and the input of the second inverter;
Either the source or the drain is connected to the output side of the first inverter, the other is connected to the first bit line, and the gate is connected to the word line, thereby controlling the reading and writing of data. A first transfer gate;
Control the reading and writing of data by connecting either the source or drain to the output side of the second inverter, connecting the other to the second bit line, and connecting the gate to the word line A second transfer gate that,
A switch element for setting an initial value, which is disposed between the output side of one of the first and second inverters and a ground potential, and is conductively controlled by a reset signal;
A memory cell comprising:   2. The memory cell according to claim 1, wherein each of the data latch circuit, the first and second transfer gates, and the switch element is constituted by a MOS transistor circuit. A memory cell array in which the memory cells according to claim 1 are arranged in a matrix at intersections of a plurality of word lines and a plurality of first and second bit lines, respectively.
A read / write circuit for reading and writing data by controlling the first and second bit lines;
With
A semiconductor memory device, wherein a fixed signal is read from a data latch circuit of the memory cell by supplying a reset signal to the switch element and making them conductive. A central processing unit capable of accessing a program memory and a data memory;
A read-only memory device that functions as the program memory;
4. A readable / writable semiconductor memory device, partly including the semiconductor memory device according to claim 3, which functions as the data memory;
With
A part of a program of the central processing unit is stored as fixed data of the semiconductor memory device, and the semiconductor memory device is dynamically switched and used as a program memory and a data memory. Microcomputer.

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