JP2760811B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip selection technique for a semiconductor integrated circuit, for example, a technique effective when applied to a semiconductor memory device and a system including the same.

[Conventional technology]

In a microcomputer application system, an address space managed by a master module such as a microcomputer or a microprocessor usually includes various peripheral devices such as a memory, an input / output circuit, and a timer / counter. Have been assigned. When a master device such as a microcomputer accesses a peripheral device, the master device outputs an address signal including a bit designating an address assigned to the access target device. Conventionally, predetermined bits of the address signal output in this way are TTL (transistor-transistor-transistor).
(Logic) circuit and the like, and the address decoder generates a selection signal such as a chip select signal for selecting a device chip based on an input address signal. The selection signal generated by the address decoder is supplied to each peripheral device and the like, and a device receiving the selection signal of the chip selection level is made operable. For example, in the case of a memory, an internal address buffer is operated in response to a chip selection state. Then, the address decoder and the read amplifier are activated, and thereafter, decoding of an external address signal for addressing a memory cell is started to perform a read operation or a write operation.

Some devices, such as microcomputers and processors, internally generate a chip select signal and directly apply it to peripheral modules as described in Japanese Patent Application Laid-Open No. Sho 62-196744. The control function is limited, and if there are a number of peripheral devices that cannot be supported by the function, an address decoder for generating a chip select signal is required as described above.

[Problems to be solved by the invention]

However, in a configuration in which chip selection control for peripheral devices is performed by an address decoder such as a TTL circuit, decoding operation for forming a chip selection signal takes time. In addition, there is a problem that a delay time that cannot be ignored is caused before operation becomes possible. Even if the operation speed of each device is improved, the access time in the system operation is prolonged, and the throughput of the system operation is reduced. Has been made clear by the present inventors.

An object of the present invention is to provide a semiconductor integrated circuit which can eliminate the overhead from the start of a bus cycle to the actual internal operation in terms of chip selection control. Still another object of the present invention is to provide a semiconductor integrated circuit which can prevent an access cycle in system operation from becoming uselessly long in terms of chip selection control and can contribute to an improvement in system operation throughput. To provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, an internal circuit that performs a unique operation based on an instruction from the outside, and an information circuit that outputs information obtained in the operation unique to the internal circuit to the outside or obtains information necessary for an operation unique to the internal circuit from the outside. In a semiconductor integrated circuit having a data interface unit, storage means for holding address information allocated for chip selection of the semiconductor integrated circuit; address information held by the storage means and address information supplied from outside; And a control means for controlling the data interface unit based on the comparison result.

Here, in response to the activation of a bus cycle externally activated, the internal circuit has its own unique circuit in synchronization with an assert timing such as a bus start signal or an address strobe signal which means the start of a bus cycle. The operation can be started. At this time, the control means substantially disables / initiates the processing of the internal circuit already started based on the comparison result of the mismatch / match between the address information held in the storage means and the address information supplied from the outside. The data interface unit can be controlled to be valid.

Further, by making the storage means rewritable based on external access, it is possible to change the address mapping state of the semiconductor integrated circuit including the storage means only by changing the information held in the storage means. .

(Operation)

According to the above-described means, each semiconductor integrated circuit has a function of determining whether or not there is a chip selection of its own based on address information allocated for chip selection, and this function is necessary for system operation. Chip
It works so that an address decoder such as a TTL circuit for select control is not required.

The result of the chip selection / non-selection state determination by the semiconductor integrated circuit itself is reflected in the control of the data interface unit. As a result, the internal circuit can operate in advance in response to the start of the bus cycle regardless of the presence / absence of chip selection / non-selection. The process of controlling the data interface unit so that the started process of the internal circuit is substantially invalidated to the outside is realized.

Therefore, the overhead from the start of the bus cycle in the system operation to the actual operation being enabled is reduced, and the access cycle in the system operation can be prevented from becoming uselessly long. This achieves an improvement in throughput.

〔Example〕

FIG. 1 is a block diagram of an SRAM (static random access memory) according to an embodiment of the present invention. Although the SRAM shown in FIG. 1 is not particularly limited, it can be manufactured by using a known semiconductor integrated circuit manufacturing technique.
Formed on one semiconductor substrate.

The SRAM 1 shown in FIG. 1 is a memory cell array 2 in which static memory cells (not shown) are arranged in a matrix.
Is provided. Terminals of the memory cells constituting the memory cell array 2 is coupled to the word line WL ₀ ~WLi for each row, also,
Data input / output terminals of memory cells are complementary bit lines in column units
BL ₀₀ , ▲ ▼ to BLen, ▲ ▼.

Although the address signal for addressing the memory cell is not particularly limited, the lower n bits of the n + i bit address signal ADRS supplied to the external address input terminal 3 are used.
The row address signal Ar contained therein is supplied to a row address buffer 4 and converted into an internal complementary address signal. The internal address signal output from the row address buffer 4 is supplied to a row address decoder and a word driver 5 for decoding, and a predetermined word line corresponding to the decoded result is driven to a selected level by the word driver. The column address signal Ac included in the lower n-bit address signal is supplied to the column address buffer 6 to be converted into an internal complementary address signal. The internal address signal output from the column address buffer 6 is supplied to a column address decoder 7 and decoded. In FIG. 1, reference numeral 8 denotes the complementary bit line BL.
₀₀ , a column selection circuit including a switch (not shown) for connecting ▲ to BLen, ▼ to the common data line CD ₀ , ▼ to CDe, ▼ on a one-to-one basis. The switches (not shown) are connected to the common data lines CD ₀ , 〜 to CDe, ▼ by the output selection signal of the column address decoder 7.
, A pair of bit lines is controlled to be conductive. Thereby, the row address signal Ar and the column address signal Ac
Are conducted to the common data lines CD ₀ , ▼ to CDe, ▼.

The common data lines CD ₀ , ▲ ▼ to CDe, ▲ ▼
It is coupled to the input terminal of the sense amplifier 10 which amplifies the memory cell data read therefrom. Although not particularly limited, the sense 10 has respective common data lines CD ₀ , ▲ ▼
~ CDe, ▲ ▼
The output taken out from each differential amplifier circuit on a single end is supplied to a read circuit 11 such as a data output buffer, and in a memory read operation, the read circuit 11
Is output to the outside via the external data input / output terminal 12. Further, an output terminal of the writing circuit 13 such as a data input buffer is coupled to the common data lines CD ₀ , ▲ to CDe, ▲. In the memory write operation, the write circuit 13 transfers write data supplied from the external data input / output terminal 12 to the common data lines CD ₀ , ▲ to CDe, ▲ ▼
To supply.

Here, FIG. 2 shows a configuration example of one bit in the write circuit 13. According to FIG. 2, the write circuit 13 converts the write data from outside into an amplifying inverter.
The signal is supplied to a pair of common data lines as a complementary level data signal via an inverter 21. In the preceding stage, for example, n-channel transfer MOSFETs Q1, Q
2 and the MOSFETs Q1 and Q2
Switch controlled by mp ・ we. This write control signal
When comp.we is set to the high level, the write circuit 13 becomes operable.

FIG. 3 shows a configuration example of one bit in the read circuit 11. According to FIG. 3, the power supply terminals Vdd, Vss
A pair of n-channel output MOSFETs Q connected in series between
3, Q4 is provided in the final output stage, and the gate electrode of one output MOSFET Q3 is coupled to the output terminal of an inverter 24 which receives and inverts the output of the two-input NAND gate 23, and similarly, the gate electrode of the other output MOSFET Q4 is It is coupled to the output terminal of an inverter 26 which receives and inverts the output of the two-input NAND gate 25. A signal obtained by inverting read data by an inverter 27 is supplied to one input terminal of the NAND gate 23, and the input terminal of the NAND gate 25 is connected to one input terminal of the NAND gate 25.
A signal obtained by further inverting the output of 27 by an inverter 28 is supplied, and the other input terminals of both NAND gates 23 and 25 are supplied with a read control signal comp · oe. The read circuit 11 is operable when the read control signal comp · oe is at a high level, thereby obtaining a logical output corresponding to the input data level. When the read control signal comp · oe is low, both MOSFETs Q3 and Q4
Is controlled to be in the off state, whereby the readout circuit 11 is set to the high output impedance state.

Next, chip selection control and internal operation timing control in the SRAM 1 of the present embodiment will be described.

The upper i bits of the address signal ADRS supplied to the external address signal input terminal 3 are regarded as address information that can be assigned for selecting a chip of a device such as an SRAM. In a conventional device such as an SRAM, the i-bit address information is not directly taken in, but is supplied to an external address decoder (not shown) for forming a chip select signal.

In FIG. 1, reference numeral 31 denotes a data register in which address information which can be assigned to select the SRAM 1 as a chip can be set. The setting of data in the data register 31 is not particularly limited, but the external data input terminal 12
Done through. The address information set in the data register 31 and the i
The bit address information is supplied to the comparison circuit 30, where the match / mismatch is determined, and a comparison control signal comp of a level corresponding to the result is output from the comparison circuit 30. Here, the case where both input address signals match means a case where each bit is completely matched or a case where there is a relation having an inclusive relation in a space defined by each address information. The signal comp is set to high level.

In FIG. 1, reference numeral 35 denotes a timing generator for generating an internal timing signal of the SRAM1. Conventional SR
A chip select signal is supplied to a timing generator in a device such as an AM, and when this is asserted, the internal operation is started only after the corresponding device is selected, but the SRAM 1 of this embodiment receives a chip select signal from the outside. I do not receive. Instead, a bus start signal ▲ ▼ which indicates the start of a bus cycle is externally received, and when this signal is asserted, the internal operation is started regardless of whether or not the SRAM 1 is a device to be chip-selected. It has become. That is, the bus start signal ▲
The timing generator 35 which receives the write enable signal ▲ ▼, the output enable signal ▲ ▼, and the register program signal ▲ ▼ from the outside together with the ▼ outputs the internal activation signal at a predetermined timing when the bus start signal ▲ ▼ is asserted. Assert φ to activate the row address buffer 4, row address decoder and word driver 5, column address buffer 6, column address decoder 7, sense amplifier 10, and the like to enable internal operation. Therefore, in this state
When the address signal ADRS is supplied to the SRAM 1, the generation of complementary internal addresses by the address buffers 4 and 6 and the address decoding operation by the address decoders 5 and 7 are started. At this time, the instruction of the memory write operation is instructed by asserting the write enable signal ▼ to a low level, and based on this, the internal write signal we is asserted to a high level at a predetermined timing. Further, the instruction of the memory read operation is instructed by asserting the output enable signal ▼ to a low level, and based on this, the internal read signal oe is asserted to a high level at a predetermined timing. Although not particularly limited, the internal write signal Ewe is ANDed with the comparison control signal comp by the AND gate 32,
The result is a write control signal comp for the write circuit 13.
・ It is called we. The internal read signal oe is not particularly limited, and the AND gate 33 takes a logical product of the internal control signal comp with the comparison control signal comp.

When the bus start signal BS is asserted to start the internal operation irrespective of whether or not the SRAM 1 is a device to be chip-selected, in parallel with this, the comparison circuit 30 outputs the upper i bits. The address signal is compared with the address information set in the data register 31. If they match, that is, if the SRAM 1 is a device to be chip-selected, the comparison control signal comp
Is asserted to a high level. Therefore, regardless of whether or not the SRAM 1 is a device to be chip-selected, the result of the internal operation started in advance is made valid to the outside. For example, in the case of a memory read operation, an address decoding operation started in advance irrespective of whether or not SRAM1 is a device to be selected as a chip, and when a predetermined memory cell is addressed thereby, assertion to a high level is performed. The read circuit 11 is activated by the read control signal comp · oe to be read, whereby the addressed memory cell data can be read to the outside. Also,
In the case of a memory write operation, an address decode operation started in advance irrespective of whether or not the SRAM 1 is a device to be chip-selected, and furthermore, when a predetermined memory cell is addressed, a write signal asserted to a high level. The write circuit 13 is activated by the control signal comp · we, whereby external write data can be written to the addressed memory cell via the write circuit 13.

On the other hand, when the bus start signal ス タ ー ト is asserted, the comparison result by the comparison circuit 30 performed in parallel with the start of the internal operation regardless of whether or not the SRAM 1 is a device to be chip-selected becomes inconsistent. In some cases, that is, when the SRAM 1 is not a device to be chip-selected, the comparison control signal comp maintains a low-level negated state. Therefore, even if the internal operation is started in advance irrespective of whether or not the SRAM 1 is a device to be chip-selected, both the read circuit 11 and the write circuit 13 are not activated. Is invalid to the outside world.

The data setting for the data register 31 is instructed by asserting the register program signal ▲ at a low level. When the register program signal ▼ is asserted, the timing generator 35 asserts the internal control signal rpgm. As a result, the input gate of the data register 31 is opened at a predetermined timing synchronized with the external data transfer timing, and external data can be set. still,
Although not particularly limited, the register program signal ▼ is generated according to an address decode result by an external address decoder.

According to the above embodiment, the following effects can be obtained.

(1) Since the SRAM 1 has the function of storing address information allocated for chip selection in the data register 31 and judging the presence / absence of chip selection / non-selection of the SRAM 1 based on this, it is necessary for system operation. Chip
An address decoder such as a TTL circuit for select control can be eliminated.

(2) In terms of system operation, the SRAM 1 of this embodiment starts an internal operation such as address decoding immediately after the start of a bus cycle, and when the SRAM 1 determines that the SRAM 1 is a device to be selected as a chip in system operation, Since the external data interface units such as the write circuit 13 and the read circuit 11 are controlled so that the processing of the already started internal circuit is made effective to the outside, the chip selection state is set even when a bus cycle is started. As compared with the conventional device configuration in which the start of the internal operation must be waited until the start of the internal operation, the overhead from the start of the bus cycle of the device to be selected to the actual operation of the device can be eliminated. The access cycle above can be prevented from becoming uselessly long, and the throughput of the system operation can be reduced. Contribute to the above.

(3) When the contents of the data register 31 are externally rewritable, the address mapping state of the SRAM 1 can be changed only by changing the setting information of the data register 31. Therefore, the SRAM 1 of the present embodiment
In a microcomputer application system or the like including a plurality of such devices, the data transfer in a memory unit can be easily performed by systematically rewriting the contents of the data register 31 included in each SRAM 1.

The invention made by the present inventor has been described in detail based on the embodiments. However, the present invention is not limited to each, and can be variously modified without departing from the gist thereof.

In the above embodiment, the operation start of the internal circuit corresponding to the start of the bus cycle is configured to be synchronized with the bus start signal ▲ ▼, but it may be changed to an address strobe signal or the like which means the validity or decision of the address signal. Good. Such a signal is not always necessary. For example, a device configured to detect a change in address and start an internal operation does not need to receive such a signal. Further, the external control signal for instructing the read operation or the write operation is not limited to the above-described embodiment, and can be changed to a signal substantially indicating the instruction of the read operation or the write operation. Further, in the above-described embodiment, a configuration in which one signal φ is commonly used as an internal control signal for activating an internal circuit has been described. However, the type and assert timing of such a signal can be appropriately changed.

Further, the storage means such as the data register 31 described in the above embodiment may be a rewritable static configuration such as a flip-flop, an EPROM (electrically programmable read only memory),
An electrically erasable nonvolatile storage element such as an EEPROM (electrically erasable and programmable read only memory), and a nonvolatile storage element such as a mask ROM. Can be. In the case where such a storage unit has a static configuration, data setting for the storage unit can be performed at system startup, and the storage unit is configured using an electrically writable nonvolatile storage element. In such a case, the storage means can be programmed at the time of system design or system development.

In the above description, the case where the invention made by the inventor is mainly applied to the SRAM, which is the application field behind it, has been described.However, the present invention is not limited thereto, and may be applied to various other semiconductor memory devices. The present invention can be widely applied not only to those that can be applied, but also to various other semiconductor integrated circuits such as input / output devices and controller devices. The present invention provides an internal circuit that performs a specific operation based on at least an instruction from the outside, and outputs information obtained by an operation specific to the internal circuit to the outside or obtains information necessary for an operation specific to the internal circuit from the outside. And a data interface unit for the same.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

In other words, the semiconductor integrated circuit according to the present invention has a function of storing address information allocated for chip selection in the storage means and determining its own chip selection / non-selection based on the information. There is an effect that an address decoder such as a TTL circuit for required chip select control can be omitted.

Further, in terms of system operation, the semiconductor integrated circuit according to the present invention starts internal operations such as address decoding immediately after the start of a bus cycle, and determines that the semiconductor integrated circuit is a device to be selected as a chip in system operation. When the determination is made, since the data interface unit is controlled so that the processing of the already started internal circuit is made valid to the outside, the start of the internal operation is waited until the chip is selected even if the bus cycle is started. Therefore, compared with the conventional device configuration, it is possible to eliminate the overhead from the start of a bus cycle to the actual operation of a device to be selected as a chip, and to further reduce access cycles in system operation. Can be prevented, and the throughput of system operation can be improved. There is an effect that kill.

If the contents of the storage means are rewritable from outside, the address mapping state of the semiconductor integrated circuit can be changed only by changing the setting information of the storage means.

[Brief description of the drawings]

FIG. 1 is a block diagram of an SRAM according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration example of one bit in a write circuit, and FIG. 3 is a configuration example of one bit in a read circuit. It is a circuit diagram. 1 ... SRAM, 2 ... memory cell array, 4 ... row address buffer, 5 ... row address decoder and word driver, 6 ... column address buffer, 7 ... column address decoder, 8 ... column selection circuit, 10 … Sense amplifier, 11 read circuit, 13 write circuit, 30 comparison circuit, 31 data register, 35 timing generator.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/41

Claims (3)

(57) [Claims] An internal circuit which starts a specific operation in response to the start of a bus cycle started externally, and outputs information obtained by an operation specific to the internal circuit to the outside or an operation specific to the internal circuit. A data interface unit for obtaining externally necessary information, a storage unit for holding address information, and comparing the address information held by the storage unit with address information supplied from the outside, and determining whether the mismatch / match Control means for controlling the data interface unit based on the comparison result so as to substantially invalidate / validate the processing of the internal circuit which has already been started with respect to the outside. 2. The semiconductor device according to claim 1, wherein the stored information of said storage means is made variable based on an external access, and said stored information is address information allocated for selecting a chip of a semiconductor integrated circuit. Integrated circuit. 3. The semiconductor integrated circuit according to claim 2, wherein said internal circuit has a memory cell array, and selects a memory cell included in said memory cell array based on an externally supplied address signal.