JP2000260184A - Static ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an initializing time of a holding data of a memory cell by connecting a 1st inverter circuit to a high order power source via a transfer gate for a 1st power source connection control, and connecting a 2nd inverter circuit to the high order power source via a transfer gate for a 2nd power source connection control. SOLUTION: A source terminal of a P-channel transistor of an inverter circuit 2 is connected to a high order power source via a transfer gate 12 for power source connection control, and a P-channel transistor 13 of an inverter circuit 3 is connected to the high order power source via a transfer gate 14 for power source connection control. When a bit line 7 and a bit line 10 are driven at a high level and a low level, respectively, the P-channel transistor 11 of the inverter circuit 2 for driving a connecting point 4 that will change from the high level to the low level is conducting but is disconnected from the high order power source, therefore, the inverter circuit 2 is not driving the bit line 7 at the high level via the transfer gate 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static RA which has an improved initialization time for initializing a memory cell and has improved operability for operating a wide address space at a time.
About M.

[0002]

2. Description of the Related Art FIG. 4 shows a well-known configuration of a typical memory cell in a conventional static RAM. In FIG. 4, the memory cell 100
Is a first inverter circuit 101 that holds stored data.
The input and output of the second inverter circuit 102 are connected to each other, and the connection point between the input of the first inverter circuit 101 and the output of the second inverter circuit 102 is connected to the word line 10.
The bit line 105 on the non-inversion side is transferred via the transfer gate 104 which is controlled to be conductive by the row address signal applied to
And the output of the first inverter circuit 101 and the second
Of the inverter circuit 102 is connected to the word line 1
03 via the transfer gate 106, which is controlled to be conductive by the row address signal applied to the bit line 10 on the inversion side.
7 is connected.

[0005] Such memory cells 100 are arranged in a matrix, for example, as shown in FIG. 5 to form a memory cell array, and memory cells 100 in the same column (column) in the memory cell array are respectively assigned to corresponding write circuits 10.
8, the storage data is applied and written via the non-inversion side bit line 105 and the inversion side bit line 107,
The storage data stored in each memory cell 100 is read out, for example, from a bit line 107 on the inversion side to a bit output signal line 110 via a transfer gate 109 whose conduction is controlled by a column address signal.

In such a static RAM,
The data held in the memory cell 100 when the power is turned on (for example, the potential of the bit line 107 on the inversion side of the memory cell 100) is either the high level or the low level, so the initial value data of the memory cell 100 is The initial value of the stored data was not uniform when viewed as a whole static RAM. Therefore, when the memory cell 100 needs to be initialized (unifiedly set to "1" or "0"), for example, a task of writing predetermined data to a memory cell in an area requiring initialization by software is performed. Was needed.

In such an initialization operation, for example, by simultaneously writing the same data to memory cells in the same column, the operation can be performed quickly. However, in such a case, as shown in FIG. 6, all the memory cells 100 in the same column, that is, all the memory cells 100 connected to the same bit line pair are selected, and one pair of each memory cell 100 is selected. Inverter circuit 10
1 and 102 are connected to the bit lines 105 and 107 via the corresponding transfer gates 104 and 106. In such a state, at the time of power-on, for example, the connection point 111 on the bit line 105 side of many of the memory cells 100 in the same column was at a high level, and the connection point 112 on the bit line 107 side was at a low level. In this case, a low level is supplied to the bit line 105 and a high level is supplied to the bit line 107 by the write circuit 108 to connect the connection point 1 of all the memory cells 100 in the same column.
When the node 11 is initialized to a low level and the connection point 112 is initialized to a high level, the drive capability of one inverter circuit 102 is small on the bit line 105 side transitioning from a high level state to a low level state, but the connection point 111 is set to a high level. The sum of the driving capacities of a large number of inverter circuits 102 driving the memory cell 100 greatly exceeds the driving capacity of the writing circuit 108, and inverts the bit line 105 from the high level to the low level to change the data held in the memory cell 100 from the high level. It has been extremely difficult to rewrite to low level. This means that one write circuit 108 is usually designed on the assumption that a write operation is performed on one memory cell 100, and is designed to have a driving capability of simultaneously rewriting data held in many memory cells 100 in the same column. It was not done.

Therefore, when the storage data of the memory cells 100 is initialized, the write operation is individually performed on each of the memory cells 100 similarly to the normal write operation. Therefore, it takes an enormous amount of time to initialize all of the many memory cells 100, and a delay occurs in processing performed after the initialization.

[0007]

As described above,
In a conventional static RAM, when initializing and unifying storage data that becomes indefinite at power-on, simultaneous writing to many memory cells in the same column is required to speed up the initialization operation. Has been extremely difficult in relation to the driving capability of a plurality of inverter circuits constituting a plurality of memory cells which must be driven by the write circuit. For this reason, the operation of initializing the memory cells has a drawback in that writing is performed individually for each memory cell, and it takes much time.

Also, when erasing unnecessary data at once in a wide address area, it is necessary to perform individual writing in the same manner, thus causing a problem that a long processing time is required.

The present invention has been made in view of the above, and an object of the present invention is to provide a static RAM capable of achieving a reduction in initialization time for initializing data held in a memory cell. It is in.

[0010]

According to a first aspect of the present invention, an input of a first inverter circuit is connected to an output of a second inverter circuit.
The output of the first inverter circuit is connected to the input of the second inverter circuit, and the output of the first inverter circuit is connected to the first bit line via a first transfer gate that is controlled to be conductive by a signal on a word line. A static RAM (random memory) including a memory cell having an output of the second inverter circuit connected to a second bit line via a second transfer gate connected and controlled to be conductive by a signal of the word line; Access memory), the first inverter circuit is connected to a higher power supply via a first power supply connection control transfer gate, and the second inverter circuit is connected via a second power supply connection control transfer gate. It is characterized by being connected to a higher power supply.

According to a second aspect of the present invention, the input of the first inverter circuit and the output of the second inverter circuit are connected,
An output of the first inverter circuit is connected to an input of the second inverter circuit, and an output of the first inverter circuit is connected to a first transfer gate via a first transfer gate controlled to be conductive by a word line signal. The memory cells connected to the bit lines and the output of the second inverter circuit connected to the second bit lines via a second transfer gate controlled to be conductive by the signal of the word lines are arranged in a matrix. In the static RAM, the first inverter circuits of all the memory cells are connected to a high-level power supply via a first power supply connection control transfer gate, and the first inverter circuits are connected via a second power supply connection control transfer gate. The second inverter circuits of all the memory cells are connected to a higher power supply.

According to a third aspect of the present invention, an input of the first inverter circuit is connected to an output of the second inverter circuit,
An output of the first inverter circuit is connected to an input of the second inverter circuit, and an output of the first inverter circuit is connected to a first transfer gate via a first transfer gate controlled to be conductive by a word line signal. The memory cells connected to the bit lines and the output of the second inverter circuit connected to the second bit lines via a second transfer gate controlled to be conductive by the signal of the word lines are arranged in a matrix. In the static RAM, the first inverter circuits of the memory cells in the same column are connected to a higher power supply via a common power supply connection control transfer gate, and the common power supply connection is different from the power supply connection transfer gate. The second inverter circuit of the memory cells in the same column is connected to a higher power supply via a control transfer gate. And it features.

According to a fourth aspect of the present invention, in the static RAM according to the first, second, or third aspect, the first and second power supply connection control transfer gates or the power supply connection control transfer gates in the same column are: One is controlled to be non-conductive when writing data to the memory cell when initializing the memory cell, and the other is controlled to be conductive when data is held in the memory cell.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a memory cell in a static RAM according to an embodiment of the present invention.

In FIG. 1, a memory cell 1 is a CMOS
The input of the inverter circuit 2 made of CMOS and the output of the inverter circuit 3 made of CMOS are connected.
And the input of the inverter circuit 3 are connected to each other. A connection point 4 between the input of the inverter circuit 2 and the output of the inverter circuit 3 is controlled to be conductive by the signal of the word line 5 via the transfer gate 6 on the non-inverting side. 7 and a connection point 8 between the output of the inverter circuit 2 and the input of the inverter circuit 3.
Are connected to a bit line 10 on the inversion side via a transfer gate 9 whose conduction is controlled by a signal on the word line 5. In the memory cell 1, the source terminal of the P-channel transistor 11 of the inverter circuit 2 is connected to a high-level power supply via a power supply connection control transfer gate 12 composed of, for example, a P-channel transistor. Is connected to a high-order power supply via a power supply connection control transfer gate 14 composed of, for example, a P-channel transistor.

In such a configuration, in order to initialize the data held in the memory cell 1 after the power is turned on, when writing is simultaneously performed to a large number of memory cells 1, for example, the non-inverting side bit line 7 is set to a high level. The bit line 10 on the inversion side is driven to a low level to set the connection point 4 to a high level and the connection point 8
Is initialized to a low level (hereinafter, such initialization of the memory cell 1 is referred to as set, and the opposite case is referred to as cleared). First, the power supply connection control transfer gate 12 is turned off, and the inverter circuit is turned off. 2 P-channel transistor 11 is disconnected from the high-level power supply, and in this state, both transfer gates 6 and 9 are changed from the non-conductive state to the conductive state, and the bit line 7 is set to the high level by the write circuit (not shown). 10 is driven to a low level. At this time, the P-channel transistor 11 of the inverter circuit 2 driving the connection point 4 which is going to transition from the high level to the low level is in a conductive state, but is separated from the high-order power supply. This means that the bit line 7 is not driven to the high level via the transfer gate 6. As a result, a collision between the write circuit and the driving force of the inverter circuit 2 of the large number of memory cells 1 can be avoided, and it is possible to easily write simultaneously to the large number of memory cells 1 with the normal write circuit driving capability. Become. When writing is completed and the potentials at the connection points 4 and 8 are determined, the transfer gates 6 and 9 are changed from the conductive state to the non-conductive state, and the inverter circuits 2 and 3 are disconnected from the bit lines 7 and 10. The control transfer gate 12 is returned from the non-conductive state to the conductive state, and the data written in the memory cell 1 is retained.

On the other hand, when the memory cell 1 is cleared by rewriting the connection point 8 of the inversion side bit line 10 from high level to low level, the transfer gate 14 for power supply connection control is replaced with the transfer gate for power supply connection control described above. Conduction control may be performed in the same manner as in step 12.

In such an embodiment, since the collision of the driving force between the write circuit and the memory cell 1 is avoided, it is necessary to simultaneously write to a large number of memory cells 1 with the normal write circuit driving capability. Therefore, the initialization time for setting or clearing the memory cell 1 after the power is turned on or after the reset is shortened, and the initialization can be performed quickly. As a result, for example, processing that requires memory initialization after system startup can be performed more quickly than in the past, and memory initialization is completed after system startup as in the conventional case. For a while, the inconvenience that the system cannot perform the processing is eliminated.

FIG. 2 is a diagram showing a configuration of a static RAM according to an embodiment of the present invention.

In FIG. 2, this embodiment is characterized in that the memory cells 1 shown in FIG. 1 are arranged in a matrix to form a memory cell array, and the bit line 7 on the non-inverting side shown in FIG. The transfer gate 12 for power supply connection control and the transfer gate 14 for power supply connection control on the inversion side bit line 10 side are common to all the memory cells 1, and the memory cells 1 in each column write corresponding write data. Writing is performed by the circuit 21, and the data stored in the memory cells 1 in each column is changed to the bit line 1 on the inversion side.
Column transfer gates 22 corresponding to 0 to 0 respectively
And the data is read out to the bit output signal line 23 via the bit line.

In such an embodiment, the transfer gate 12 or 14 for power supply connection control is controlled from the conductive state to the non-conductive state, and all the memory cells 1 are selected to drive the bit line pair by the write circuit 21. This makes it possible to simultaneously perform a write operation on all the memory cells 1 in one cycle, and to quickly set or clear all the memory cells 1. For example, the write time of one memory cell is set to 1
(μsec), and when initializing memory cells at addresses of 1K (1024 bits), if writing is performed individually to each memory cell as in the related art, 1
In contrast to the case where a time of (msec) or more is required, in this embodiment, the write time of one memory cell is about 1 (μsec), which is approximately the same as that of one memory cell, so that the initialization time can be significantly reduced. . As a result, the system can quickly enter the actual processing from the initial setting of the memory, and can sufficiently cope with an application or the like that requires high-speed control.

FIG. 3 is a diagram showing a configuration of a static RAM according to an embodiment of the present invention.

In FIG. 3, the feature of this embodiment is that, in the configuration of the memory cell array shown in FIG. 2, the bit line 7 on the non-inversion side common to the memory cells 1 in each column is provided for each column. A power connection control transfer gate 12 and a power connection control transfer gate 14 for the inverting bit line 10 are provided.
2 is controlled in common, and the transfer gates 14 for power supply connection control of the inversion side bit line 10 are controlled independently and individually. This is the same as the configuration shown in FIG.

In such an embodiment, the set initialization can be performed simultaneously for all the memory cells 1 by commonly controlling the transfer gate 12 for controlling the power supply connection on the non-inverting side, On the other hand, by individually controlling the conduction of the transfer gate 12 for controlling the power supply connection on the inversion side, it is possible to simultaneously initialize the clearing of the memory cells 1 in the same column on a column basis. The power supply connection control transfer gates 12 of the non-inverting side bit lines 7 may be independently and independently controlled for conduction.
In this case, it is possible to initialize the set of the memory cells 1 at the same time in column units. As described above, since initialization can be performed in units of columns, the degree of freedom of initialization is increased, and even when it is desired to initialize a partial address area of the memory during a job execution process in the system, it can be performed in a short time. When the initialization of the memory is completed, the influence on the processing being executed can be minimized, and the restriction on the software accompanying the memory initialization processing can be reduced.

In the above-described embodiment, the inverter circuits 2 and 3 of the memory cell 1 are inverter circuits using a resistor or a depletion-type FET (field effect transistor) as a load element even if they are not of a CMOS configuration. You may. The transfer gates 12 and 14 for controlling power supply connection are N-channel transistors in order to avoid complication of the manufacturing process when the memory cell 1 is composed of N-channel transistors. Is also good.

[0027]

As described above, according to the first aspect of the present invention, the power supply connection control transfer gate, which is controlled to be conductive when the memory cell is initialized, is connected between the inverter circuit of the memory cell and the higher power supply. With this configuration, it is possible to simultaneously write data into a large number of memory cells, and it is possible to greatly reduce the initialization time of the memory cells. In addition, since unnecessary data during processing can be erased at a time, the load on software can be reduced.

According to the second aspect of the present invention, the power supply connection control transfer gate according to the first aspect is used in common for all the memory cells of the memory cell array. Can be initialized at the same time, and the initialization time of the memory cell can be greatly reduced.

According to the third aspect of the present invention, the power supply connection control transfer gate according to the first aspect is shared for each column of the memory cell array, so that the memory cells of the memory cell array are simultaneously initialized in units of columns. The initialization time of the memory cell can be significantly reduced, and the degree of freedom of the initialization process can be increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a memory cell of a static RAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a static RAM according to an embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a memory cell of a static RAM according to an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a memory cell of a conventional static RAM.

5 is a diagram showing a configuration of a conventional static RAM using the memory cells shown in FIG.

6 is a diagram showing a state of a write operation on a plurality of memory cells shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell 2, 3 Inverter circuit 4, 8 Connection point 5 Word line 6, 9 Transfer gate 7, 10 Bit line 11, 13 P-channel transistor 12, 14, Power supply connection control transfer gate 21 Write circuit 22 Column transfer gate 23 bits Output signal line

Claims (4)

[Claims] 1. An input of a first inverter circuit and an output of a second inverter circuit are connected, an output of the first inverter circuit and an input of the second inverter circuit are connected, and a signal of a word line is used. An output of the first inverter circuit is connected to a first bit line via a first transfer gate whose conduction is controlled, and the output of the first inverter circuit is supplied via a second transfer gate which is controlled by a signal on the word line. In a static RAM (random access memory) having a memory cell in which the output of the second inverter circuit is connected to a second bit line, the first inverter is connected via a first power supply connection control transfer gate. The circuit is connected to a higher power supply, and the second inverter circuit is connected to the higher power supply via a second power supply connection control transfer gate. Static RAM characterized by comprising Te. 2. An input of a first inverter circuit and an output of a second inverter circuit are connected. An output of the first inverter circuit and an input of the second inverter circuit are connected. An output of the first inverter circuit is connected to a first bit line via a first transfer gate whose conduction is controlled, and the output of the first inverter circuit is supplied via a second transfer gate which is controlled by a signal on the word line. In a static RAM in which memory cells each having an output of the second inverter circuit connected to a second bit line are arranged in a matrix, a memory cell of all the memory cells is connected via a first power supply connection control transfer gate. The first inverter circuit is connected to a higher power supply, and the second inverter of all the memory cells is connected via a second power supply connection control transfer gate. Static RAM road is characterized by comprising connected to the high potential power supply. 3. An input of the first inverter circuit and an output of the second inverter circuit are connected, and an output of the first inverter circuit and an input of the second inverter circuit are connected. An output of the first inverter circuit is connected to a first bit line via a first transfer gate whose conduction is controlled, and the output of the first inverter circuit is supplied via a second transfer gate which is controlled by a signal on the word line. In a static RAM in which the memory cells each having the output of the second inverter circuit connected to the second bit line are arranged in a matrix, the memory cells in the same column are connected via a common power supply connection control transfer gate. The first inverter circuit is connected to a high-order power supply, and includes a common power supply connection control transfer gate different from the power supply transfer gate. Static R of the second inverter circuit of the memory cell of the same column and characterized by comprising connected to the high potential power supply
AM. 4. The first and second power supply connection control transfer gates or the power supply connection control transfer gates in the same column write data to the memory cell when one of the transfer gates initializes the memory cell. 4. The static RAM according to claim 1, wherein the static RAM is controlled to be in a non-conductive state at a time, and both are controlled to be in a conductive state when data is held in the memory cell.