HU190282B - Arrangement for quick solving numerous logic fenction - Google Patents

Abstract

In the process of the present invention, a memory is addressed, the memory address is stored until the execution of the instruction is completed, an instruction and an additional address are stored from the stored memory address, the address of the variable is determined with the additional address or stored address, and the variable is read and executed. the operation corresponding to the instruction. The arrangement according to the invention comprises a microprocessor (MP), two memories (M1, M2) and a timer / control logic (IVL) connected to the other units. The output (A) of the microprocessor (MP) program counter is connected via a container (TI) to the input of the first memory (M1). Command rail (U) and address bar (CMl) are connected to the first memory (M1). The first access / disarming unit (E1) and / or code converter (PR) is connected between the instruction rail (U) and the microprocessor (MP) data bus (D). The address bar (CMl) is connected to a second enable / disable unit (E2) with the data bus (D) and a second address (CM2) connected to one of the inputs of an AND / OR logic (EV). The other input of the AND / OR logic (EV) is connected to the output of the container (TI) (C). The output of the AND / OR logic (EV) is connected to the input of the second memory (M2). The second memory (M2) is connected to the data bus (D) via the third enable / disable unit (E3). -1-

Description

The present invention relates to an arrangement for rapidly solving a large number of logical functions.

Since the mid-1960s, free-programmable controllers (PLCs) have been increasingly used in place of conventional relay control technology, due to their many advantages. Their appearance and rapid spread was made possible by the development of cheap LSI circuits (microprocessors, memories, etc.).

The internal structure of PLCs was based on the organization of the well-known single-processor computer; It consists of a central unit, a memory unit and an input / output unit. However, a significant difference from universal microcomputers is that the PLC has to operate reliably in a noisy industrial environment over a wide temperature range and the number of input / output units increases significantly (there may be thousands). The programming of traditional computers is facilitated by advanced languages. Similar to this is the special programming language of PLC equipment, which is adapted to the expertise of control technicians. The minimum functions that can be programmed with PLCs are the basic logic functions, the delayers and the counters. The functions to be implemented at each PLC depend to a large extent on the choice of central unit, the organization of the operation.

The operation of the programmable logic controllers is also determined by the design of the central unit. Logic processors, microprocessors, or mixed systems are most commonly used in central units.

Logical processors are generally composed of logic units and timer / control logic and are supplemented with program counter, memory, and input / output unit addressing logic. During operation, the program counter addresses the memory, the output of which displays simultaneously the variable address and the (logical) type of the instruction. The variable address value selects the appropriate input or output variable, which may be stored in memory. The selected variable passes through a one-bit data channel to the logical processor, which performs the operation defined by the instruction code. Thus, in this arrangement, the address of the program counter, which selects the next instruction of the user program store and the address of the variable, the instruction code and the address of the variable, and thus the value of the variable with little delay, is available at the same time. Thus, in practice, a logical instruction can be executed during a cycle. Even the simplest circuit design achieves 1 ps instruction execution. In addition, implementing the PLC programming language is easy. The disadvantage of this solution is that additional circuits are required to implement the delay counting function, and their handling is difficult.

Microprocessors are most often used in PLCs because they have low-cost hardware / software development tools and application technology experience. A more intelligent set of instructions and internal organization of microprocessors allows for universal tasks.

Data is transmitted between the microprocessor and the memory or peripheral via the data channel, which is timed or controlled by the signals on the control channels to a location or location selected by the information on the address channel. This organization is slower than the previous one, but it requires less wires (rails) for data traffic, which is advantageous for common data processing tasks. However, for PLCs, the type of task implies that many variables have to be performed with relatively low complexity, and thus this organization is no longer beneficial.

Most microprocessor systems use an interpreter operating program that interprets and executes a step-by-step PLC program stored in user memory.

As a consequence of the above, the disadvantage of this solution is that with conventional microprocessors the solution of a logical function is 50-100 ps, so that the operation is very slow. A further disadvantage is that it is quite expensive to write an operating program.

In order to reduce the cycle time of PLCs, mixed (dual-processor) systems are also used in which the logic processor solves the logic functions, while other tasks (delay, counting, error checking, communication with other units, etc.) are entrusted to a microprocessor. However, due to the use of the two processors, this system is more expensive, more complicated, and it is more difficult to coordinate design and operation.

It is an object of the present invention to provide an arrangement that accelerates the execution of a large number of logical tasks primarily required in PLCs.

The arrangement according to the invention comprises a microprocessor, two memories, and a timing / control logic connected to the other units. The output of the microprocessor program counter is connected to a first memory input via a storage. The first memory is connected to an instruction rail and an address rail. A first enable / disable unit and / or code converter is connected between the instruction bus and the data bus of the microprocessor. The address bus is connected through a second enable / disable unit to the data bus and through a second address bus to one of the inputs of an AND / OR logic. The other input of the AND / OR logic is connected to the output of the container. The output of the AND / OR logic connects to the second memory input. The second memory is connected to the data bus via a third enable / disable unit.

The invention will now be described in more detail with reference to embodiments and drawings. In the drawings it is

FIG. 1 is a block diagram of an embodiment of the embodiment of the present invention, and FIG

Figure 2 is a schematic diagram of a memory block of another embodiment.

In the embodiment of Figure 1, the A output of the MP microprocessor program counter is coupled to the TI memory and the IVL timer / control logic. The C output of the TI container is connected to the MI memory located in the M me-21.190 282 block of memory, one of the inputs to the EV AND / OR logic and the M3 memory. The first instruction memory M1 is connected to the U instruction bus and the CM1 address bus. A first E1 enable / disable unit and a PR code converter are coupled between the U command bus and the data bus D of the MP microprocessor, also connected to the IVL timer / control logic. The address bus CM1 is connected via a second enable / disable unit E2 to the data bus D and a second address bus CM2 to the EV AND / OR logic and one of the inputs of the MUX multiplexer. The output of the EV AND / OR logic is connected to the input of a second M2 memory. The M2 memory 'is connected to the other input of the MUX multiplexer. The MUX multiplexer is connected to the D bus. The memory M2 is also connected to the data bus D via a third enable / filler unit E3 and is connected to the ÁCS data channel via a fourth enable / disable unit E4. The M3 memory is also connected to the D bus. The IVL timer / control logic communicates with each of the units shown in Figure 1 and a fifth E5 enable / disable unit with the CCS address channel.

In the method of the present invention, memory is indirectly addressed by accessing variables stored in the M2 memory. When executing an instruction, in the first (fetch) cycle, the program counter address issued by the MP microprocessor at output A is stored in the TI memory. With the information displayed at the output C of the TI memory, the instruction code stored in memory M1 is selected to be transmitted to the instruction rail U and the additional address associated with the instruction which is placed on the CM1 and CM2 addresses. With this additional address, or with the address stored in the TI container, the address of the variable is determined by the EV AND / OR logic. The variable is then read from the M2 memory and executed in the MP microprocessor according to the instruction.

Thus, the selection of the variable begins already in the fetch loop, since the additional address read from the Μ1 memory is controlled by the M2 memory and the MUX multiplexer address input. In the second cycle of the instruction, after the program counter advances, the MP microprocessor provides additional information to output A, however, the IVL timer / control logic disables its loading into the TI memory until the execution of the instruction is completed, leaving the previous program counter content in the TI memory. Meanwhile, the IVL timer / control logic enables the MUX multiplexer to establish a connection between the M2 memory and the D bus. Since the value of the program counter has increased by one during execution of the instruction, the execution of the following instruction can begin immediately after the execution of the instruction by allowing IVL timer / control logic to allow new information to be entered into the TI repository.

The function of the MUX multiplexer is to generate the complement 1 of the input or output variables, depending on the instruction, and to select the variable in an "n" bit organized M2 memory. In the case of single-bit organized M2 memory, it only performs complementary training, but may be omitted from this organization. The PR code converter, preferably a PROM, generates an "understandable" instruction from the instruction code to the MP microprocessor, which the MP microprocessor samples. If the instruction code on the U instruction rail has a bit number equal to the MP microprocessor word length, code conversion is not required so that the instruction code can pass through the E bus on the D bus. M3 memory is used to store firmware and other programs. The E1, E2 and E3 enable / disable units allow inspection and modification of each memory compartment, while the E4 and E5 enable / disable units communicate between the M2 memory and the input / output units connected to the ÁCS data channel and CCS address channel. Each unit can be implemented from a standard circuit kit.

Figure 2 shows another embodiment of the memory block M. Here, memory M1 is connected via a second storage T2 to the instruction bus U and to the second address bus CM2.

Using the layout of Figure 2, direct address logical instructions can be used as above. In doing so, the instruction and the further address are determined from two memory addresses of memory M1, of which only the second is stored until the execution of the instruction. During the execution of an instruction, the information on the output C of the TI memory during the fetch cycle selects from the memory Μ1 an instruction code including an address portion, which is stored in the T2 memory. At the end of the fetch cycle, the address of the program counter increases by one. In the execution cycle, the TI store stores the second memory address, which is read from memory Μ1. Thus, the additional address that appears on the CM2 address bus is read from the first address in memory Μ1 and stored in the T2 repository and the contents of the second addressable compartment ΜI on the CM1 address bus. The address bus CM1 allows access to memory Μ1 via the enable / disable unit E2. In this embodiment, the Enable / Disable E unit is not required. From the U busbar, the instruction code is transmitted to the data bus D via the PR code converter. This system solution improves memory utilization compared to the previous one.

An advantage of the arrangement according to the invention compared to the known solutions is that it greatly speeds up the solution of the large number of logic functions required primarily in PLC equipment.

Claims (3)

Claims An arrangement for rapidly solving a plurality of logic functions comprising a microprocessor and two memories connected to the microprocessor, and a drive / control logic connected to the other units, characterized in that the output (A) of the microprocessor (MP) program counter (A) is is connected to the input of the first memory (M1), to the instruction memory (U) of the first memory (M1) and to the address bus (CM 1) -3.190 282 occupied, first enable / disable unit (E1) and / or code converter (PR) connected between command bus (U) and microprocessor (MP) data bus, address bus (CM1) on second enable / disable unit (E2) is connected to the data bus (D) and through a second address bus (CM 2) to one of the inputs of an AND / OR logic (EV), the other input of the ES / OR logic (EV) to the output of the container (TI) (C) is connected, the output of the AND / OR logic (EV) is connected to the input of the second memory (M2) and the second memory (M2) is connected to the data bus (D) via a third enable / disable unit (E3). An embodiment of the arrangement according to claim 1, characterized in that a multiplexer (MUX) is connected between the data bus (D) and the second address bus (CM2) and the second memory (M2). Arrangement according to claim 1 or 2, characterized in that the first memory (M1) is connected to the instruction bus (U) and the second address bus (CM2) via a second storage (T2).