JPS61159766A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the manufacturing process of a semiconductor device by simultaneously executing a process, in which ions are implanted to an inter- element isolation region in a semiconductor device, and a process in which ions are implanted to an element forming region and a short-channel effect is prevented. CONSTITUTION:When the conditions of ion implantation are determined, energy, a dosage and the range of implantation depth are decided so as to form an impurity profile in a region in which a short channel effect is inhibited sufficiently in an element forming region. Energy, a dosage and the thickness of a LOCOS film are determined so as to simultaneously shape a sufficient impurity profile under a LOCOS8 in a field region. Consequently, even an effect increasing the concentration of a field substrate is displayed in the ion implantation. As a result, the energy of ions, the dosage, the pressure of a field film, implantation depth, etc. are optimized and the method is executed so that an impurity is introduced to the region sufficiently inhibiting the short-channel effect in the element forming region and under the LOCOS8 in the field region. Accordingly, ion implantation has been divided into independent two processes, but the impurity may be treated through one-time ion implantation, thus simplify processes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device. This method can be applied to MOS IC processes, etc.

It can be used to simplify the manufacturing process.

[Prior Art] Conventionally, the following manufacturing method has been adopted in the MOS IC process. That is, as shown in FIG. 2(a), a SiO* film 2' and 5isNall13 are formed on a substrate 1'
' and then remove unnecessary parts to obtain 5iO22 and 5i3N43 as shown in FIG. 2(b).

This portion corresponds to the element formation region 4. At a later stage, ions are implanted into the field region 5 for channel stop to form a high concentration region as shown by the broken line in FIG. 2(C). This ion implantation sets the field region as a region of higher concentration than the rest of the substrate l to the V threshold (v
th, the critical voltage for current to flow). Thereafter, a source region 6 and a drain region 7 are formed as shown in FIG. 2(d). In addition, 8 in the figure is LOGO3,
9 is a polysilicon electrode.

In the conventional technology, in order to reduce the short channel effect, a deep part (
However, ion implantation is performed at a higher concentration than in other parts of the substrate l (the depth differs depending on the case), that is, as shown in FIG.
), a high concentration region is formed under the gate silicon 41, thereby forming a source region 6 and a drain region 7 other than the surface.
This prevents the charge from moving between the two, that is, the short channel effect.

As mentioned above, deep ion implantation is used to reduce the short channel effect in the device formation region 4.
This technique is adopted as a technique for implanting ions at a higher concentration than that of the substrate 1 under the substrate. Therefore, the ion implantation in this case only needs to be carried out under the element formation region 4.Although ion implantation may be carried out over the entire surface, it is also performed for the purpose of implanting into the element formation region 4.

As mentioned above, in the past, ion implantation to suppress the short channel effect of active MO5 was carried out to reduce the vt of field MO5.
Ion implantation for increasing h was performed completely independently. For this reason, ion implantation has to be performed twice, increasing the number of steps.

[Object of the Invention] An object of the present invention is to provide a method for manufacturing a semiconductor device with simplified steps.

[Structure and operation of the invention] In the method for manufacturing a semiconductor device of the present invention, the step of implanting ions into the element isolation region of the semiconductor device is performed at the same time as the step of preventing the short channel effect by implanting ions into the element formation region. conduct.

With this configuration, the ion implantation for preventing the short channel effect can have the effect of the ion implantation for stopping the channel, so that both functions can be achieved by one step of ion implantation. As a result, the process can be simplified.

Note that the above-mentioned element formation region refers to a region where an element is to be formed at an appropriate position in this region, and does not necessarily indicate only the position itself where the element is formed. This area corresponds to the area where the image is applied.

Conventionally, as mentioned above, it was thought that ion implantation should be performed under the element formation region (active region) in order to prevent the short channel effect, and in the end it was considered to be a completely different means from ion implantation into the field region. , this idea was assumed. Therefore, even when ion implantation is performed to prevent the field channel effect, ions are generally implanted into the field region beforehand to increase vth.

Rather, in order to independently set the energy of both ion implantation steps and the a (dose m) of the implanted ion exiting from the middle surface 11i, it has been a fixed idea that the two ion implantation steps should be performed as separate steps.

However, normally the ions in both ion implantations are of the same type,
The energy and dose are not significantly different. Therefore, by optimizing the ion implantation conditions to prevent the short channel effect, it is possible to omit ion implantation in the field region, which was traditionally performed. Optimization of the 0 condition, which has led to the present invention based on knowledge, may be achieved by optimizing the depth and concentration of impurities in the element formation region and the isolation region (active region and field region), for example.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
This will be explained using the schematic diagram shown in C).

This example is a case where the present invention is applied to an Nch MOS, and is the same up to the middle as the conventional method explained in FIG. That is, the process is the same up to the stage of ion implantation into the field region shown in FIG. 2(b), but in this example,
This ion implantation is not performed. Therefore, the state shown in FIG. 1(A) is different from the corresponding conventional state shown in FIG. 2(C) in which no ions are implanted and there is no high ion concentration area. .

Next, in this embodiment, as shown in FIG. 1(b), ion implantation is performed.
It can be carried out in the KeV range, and in one example it is 200KeV.
I went there. This is set at a high energy so that it can be injected down to 5 iOz41, but it can be controlled depending on the individual target. Through this ion implantation, as shown in Figure 1 (
As shown in C), ion implantation into a deep part under the element formation region 4 (ion implantation into the part shown by 4a in the figure) and ion implantation into the part under the field region 5 (into the part shown by 5a in the figure) is performed. (ion implantation) is achieved simultaneously in one step.

When determining the conditions for this ion implantation, first, the energy, dose amount, and implantation depth range are determined so that an impurity profile is created in a region where the short channel effect is sufficiently suppressed in the element formation region. At the same time, in the field region, the energy, dose, LOCO5Jf!
Determine the thickness. This allows the ion implantation to also have the effect of increasing the field substrate concentration.

In this way, in the element formation region, the short channel effect is sufficiently suppressed, and in the field region, the LOCO5
By optimizing the ion energy, dose, field film pressure, implantation depth, etc. so that the impurity enters sufficiently under a, the conventional ion implantation process, which was divided into two independent steps, can now be performed in one step. can now be treated with ion implantation,
The process has been simplified.

In this example, ion implantation was performed after LOCOS, but ion implantation may be performed before LOCO3, as long as the ion implantation can be performed at a time when two effects can be achieved simultaneously.

Naturally, the present invention is not limited to the embodiments described above.

[Effects of the Invention] As described above, according to the present invention, there is an effect that the steps in the method of manufacturing a semiconductor device can be simplified.

[Brief explanation of drawings]

FIGS. 1A to 1C are diagrams showing an embodiment of the present invention in the order of steps. FIGS. 2(a) to 2(f) are diagrams showing five conventional techniques in order of process. DESCRIPTION OF SYMBOLS 1... Substrate, 4... Element formation region, 5... Field region, 8... Element isolation region (LOGO3).

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device, characterized in that the step of implanting ions into the element isolation region of the semiconductor device is carried out simultaneously with the step of preventing short channel effects by implanting ions into the element formation region.