KR100263454B1 - Semiconductor device manufacture method - Google Patents

Semiconductor device manufacture method Download PDF

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KR100263454B1
KR100263454B1 KR1019970073428A KR19970073428A KR100263454B1 KR 100263454 B1 KR100263454 B1 KR 100263454B1 KR 1019970073428 A KR1019970073428 A KR 1019970073428A KR 19970073428 A KR19970073428 A KR 19970073428A KR 100263454 B1 KR100263454 B1 KR 100263454B1
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well
region
profiled
well region
ion
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KR1019970073428A
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Korean (ko)
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KR19990053738A (en
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오재근
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H01J37/3171—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation for ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Abstract

PURPOSE: A method for manufacturing semiconductor devices is provided to prevent location of an N type dopant between an N well region and a P channel field stop implant region and decrease in the concentration using As ions being an N type dopant upon formation of a profiled N well region. CONSTITUTION: A method for manufacturing semiconductor devices forms a field oxide film for device separation on a semiconductor substrate. A profiled N well region sequentially having an N well implant region(56) and a P channel field stop implant region(58) is formed at a location where an N well region will be formed in the semiconductor substrate, using an ion implanter. A profiled P well region sequentially having a P well implant region(62), a medium P well implant region(64) and an N channel field stop implant region(66) is formed at a location where a P well region will be formed in the semiconductor substrate, using the ion implanter. The entire surface of the structure is experienced by thermal process to activate the profiled N well region and the profiled P well region.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 고에너지 이온주입기를 이용하여 N형 도펀트인 비소(Arsenic)이온을 주입하여 프로파일드(profiled) 웰영역을 형성함으로써 소자의 생상수율을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and to implanting Arsenic ions, which are N-type dopants, using a high energy ion implanter to form a profiled well region, thereby improving the production yield of the device. It is about.

도 1a 내지 도 1e 는 종래 기술에 따른 반도체 소자의 제조공정도이다.1A to 1E are manufacturing process diagrams of a semiconductor device according to the prior art.

먼저, 반도체 기판(10) 상부에 소자분리를 위한 필드산화막(12)을 형성한다.(도 1a 참조)First, a field oxide film 12 for device isolation is formed on the semiconductor substrate 10 (see FIG. 1A).

다음, 상기 구조에서 임플란트 공정을 실시하지 않는 영역에 감광막(14)을 도포하여 N웰 임플란트 마스크 공정을 진행한 다음, 고에너지 이온주입기를 통해 포스포러스(phosphorus) 이온을 주입하여 N웰 임플란트영역(16)과 중간 N웰 임플란트영역(18), P채널 필드스톱(field stop) 임플란트영역(20)을 순차적으로 형성하여 프로파일드 N웰영역이 형성된다.(도 1b 참조)Next, in the above structure, the photoresist film 14 is applied to a region where the implant process is not performed, and an N well implant mask process is performed, and then phosphorus ions are implanted through a high energy ion implanter to implant the N well implant region ( 16), the intermediate N well implant region 18, and the P-channel field stop implant region 20 are sequentially formed to form a profiled N well region (see FIG. 1B).

그 다음, 상기 N웰 임플란트 마스크용 감광막(14)을 제거한 후 다시 감광막(22)를 도포하여 P웰 임플란트 마스크 공정을 진행한 다음, 고에너지 이온주입기를 통해 보론(boron)이온을 주입함으로써 P웰 임플란트영역(24)과, 중간 P웰 임플란트영역(26), N채널 필드 스톱 임플란트영역(28)을 순차적으로 형성하여 프로파일드 P웰영역을 형성시킨다.(도 1c 참조)Then, after removing the photoresist film 14 for the N well implant mask, the photoresist film 22 is applied again to perform a P well implant mask process, and then P-well is injected by injecting boron ions through a high energy ion implanter. The implant region 24, the intermediate P well implant region 26, and the N-channel field stop implant region 28 are sequentially formed to form a profiled P well region (see FIG. 1C).

다음, N웰 임플란트 마스크용 감광막(22)를 제거한 후 프로파일드 N웰영역(30)과 P웰영역(32)을 열처리 과정을 통해 활성화한다.(도 1d 참조)Next, after removing the photoresist film 22 for the N well implant mask, the profiled N well region 30 and the P well region 32 are activated through a heat treatment process (see FIG. 1D).

그 다음, N형 및 P형 반도체 기판(10) 상부에 게이트산화막(34) 및 폴리실리콘층을 패터닝하여 게이트전극(36)을 각각 형성한 다음, P형 불순물과 N형 불순물을 이온주입하여 상기 게이트전극(36) 양측의 반도체 기판(10)에 소오스/드레인영역(38)을 형성한다.(도 1e 참조)Next, the gate oxide layer 34 and the polysilicon layer are patterned on the N-type and P-type semiconductor substrate 10 to form a gate electrode 36, and then ion implantation of P-type impurities and N-type impurities is performed. Source / drain regions 38 are formed in the semiconductor substrate 10 on both sides of the gate electrode 36 (see FIG. 1E).

또한, 도 2는 종래 기술에 따라 프로파일드 N웰영역을 형성 하였을때 N형 도펀트의 깊이와 농도를 이차이온 질량분석기로 분석한 도표를 나타내는데, 고에너지 이온주입기를 통해 포스포러스 이온을 주입하여 프로파일드 N웰 영역을 형성후의 도표이다.In addition, FIG. 2 shows a chart in which the depth and concentration of an N-type dopant are analyzed by a secondary ion mass spectrometer when a profiled N well region is formed according to the prior art. This is the plot after de N well region formation.

도 3은 프로파일드 N웰영역을 열처리시 N형 도펀트의 농도변화를 이차이온 질량분석기로 분석한 도표이다.3 is a chart in which the concentration change of the N-type dopant during heat treatment of the profiled N well region is analyzed using a secondary ion mass spectrometer.

상기와 같은 종래 기술에 따르면, 도 2 및 도3에 도시된 바오 같이 포스포러스이온을 이용하여 프로파일 N웰을 형성시킬때 중간 N웰 임플란트의 에너지와 주입량이 적당하지 않으면 N웰과 P채널 필드스톱 사이의 N형 도펀트의 위치와 농도가 달라져서 소자의 특성에 민감하게 영향을 주는 P채널 필드스톱영역에도 영향을 미쳐 접합누설전류의 증가, 접합파괴 전압값의 감소 등의 요인이 되고 있을뿐만 아니라 고에너지 이온주입에 의한 프로파일드 웰 장점중 하나인 도펀트층의 위치와 농도를 독립적으로 형성할 수 있는 장점이 사라지는 문제점이 발생된다.According to the prior art as described above, when forming the profile N well using phosphorus ions as shown in Figs. 2 and 3, if the energy and injection amount of the intermediate N well implant are not appropriate, the N well and the P-channel field stop The location and concentration of the N-type dopant in between affects the P-channel field stop region, which affects the characteristics of the device sensitively, resulting in an increase in junction leakage current and a decrease in junction breakdown voltage. There is a problem in that the advantage of independently forming the position and concentration of the dopant layer, which is one of the advantages of the profiled well by the ion implantation, is lost.

그리고, 가령 중간 N웰 임프란트 공정을 생략한다면 N웰과 P채널 필드스톱 사이의 N형 도펀트층이 존재하지 않은 문제점이 발생된다.For example, if the intermediate N well implant process is omitted, there is a problem that there is no N-type dopant layer between the N well and the P-channel field stop.

이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 프로파일드 N웰영역 형성시 N형 도펀트인 As 이온을 사용함으로써 N웰영역과 P채널 필드스톱 임플란트영역 사이의 N형 도펀트의 위치와 농도 저하를 방지하여 소자의 생산 수율을 향상시키는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, and by using As ion, which is an N-type dopant, when forming a profiled N-well region, the position and concentration of the N-type dopant between the N-well region and the P-channel field stop implant region are reduced. It is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents and improves the production yield of the device.

도 1a 내지 도 1e 는 종래 기술에 따른 반도체 소자의 제조공정도1a to 1e is a manufacturing process diagram of a semiconductor device according to the prior art

도 2는 종래 기술에 따라 프로파일드 N웰영역을 형성 하였을때 N형 도펀트의 깊이와 농도를 이차이온 질량분석기로 분석한 도표2 is a chart in which the depth and concentration of an N-type dopant are analyzed by a secondary ion mass spectrometer when a profiled N well region is formed according to the related art.

도 3은 종래 기술에 따라 프로파일드 N웰영역을 열처리시 N형 도펀트의 농도변화를 이차이온 질량분석기로 분석한 도표Figure 3 is a chart analyzing the concentration change of the N-type dopant when the heat treatment of the profiled N well region in accordance with the prior art with a secondary ion mass spectrometer

도 4a 내지 도 4e 는 본 발명에 따른 반도체 소자의 제조공정도4a to 4e is a manufacturing process diagram of a semiconductor device according to the present invention

도 5는 본 발명에 따라 프로파일드 N웰영역을 형성 하였을때 N형 도펀트의 깊이와 농도를 이차이온 질량분석기로 분석한 도표5 is a chart in which the depth and concentration of an N-type dopant are analyzed by a secondary ion mass spectrometer when a profiled N well region is formed according to the present invention.

도 6은 본 발명에 따라 프로파일드 N웰영역을 열처리시 N형 도펀트의 농도변화를 이차이온 질량분석기로 분석한 도표6 is a chart in which the concentration change of the N-type dopant when the heat treatment of the profiled N well region in accordance with the present invention by a secondary ion mass spectrometer

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10, 50 : 반도체 기판 12, 52 : 필드산화막10, 50: semiconductor substrate 12, 52: field oxide film

14, 54 : 감광막 16, 56 : N웰 임플란트영역14, 54 photosensitive film 16, 56: N well implant region

18 : 중간 N웰 임플란트영역 20, 58 : P채널 필드스톱 임플란트영역18: Middle N well implant area 20, 58: P-channel field stop implant area

24, 62 : P웰 임플란트영역 26, 64 : 중간 P웰 임플란트영역24, 62: P well implant region 26, 64: Intermediate P well implant region

28, 66 : N채널 필드 스톱 임플란트영역 30, 68 : N웰영역28, 66: N-channel field stop implant area 30, 68: N well area

32, 70 : P웰영역 34, 72 : 게이트산화막32, 70: P well region 34, 72: gate oxide film

36, 74 : 게이트전극 38, 76 : 소오스/드레인영역36, 74: gate electrodes 38, 76: source / drain regions

상기 목적을 달성하기 위해 본 발명에 따르면,According to the present invention to achieve the above object,

반도체 기판 상부에 게이트산화막과, 게이트전극, 소오스/드레인영역을 구비하는 반도체 소자의 제조공정에 있어서;A manufacturing method of a semiconductor device having a gate oxide film, a gate electrode, and a source / drain region on a semiconductor substrate;

반도체 기판 상부에 소자분리를 위한 필드산화막을 형성하는 공정과,Forming a field oxide film on the semiconductor substrate for device isolation;

상기 반도체 기판에서 N웰영역으로 예정된 부위에 이온주입기를 이용하여 순차적으로 N웰 임플란트영역 및 P채널 필드스톱 임플란트영역을 구비하는 프로파일드 N웰영역을 형성하는 공정과,Forming a profiled N well region having an N well implant region and a P-channel field stop implant region sequentially using an ion implanter at a portion of the semiconductor substrate, the ion well implanter;

상기 반도체 기판에서 P웰영역으로 예정된 부위에 이온주입기를 이용하여 순차적으로 P웰 임플란트영역과, 중간 P웰 임플란트영역, N채널 필드 스톱 임플란트영역을 구비하는 프로파일드 P웰영역을 형성하는 공정과,Forming a profiled P well region having a P well implant region, an intermediate P well implant region, and an N-channel field stop implant region in sequence using an ion implanter at a predetermined portion of the semiconductor substrate as a P well region;

상기 구조의 전표면을 열처리하여 상기 프로파일드 N웰영역 및 프로파일드 P웰영역을 활성화시키는 공정을 포함한다.Heat treating the entire surface of the structure to activate the profiled N well region and the profiled P well region.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 4a 내지 도 4e 는 본 발명에 따른 반도체 소자의 제조공정도이다.4A to 4E are manufacturing process diagrams of a semiconductor device according to the present invention.

먼저, 반도체 기판(50) 상부에 소자분리를 위한 필드산화막(52)을 형성한다.(도 4a 참조)First, a field oxide film 52 for device isolation is formed on the semiconductor substrate 50 (see FIG. 4A).

다음, 상기 구조에서 임플란트 공정을 실시하지 않는 영역에 밀도가 1 ∼ 10 g/cm2인 감광막(54)을 이용하여 N웰 임플란트 마스크 공정을 진행한 다음, 고에너지 이온주입기를 통해 비소(As) 이온을 주입하여 N웰 임플란트영역(56)과 P채널 필드스톱(field stop) 임플란트영역(58)을 순차적으로 형성하여 프로파일드 N웰영역이 형성된다.Next, an N well implant mask process is performed using a photosensitive film 54 having a density of 1 to 10 g / cm 2 in a region where the implant process is not performed in the structure, and then arsenic (As) through a high energy ion implanter. By implanting ions, the N well implant region 56 and the P-channel field stop implant region 58 are sequentially formed to form a profiled N well region.

이 때, 상기 N웰 임플란트영역(56)에 주입되는 이온주입량은 5×1012∼ 1×1414ions/cm2이고, 이온주입에너지는 1 ∼ 3 MeV 이다.At this time, the amount of ion implanted into the N well implant region 56 is 5 × 10 12 to 1 × 14 14 ions / cm 2 , and the ion implantation energy is 1 to 3 MeV.

또한, 고에너지 이온주입기를 통해 P채널 필드스톱 임플란트영역(58)에 주입되는 이온으로 As 이온과 P이온이 사용되며, 이온주입량은 1×1012∼ 5×1413ions/cm2이고, As이온 일때 이온주입에너지는 450 ∼ 650 KeV 이며, P이온 일때 이온주입에너지는 200 ∼ 300 KeV 이다.(도 4b 참조)In addition, As ions and P ions are used as ions to be injected into the P-channel field stop implant region 58 through the high energy ion implanter, and the ion implantation amount is 1 × 10 12 to 5 × 14 13 ions / cm 2 , The ion implantation energy is 450 to 650 KeV for ions and the ion implantation energy is 200 to 300 KeV for P ions (see FIG. 4B).

그 다음, 상기 N웰 임플란트 마스크용 감광막(54)을 제거한 후 다시 감광막(60)를 도포하여 P웰 임플란트 마스크 공정을 진행한 다음, 고에너지 이온주입기를 통해 보론(boron)이온을 주입함으로써 P웰 임플란트영역(62)과, 중간 P웰 임플란트영역(64), N채널 필드 스톱 임플란트영역(66)을 순차적으로 형성하여 프로파일드 P웰영역을 형성시킨다.(도 4c 참조)Next, after removing the N well implant mask photoresist film 54 and applying the photoresist film 60 again, the P well implant mask process is performed, and P wells are injected by injecting boron ions through a high energy ion implanter. The implant region 62, the intermediate P well implant region 64, and the N-channel field stop implant region 66 are sequentially formed to form a profiled P well region (see FIG. 4C).

다음, P웰 임플란트 마스크용 감광막(60)를 제거한 후 프로파일드 N웰영역(68)과 P웰영역(70)을 열처리 과정을 통해 활성화한다.Next, the P well implant mask photoresist layer 60 is removed, and then the profiled N well region 68 and the P well region 70 are activated by heat treatment.

이 때, 상기 열처리시 로(furnace)나 RTP 장비를 사용하는데 로장비를 사용시 온도는 900 ∼ 1000℃ 이고, 시간은 30분 ∼ 1시간의 조건에서 실시하고, RTP장비를 사용시 온도는 900 ∼ 1100℃ 이고, 시간은 30초 ∼ 1분의 조건에서 실시한다.(도 1d 참조)At this time, the furnace is used for furnace (furnace) or RTP equipment when using the furnace equipment temperature is 900 ~ 1000 ℃, time is carried out under the conditions of 30 minutes to 1 hour, when using the RTP equipment temperature is 900 ~ 1100 It is degree C and time is performed on conditions of 30 second-1 minute. (Refer FIG. 1D)

그 다음, N형 및 P형 반도체 기판(50) 상부에 게이트산화막(72) 및 폴리실리콘층을 패터닝하여 게이트전극(74)을 각각 형성한 다음, P형 불순물과 N형 불순물을 이온주입하여 상기 게이트전극(74) 양측의 반도체 기판(50)에 저농도 소오스/드레인영역(76)을 형성한다.(도 4e 참조)Next, the gate oxide film 72 and the polysilicon layer are patterned on the N-type and P-type semiconductor substrate 50 to form a gate electrode 74, and then ion implantation of P-type impurities and N-type impurities is performed. Low concentration source / drain regions 76 are formed in the semiconductor substrate 50 on both sides of the gate electrode 74. (See FIG. 4E.)

도 5는 본 발명에 따라 고에너지 이온주입기를 통해 비소 이온을 주입하여 프로파일드 N웰영역을 형성 하였을때 N형 도펀트의 깊이와 농도를 이차이온 질량분석기로 분석한 도표를 나타내며, 도 6은 프로파일드 N웰영역을 열처리시 N형 도펀트의 농도변화를 이차이온 질량분석기로 분석한 도표를 나타낸다.FIG. 5 shows a chart in which a depth and concentration of an N-type dopant are analyzed by a secondary ion mass spectrometer when implanted arsenic ions through a high energy ion implanter to form a profiled N well region, and FIG. 6 is a profile. The graph shows the change in concentration of N-type dopant when the N-well region is heat treated by secondary ion mass spectrometry.

도 5와 6에 도시된 바와 같이, 프로파일드 N웰영역을 형성시킬때 N형 도펀트의 이온으로서 P이온 대신 As이온을 사용함으로써 N웰영역과 P채널 필드스톱 임플란트영역 사이의 N형 도펀트의 위치와 농도 저하를 효과적으로 해결할 수 있다는 것을 알수 있다.5 and 6, the position of the N-type dopant between the N-well region and the P-channel field stop implant region by using As ions instead of P ions as the ions of the N-type dopant when forming the profiled N-well region. It can be seen that it is possible to effectively solve the decrease in concentration.

상기한 바와같이 본 발명에 따르면, 프로파일드 N웰영역 형성시 N형 도펀트인 As 이온을 사용함으로써 N웰영역과 P채널 필드스톱 임플란트영역 사이의 N형 도펀트의 위치와 농도 저하를 효과적으로 해결함과 더불어 농도 저하분을 보상하기 위해 실시하는 이온주입공정을 생략할 수 있어 공정 단계와 시간이 절약되어 소자의 생산 수율을 향상시키는 이점이 있다.As described above, according to the present invention, the use of As ions, which are N-type dopants, in forming the profiled N-well region effectively solves the position and concentration reduction of the N-type dopant between the N-well region and the P-channel field stop implant region. In addition, since the ion implantation process can be omitted to compensate for the concentration decrease, the process step and time is saved, thereby improving the production yield of the device.

Claims (8)

반도체 기판 상부에 게이트산화막과, 게이트전극, 소오스/드레인영역을 구비하는 반도체 소자의 제조공정에 있어서;A manufacturing method of a semiconductor device having a gate oxide film, a gate electrode, and a source / drain region on a semiconductor substrate; 반도체 기판 상부에 소자분리를 위한 필드산화막을 형성하는 공정과,Forming a field oxide film on the semiconductor substrate for device isolation; 상기 반도체 기판에서 N웰영역으로 예정된 부위에 이온주입기를 이용하여 순차적으로 N웰 임플란트영역 및 P채널 필드스톱 임플란트영역을 구비하는 프로파일드 N웰영역을 형성하는 공정과,Forming a profiled N well region having an N well implant region and a P-channel field stop implant region sequentially using an ion implanter at a portion of the semiconductor substrate, the ion well implanter; 상기 반도체 기판에서 P웰영역으로 예정된 부위에 이온주입기를 이용하여 순차적으로 P웰 임플란트영역과, 중간 P웰 임플란트영역, N채널 필드 스톱 임플란트영역을 구비하는 프로파일드 P웰영역을 형성하는 공정과,Forming a profiled P well region having a P well implant region, an intermediate P well implant region, and an N-channel field stop implant region in sequence using an ion implanter at a predetermined portion of the semiconductor substrate as a P well region; 상기 구조의 전표면을 열처리하여 상기 프로파일드 N웰영역 및 프로파일드 P웰영역을 활성화시키는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Heat treating the entire surface of the structure to activate the profiled N well region and the profiled P well region. 제 1 항에 있어서, 상기 N웰영역과 P웰영역에 이온주입기를 통해 As 이온과 B 이온이 각각 주입되는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein As and B ions are respectively implanted into the N well region and the P well region through an ion implanter. 제 1 항에 있어서, 상기 프로파일드 N웰영역 및 프로파일드 P웰영역 형성시 사용하는 감광막의 밀도는 1 ∼ 10 g/cm2인 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the density of the photoresist used in forming the profiled N well region and the profiled P well region is 1 to 10 g / cm 2 . 제 1 항에 있어서, 상기 이온주입기를 통해 N웰 임플란트영역에 주입되는 이온주입량은 5×1012∼ 1×1414ions/cm2이고, 이온주입에너지는 1 ∼ 3 MeV 인 것을 특징으로 하는 반도체 소자의 제조방법.The semiconductor of claim 1, wherein an ion implantation amount is implanted into the N well implant region through the ion implanter is 5 × 10 12 to 1 × 14 14 ions / cm 2 , and an ion implantation energy is 1 to 3 MeV. Method of manufacturing the device. 제 1 항에 있어서, 상기 이온주입기를 통해 P채널 필드스톱 임플란트영역에 주입되는 이온은 As 이온과 P이온이 사용되며, 이온주입량은 1×1012∼ 5×1413ions/cm2이고, As이온 일때 이온주입에너지는 450 ∼ 650 KeV 이며, P이온 일때 이온주입에너지는 200 ∼ 300 KeV 인 것을 특징으로 하는 반도체 소자의 제조방법.According to claim 1, As ions and P ions are implanted into the P-channel field stop implant region through the ion implanter, the ion implantation amount is 1 × 10 12 ~ 5 × 14 13 ions / cm 2 , As The ion implantation energy is 450 ~ 650 KeV when the ion, the ion implantation energy is 200 ~ 300 KeV when P ion. 제 1 항에 있어서, 상기 열처리시 로(furnace)나 RTP 장비를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein furnace or RTP equipment is used during the heat treatment. 제 1 항 또는 제 6항에 있어서, 상기 로장비를 사용시 온도는 900 ∼ 1000℃ 이고, 시간은 30분 ∼ 1시간의 조건에서 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1 or 6, wherein the furnace equipment is used at a temperature of 900 to 1000 ° C and a time of 30 minutes to 1 hour. 제 1 항 또는 제 6항에 있어서, 상기 RTP장비를 사용시 온도는 900 ∼ 1100℃ 이고, 시간은 30초 ∼ 1분의 조건에서 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1 or 6, wherein the temperature at which the RTP equipment is used is 900 to 1100 ° C, and the time is performed under a condition of 30 seconds to 1 minute.
KR1019970073428A 1997-12-24 1997-12-24 Semiconductor device manufacture method KR100263454B1 (en)

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