KR950012035B1 - Cmos transistor manufacturing process - Google Patents

Cmos transistor manufacturing process Download PDF

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Publication number
KR950012035B1
KR950012035B1 KR1019930008878A KR930008878A KR950012035B1 KR 950012035 B1 KR950012035 B1 KR 950012035B1 KR 1019930008878 A KR1019930008878 A KR 1019930008878A KR 930008878 A KR930008878 A KR 930008878A KR 950012035 B1 KR950012035 B1 KR 950012035B1
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well
forming
oxide film
region
gate
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KR1019930008878A
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Korean (ko)
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정인술
정재관
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현대전자산업주식회사
김주용
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Priority to KR1019930008878A priority Critical patent/KR950012035B1/en
Priority to DE19944417819 priority patent/DE4417819B4/en
Priority to JP6130826A priority patent/JPH06338591A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

depositing an element-separating oxide film (4) on a p-Si substrate(1) with an N-well (2) and a P-well (3); forming a buffer oxide film(5) on the whole surface and implanting P-type impurity ions into a region (6) serving to define the threshold voltage; forming another region(8) to implant P-type impurity ions in the N-well only; removing the buffer oxide film(5); forming a gate oxide film(9) over both wells; forming a gate oxide film(9), a gate electrode(10) and a gate polyoxide film(11) respectively on the N-well and P-well: forming an ion diffusion region(12) for LCC by implanting imprity ions for LCC on the whole surface; forming a gate side wall spacer oxide film(13) on the side wall of the gate electrode(10); and forming ion diffusion regions(15,17) for source and drain in the N-well(2) and P-well(3), and annealing. The process is facilitated without additional masking steps, and threshold voltage is improved by simultaneous formation of source and drain pockets.

Description

상보 모스 트랜지스터 제조방법Complementary MOS transistor manufacturing method

제1도는 본 발명의 일 실시예에 따른 CMOS제조 공정 단면도.1 is a cross-sectional view of a CMOS manufacturing process according to an embodiment of the present invention.

＊도면의 주요부분에 대한 부호의 설명＊ Explanation of symbols for main parts of drawing

1 : 실리콘 기판 2 : N-웰1: silicon substrate 2: N-well

3 : P-웰 4 : 소자 분리 산화막3: P-well 4: device isolation oxide film

5 : 완충 산화막 6 : 차단 문턱전압 이온 주입영역5: buffer oxide film 6: blocking threshold voltage ion implantation region

7, 14, 16 : 감광막 8 : P-채널 문턱전압 이온 주입영역7, 14, 16: photosensitive film 8: P-channel threshold voltage ion implantation region

9 : 게이트 산화막 10 : 게이트 전구9: gate oxide film 10: gate bulb

11 : 게이트 폴리 산화막 12 : LDD용 이온확산영역11: gate poly oxide film 12: ion diffusion region for LDD

13 : 게이트 측벽 스페이서 산화막 15 : N+소스, 드레인 이온확산영역13 gate sidewall spacer oxide film 15 N + source, drain ion diffusion region

17 : P+소스, 드레인 이온확산영역17: P + source, drain ion diffusion region

본 발명은 상보 모스 트랜지스터(CMOS; complementary metal oxide semiconductor : 이하 CMOS라 칭함) 제조방법에 관한 것으로, 특히 마스크의 사용없이 차단막(blanket)으로 동시에 전 표면을 N-LDD(Llghtly Doped Drain : 이하 LDD라 칭함) 이온주입함으로써 간단한 공정으로 특성이 개선된 P-MOSFET(Metal Oxide Semiconductor Field Effect Trransistor)을 제조할 수 있는 CMOS 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a complementary metal oxide semiconductor (CMOS), and in particular, the entire surface of the N-LDD (LDD), at the same time as a blanket without the use of a mask. The present invention relates to a CMOS manufacturing method capable of manufacturing P-MOSFET (Metal Oxide Semiconductor Field Effect Trransistor) whose characteristics are improved by a simple process by ion implantation.

종래의 CMOS 제조시 N-MOSFET와 P-MOSFET의 특성을 최적화 하기 위해 여러 종류의 마스크를 사용하여 이온주입함으로써 소자의 특성을 개선하고 있으며, 특히 P-MOSFET의 단채널 효과(short channel effect), 열전자(hot current effect), 문턱전압(Vt; threshold voltage) 등의 특성 개선을 위하여 LDD P-MOSFET 및 포캣(Pocket) P-MOSFET 등의 구조로 다수의 마스크를 사용하여 P-MOSFET을 제조하고 있다. 따라서, 여러 단계의 마스킹 과정을 거침으로써 공정이 복잡하고 특성이 저하되는 등의 문제점이 따랐다.In order to optimize the characteristics of N-MOSFETs and P-MOSFETs in conventional CMOS fabrication, the characteristics of devices are improved by ion implantation using various types of masks. Especially, the short channel effects of P-MOSFETs, In order to improve characteristics such as hot current effect and threshold voltage (Vt), P-MOSFETs are manufactured using a plurality of masks with structures such as LDD P-MOSFETs and pocket P-MOSFETs. . Therefore, there are problems such as complexity and deterioration of the process by going through a multi-step masking process.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 간단한 공정을 통해 특성이 향상된 CMOS 제조방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is an object of the present invention to provide a method for manufacturing a CMOS improved characteristics through a simple process.

상기 목적을 달성하기 위하여 본 발명인 CMOS 제조방법은, 실리콘 기판 상에 N웰과 P웰을 형성한 다음, 소자 분리 산화막을 형성하고, 전 표면에 완충 산화막을 형성한 다음, 불순물 이온을 동작영역에 주입하여 차단 문턱전압 이온주입영역을 형성하는 제1단계, 상기 P-웰영역에 감광막을 형성한 다음, N-웰영역의 동작영역에만 이온이 주입되도록 P형 불순물을 주입하여 P-채널 문턱전압 이온주입영역을 형성하는 제2단계, 상기 감광막, 완충산화막을 제거하고, N웰 및 P웰상에 각각 게이트 산화막, 게이트 전극, 게이트 폴리 산화막을 차례로 형성한 다음, 전 표면에 N형 LDD용 불순물을 이온주입하여 LDD용 이온확산 영역을 형성하는 제3단계, 상기 게이트 전극 측벽에 게이트 측벽 스페이서 산화막을 형성한 다음, 각각의 N웰 및 P웰에 소스, 드레인 이온확산영역을 형성하고 어닐링하는 제4단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a CMOS manufacturing method of the present invention comprises forming an N well and a P well on a silicon substrate, forming a device isolation oxide film, forming a buffer oxide film on the entire surface, and then implanting impurity ions into the operating region. In the first step of forming a blocking threshold voltage ion implantation region by implantation, a photoresist film is formed in the P-well region, and then P-type impurities are implanted to inject ions only into an operating region of the N-well region, thereby forming a P-channel threshold voltage. In the second step of forming an ion implantation region, the photoresist film and the buffer oxide film are removed, and a gate oxide film, a gate electrode, and a gate poly oxide film are sequentially formed on the N well and the P well, and then an N-type LDD impurity is formed on the entire surface. In the third step of forming an ion diffusion region for LDD by ion implantation, a gate sidewall spacer oxide film is formed on the sidewall of the gate electrode, and then source and drain ion diffusion is formed on each of the N well and P well. And a fourth step of forming and annealing the inverse.

이하, 첨부된 도면 제1도를 참조하여 본 발명을 상술하면, 도면 제1도(a) 내지 제1도(f)는 본 발명의 일 실시예에 따른 CMOS 제조공정을 나타낸 단면도이다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings of FIG. 1. FIGS. 1A to 1F are cross-sectional views illustrating a CMOS manufacturing process according to an exemplary embodiment of the present invention.

우선, 제1도(a)는 P형 실리콘 기판(1)상에 N웰(2)과 P웰(3)을 형성한 다음, 소자 분리 산화막(4)을 형성하여 동작영역과 절연분리영역을 형성하고, 전 표면에 완충 산화막(5)을 형성한 다음, 동작영역과 절연문턱전압 조절용 P형 불순물 이온을 동작영역에 주입하여 차단 문턱전압 이온주입 영역(6)을 형성한 단면도이다.First, in FIG. 1A, an N well 2 and a P well 3 are formed on a P-type silicon substrate 1, and then an isolation layer 4 is formed to form an operation region and an insulation isolation region. After forming the buffer oxide film 5 on the entire surface, the cross-sectional view of the blocking threshold voltage ion implantation region 6 is formed by implanting the operating region and the P-type impurity ions for controlling the insulation threshold voltage into the operating region.

제1도(b)는 상기 P-웰(3)영역에 감광막(7)을 형성한 다음, N-웰(2)영역의 동작영역에만 이온이 주입되도록 P형 불순물을 주입하여 P-채널 문턱전압 이온주입영역(8)을 형성한 단면도이다.FIG. 1 (b) shows a P-channel threshold by forming a photoresist film 7 in the P-well 3 region and then implanting P-type impurities such that ions are implanted only in the operating region of the N-well 2 region. It is sectional drawing in which the voltage ion implantation area | region 8 was formed.

제1도(c)는 상기 감광막(7), 완충산화막(5)을 제거한 다음 게이트 산화막(9)을 형성한 후 게이트 전극(10)을 형성하고 일정 두께의 게이트 폴리 산화막(11)을 형성한 다음, 전 표면에 N-LDD용 불순물인 인이온(phosphorous)을 1012내지 1014/㎠의 도즈로 이온주입하여 LDD용 이온확산영역(12)을 형성한 단면도이다. 여기서, P-MOSFET(N-웰)에서는 N-웰(2)과 N-LDD이온 불순물이 동일한 N-형이므로 N-LDD 이온확산영역은 P-MOSFET의 포켓용으로 이용된다. 이렇게 함으로써 LDD N-MOSFET와 포켓 P-MOSFET를 마스크 공정 없이 N-MOSFET에는 LDD 이온주입과 포켓 P-MOSFET에는 포켓용으로 사용되도록 형성한 것이 본 발명의 요지이다.In FIG. 1C, the photoresist film 7 and the buffer oxide film 5 are removed, a gate oxide film 9 is formed, a gate electrode 10 is formed, and a gate poly oxide film 11 having a predetermined thickness is formed. Next, a sectional view of the ion diffusion region 12 for LDD is formed by ion implantation of phosphorus ion, which is an impurity for N-LDD, on the entire surface with a dose of 10 12 to 10 14 / cm 2. In the P-MOSFET (N-well), since the N-well 2 and the N-LDD ion impurity are the same N-type, the N-LDD ion diffusion region is used for the pocket of the P-MOSFET. In this way, the LDD N-MOSFET and the pocket P-MOSFET are formed so as to be used for LDD ion implantation in the N-MOSFET and pockets in the pocket P-MOSFET without a mask process.

제1도(d)는 상기 게이트 전극(10)측벽에 게이트 측벽 스페이서 산화막(13)을 0.05 내지 0.20㎛ 두께로 형성한 다음, N+소스, 드레인 불순물 이온마스크를 이용하여 감광막(14)을 형성한 후, N-MOSFET의 동작영역에 N+소스, 드레인 불순물을 1015/㎠의 도즈로 이온주입하여 N+소스, 드레인 이온확산영역(15)을 형성한 단면도이다.FIG. 1 (d) forms a gate sidewall spacer oxide layer 13 on the sidewall of the gate electrode 10 to a thickness of 0.05 to 0.20 μm, and then forms a photosensitive layer 14 using an N + source and drain impurity ion mask. After that, the N + source and drain ion diffusion regions 15 are formed by ion implanting N + source and drain impurities into a dose of 10 15 / cm 2 into the operating region of the N-MOSFET.

제1도(e)는 상기 감광막(14)을 제거하고, P+소스, 드래인 불순물 이온마스크를 이용하여 감광막(16)을 헝성한 후, P-MOSFET의 동작영역에 P+소스, 드레인 불순물 1015/㎠의 도즈로 이온주입하여 P+소스, 드레인 이온확산영역(17)을 형성한 단면도이다.FIG. 1E shows that the photoresist layer 14 is removed, the photoresist layer 16 is formed using a P + source and a drain impurity ion mask, and then P + source and drain impurities are formed in the operating region of the P-MOSFET. A sectional view of the P + source and drain ion diffusion regions 17 formed by ion implantation at a dose of 10 15 / cm 2.

제1도(f)는 상기 감광막(17)을 제거하고 어닐링하여 이온 불순물이 확산되어 최종 형태의 프로파일을 형성한 단면도이다. 이때 P-MOSFET 영역의 P-채널 가장자리 동작영역에서 N-LDD 이온확산영역(12)이 N-웰(2), P-채널 및 P+소스, 드레인 이온확산영역(17) 경계면에 위치하게 되고, 또한 P+소스, 드레인 불순물과는 반대형으로 존재하여 포켓 P-MOSFET을 형성하게 된다.FIG. 1F is a cross-sectional view of removing and annealing the photosensitive film 17 to diffuse ionic impurities to form a final profile. At this time, the N-LDD ion diffusion region 12 is located at the boundary of the N-well 2, P-channel and P + source and drain ion diffusion regions 17 in the P-channel edge operation region of the P-MOSFET region. It also exists in the opposite form of the P + source and drain impurities, forming a pocket P-MOSFET.

상기와 같이 이루어지는 본 발명은 CMOS 제조시 N-MOSFET와 P-MOSFET를 구분하여 사용하고 있는 LDD 이온주입용 마스크 공정을 거치지 않고 블랭킷으로 N-MOSFET와 P-MOSFET에 동시에 N-LDD 이온을 주입함으로써 N-MOSFET에 LDD-N-MOSFET가 되고 P-MOSFET에는 포켓용으로 사용됨으로써 포켓-P-MOSFET을 제조하여 공정이 간단한 효과가 있다.In the present invention as described above, by injecting N-LDD ions into the N-MOSFET and the P-MOSFET simultaneously with a blanket without going through the LDD ion implantation mask process that separates the N-MOSFET and the P-MOSFET during CMOS fabrication. LD-N-MOSFETs for N-MOSFETs and pockets for P-MOSFETs can be used to fabricate pocket-P-MOSFETs, thus simplifying the process.

또한 P-MOSFET 영역의 P-채널 가장자리 동작영역에서 N-LDD 이온확산영역이 N-웰, P-채널 및 P+소스, 드레인 이온확산영역 경계면에 위치하게 되고, 또한 P+소스, 드레인 불순물과는 반대형으로 존재하여 포켓 P-MOSFET을 형성하게 됨으로써 P-MOSFET의 DIBL(Drain lnduced Varial Lowering)효과 및 문턱전압 특성을 개선하는 효과를 얻을 수 있다.Also, in the P-channel edge operation region of the P-MOSFET region, the N-LDD ion diffusion region is located at the interface of the N-well, P-channel and P + source and drain ion diffusion region, and also the P + source and drain impurities By forming the pocket P-MOSFET in the opposite form, the effect of improving the drain-induced varial lowering (DIBL) and threshold voltage characteristics of the P-MOSFET can be obtained.

Claims (5)

CMOS 제조방법에 있어서, 실리콘 기판(1)상에 N웰(2)과 P웰(3)을 형성한 다음, 소자 분리 산화막(4)을 형성하고, 전 표면에 완충 산화막(5)을 형성한 다음, P형 불순물 이온을 동작영역에 주입하여 차단 문턱전압 이온주입영역(6)을 형성하는 제1단계, 상기 P-웰(3)영역에 감광막(7)을 형성한 다음, N-웰(2)영역의 동작영역에만 이온이 주입되도록 P형 불순물을 주입하여 P-채널 문턱전압 이온주입영역(8)을 형성하는 제2단계, 상기 감광막(7), 완충산화막(5)을 제거하고, N웰(2) 및 P웰(3)상에 각각 게이트 산화막(9), 게이트 전극(10), 게이트 폴리 산화막(11)을 차례로 형성한 다음, 전 표면에 N형 LDD용 불순물을 이온주입하여 LDD용 이온확산영역(12)을 형성하는 제3단계, 상기 게이트 전극(10)측벽에 게이트 측벽 스페이서 산화막(13)을 형성한 다음, 각각의 N웰(2) 및 P웰(3)에 소스, 드레인 이온확산영역(15,17)을 형성하고 어닐링 하는 제4단계를 포함하여 이루어지는 것을 특징으로 하는 CMOS 제조방법.In the CMOS manufacturing method, the N well 2 and the P well 3 are formed on the silicon substrate 1, the device isolation oxide film 4 is formed, and the buffer oxide film 5 is formed on the entire surface. Next, a first step of forming the blocking threshold voltage ion implantation region 6 by implanting P-type impurity ions into the operation region, forming a photosensitive film 7 in the P-well (3) region, and then N-well ( 2) a second step of forming a P-channel threshold voltage ion implantation region 8 by implanting P-type impurities such that ions are implanted only in the operation region of the region, and removing the photosensitive film 7 and the buffer oxide film 5, A gate oxide film 9, a gate electrode 10, and a gate poly oxide film 11 are sequentially formed on the N wells 2 and P wells 3, and then ion implantation of N-type LDD impurities is carried out on the entire surface. In the third step of forming the ion diffusion region 12 for the LDD, a gate sidewall spacer oxide film 13 is formed on the side wall of the gate electrode 10, and then the small portions of the N wells 2 and the P wells 3 are formed. , CMOS manufacturing method comprising the fourth step of forming and annealing the drain ion diffusion regions (15,17). 제1항에 있어서, 상기 제4단계의 소스, 드레인 이온확산영역(15,17) 형성은 N웰(2)상에 감광막(14)을 형성한 후, N 채널 MOSFET의 동작영역에 N+소스, 드레인 불순물을 이온주입하여 N+소스, 드레인 이온확산영역(15)을 형성하는 단계와, N웰(2)상에 감광막(14)을 제거하고 P웰(3)상에 감광막(16)을 형성한 후, P채널 MOSFET의 동작영역에 P+소스, 드레인 불순물을 이온주입하여 P+소스, 드레인 이온확산영역(17)을 형성하는 단계를 더 포함하여 이루어지는 것을 특징으로 하는 CMOS 제조방법.2. The method of claim 1, wherein the source and drain ion diffusion regions 15 and 17 of the fourth step are formed by forming the photoresist film 14 on the N well 2, and then forming an N + source in the operating region of the N channel MOSFET. Ion implantation of the drain impurity to form an N + source and drain ion diffusion region 15, removing the photoresist film 14 on the N well 2, and removing the photoresist film 16 on the P well 3. And forming a P + source and a drain ion diffusion region (17) by implanting P + source and drain impurities into the operation region of the P-channel MOSFET after formation. 제1항에 있어서, 상기 제3단계의 N형 LDD용 주입불순물이 인이온(phosphorous)인 것을 특징으로 하는 CMOS 제조방법.The method of claim 1, wherein the implanted impurity for N-type LDD in the third step is phosphorous. 제3항에 있어서, 불순물 주입시 1012내지 1014/㎠ 의 양으로 이온주입함을 특징으로 하는 CMOS 제조방법.The method of claim 3, wherein the implant is ion implanted in an amount of 10 12 to 10 14 / cm 2. 제1항에 있어서, 상기 제4단계의 게이트 측벽 스페이서 산화막(13)의 두께가 0.05 내지 0.20㎛임을 특징으로 하는 CMOS 제조방법.2. The method of claim 1 wherein the thickness of the gate sidewall spacer oxide film (13) in said fourth step is between 0.05 and 0.20 [mu] m.
KR1019930008878A 1993-05-22 1993-05-22 Cmos transistor manufacturing process KR950012035B1 (en)

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