JPS61158958U - - Google Patents
Info
- Publication number
- JPS61158958U JPS61158958U JP4356085U JP4356085U JPS61158958U JP S61158958 U JPS61158958 U JP S61158958U JP 4356085 U JP4356085 U JP 4356085U JP 4356085 U JP4356085 U JP 4356085U JP S61158958 U JPS61158958 U JP S61158958U
- Authority
- JP
- Japan
- Prior art keywords
- package
- lead
- sides
- glass
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000011295 pitch Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はパツケージ基板上に本考案によるリー
ドフレームをアタツチした状態を示す平面図、第
２図は同正面図、第３図は同右側面図、第４図イ
，ロは本考案と従来例とにおけるワイヤボンデイ
ング要領の概略比較図でありイは本考案の場合、
ロは従来例の場合を夫々示し、第５図は従来のリ
ードフレームをパツケージ基板上にアタツチした
状態を示す平面図である。
（符号の説明）、１…半導体チツプ、１１…ボ
ンデイングパツド、２…パツケージ基板、２１…
ダイアタツチエリア、３…リードフレーム、３１
，３２…リード端子、４…ワイヤ、５…パツケー
ジキヤツプ。
Fig. 1 is a plan view showing the lead frame according to the present invention attached to a package board, Fig. 2 is a front view of the same, Fig. 3 is a right side view of the same, and Fig. 4 A and B show the present invention and the conventional lead frame. A is a schematic comparison diagram of the wire bonding procedure in the case of the present invention,
FIG. 5 is a plan view showing a state in which a conventional lead frame is attached to a package substrate. (Explanation of symbols), 1... semiconductor chip, 11... bonding pad, 2... package substrate, 21...
Die attach area, 3...Lead frame, 31
, 32...Lead terminal, 4...Wire, 5...Package cap.
Claims (1)
ングパツドが偏在した方形の半導体チツプを取着
塔載するダイアタツチエリアを有し、該パツケー
ジ基板の両側辺より複数のリード端子を等ビツチ
で導入すると共にワイヤを介して上記ボンデイン
グパツドに結線し且つパツケージキヤツプをガラ
ス接着にて覆蓋して成るガラス封止型半導体パツ
ケージに用いられるリードフレームにおいて、前
記リード端子のうちパツケージ基板の両側辺中央
部に位置するリード端子をＴ字形の左右対称共役
導出型リード端子となすと共に、他のリード端子
の先端を、前記ダイアタツチエリアの左右側辺部
側に延出配向したことを特徴とするガラス封止型
半導体パツケージ用リードフレーム。 Approximately in the center of the package board, there is a die attach area for mounting a rectangular semiconductor chip with bonding pads unevenly distributed on the left and right sides, and a plurality of lead terminals are introduced from both sides of the package board at equal pitches. In a lead frame used for a glass-sealed semiconductor package, which is connected to the bonding pad via a wire and a package cap is covered with glass adhesive, one of the lead terminals is connected to the center of both sides of the package substrate. A glass seal characterized in that the located lead terminal is a T-shaped bilaterally symmetrical conjugate lead terminal, and the tips of the other lead terminals are oriented to extend toward the left and right sides of the die attach area. Lead frame for type semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4356085U JPS61158958U (en) | 1985-03-26 | 1985-03-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4356085U JPS61158958U (en) | 1985-03-26 | 1985-03-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61158958U true JPS61158958U (en) | 1986-10-02 |
Family
ID=30555343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4356085U Pending JPS61158958U (en) | 1985-03-26 | 1985-03-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61158958U (en) |
-
1985
- 1985-03-26 JP JP4356085U patent/JPS61158958U/ja active Pending
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