JPS6115754U - integrated circuit container - Google Patents
integrated circuit containerInfo
- Publication number
- JPS6115754U JPS6115754U JP9855784U JP9855784U JPS6115754U JP S6115754 U JPS6115754 U JP S6115754U JP 9855784 U JP9855784 U JP 9855784U JP 9855784 U JP9855784 U JP 9855784U JP S6115754 U JPS6115754 U JP S6115754U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit container
- thin film
- film
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案集積回路容器の一実施例を示す平面図、
第２図は同じくそのＡ −Ａ’断面図であ１．．．１（
１）−ｋ５ｉ”７９ｇよ、２．．．エ２（１）−ｋ５ｉ
ツク基板、３・・・第１の金属薄膜、一・・・絶縁膜、
５一・・第２の金属薄膜、、６・・・キャビテイ部、７
・・・窓８・・・配線パターン、９・・・端子、１１・
・・電源線、１２・・・接地線。FIG. 1 is a plan view showing an embodiment of the integrated circuit container of the present invention;
FIG. 2 is a cross-sectional view taken along line A-A' of 1. ．． ．． 1(
1)-k5i"79g, 2...d2(1)-k5i
3... first metal thin film, 1... insulating film,
51... Second metal thin film, 6... Cavity part, 7
...Window 8...Wiring pattern, 9...Terminal, 11.
...Power wire, 12...Ground wire.
Claims (1)
成する一定面積のパターンを薄膜ないし厚膜によって形
成し、その上に誘電体薄膜を介してさらに他の電極を構
成するパターンを薄膜ないし厚膜で形成して一定容量の
コンデンサを構成せしめ、その上に形成したキャビテイ
部を有する第２のセラミック基板上の配線パターンのう
ち電源線と接地線を前記コンデンサの一極にそれぞれ接
続せしめたことを特徴とする集積回路容器。A pattern of a certain area constituting one electrode is formed on the first ceramic substrate of the integrated circuit container using a thin film or a thick film, and a pattern constituting the other electrode is formed on the thin film or thick film with a dielectric thin film interposed therebetween. A capacitor of a certain capacity is formed by forming a film, and a power line and a ground line of the wiring pattern on a second ceramic substrate having a cavity formed thereon are respectively connected to one pole of the capacitor. An integrated circuit container featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9855784U JPS6115754U (en) | 1984-07-02 | 1984-07-02 | integrated circuit container |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9855784U JPS6115754U (en) | 1984-07-02 | 1984-07-02 | integrated circuit container |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6115754U true JPS6115754U (en) | 1986-01-29 |
Family
ID=30658095
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9855784U Pending JPS6115754U (en) | 1984-07-02 | 1984-07-02 | integrated circuit container |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6115754U (en) |
-
1984
- 1984-07-02 JP JP9855784U patent/JPS6115754U/en active Pending
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