JPS61156318U

JPS61156318U -

Info

Publication number: JPS61156318U
Application number: JP4006985U
Authority: JP
Priority date: 1985-03-20
Filing date: 1985-03-20
Publication date: 1986-09-27
Also published as: JPH0445301Y2

Description

[Brief explanation of the drawing]

第１図は本考案によるタイマー装置の一実施例
を示す電気回路図、第２図は第１図の任意点およ
びＩ，Ｏで示した入・出力端子の信号波形図を示
している。第３図は従来実用化されているカムタ
ムＩＣと対応し同一動作を行なう周知構成による
電気回路図、第４図は第３図中における任意点お
よびＯで示した出力端子の信号波形図を示してい
る。５……出力回路、６……トランジスタ、７……
ツエナーダイオード、８……第１のタイマー回路
、９……第２のタイマー回路、１０……阻止回路
、１１……遅延回路、ＣＩ……コンデンサ、Ｔｒ
……トランジスタ。 FIG. 1 is an electric circuit diagram showing an embodiment of a timer device according to the present invention, and FIG. 2 is a signal waveform diagram of arbitrary points in FIG. 1 and input/output terminals indicated by I and O. Fig. 3 is an electrical circuit diagram of a well-known configuration that corresponds to a conventional Cam-Tom IC and performs the same operation, and Fig. 4 shows a signal waveform diagram of an arbitrary point in Fig. 3 and the output terminal indicated by O. ing. 5...Output circuit, 6...Transistor, 7...
Zener diode, 8...first timer circuit, 9...second timer circuit, 10...blocking circuit, 11...delay circuit, CI...capacitor, Tr
...Transistor.

Claims

[Claims for Utility Model Registration] (1) An input terminal to which a group of pulse signals of an arbitrary number of bits is serially supplied, and an input terminal that operates by detecting the rising or falling edge of the input pulse signal. By detecting the rise or fall of the pulse signal group when the pulse signal group is supplied through the pulse signal group, the timing end point is set at an arbitrary point until the next pulse signal of the pulse signal group is supplied. a first timer circuit that outputs a first timing pulse signal having a first time width; a second timing pulse signal having a second time width equal to the time immediately before outputting the desired arbitrary bit pulse signal by detecting the rising or falling edge of the pulse signal group when the pulse signal group is supplied; a second timer circuit that outputs a second timer circuit; and a switch element whose operation is controlled by being supplied with the first timer pulse signal, and the operation of the switch element produces a predetermined output corresponding to the first timer pulse signal. an output circuit for setting a state; a blocking circuit that is activated to at least block the supply of the pulse signal group to the first timer circuit; and a blocking circuit that is activated by being supplied with the second timer pulse signal. ,
A predetermined delay time is set within the time until the next pulse signal of the pulse signal group is supplied, and after the delay time, the blocking circuit is operated with a time width responsive to the second timing pulse signal. and a delay circuit that outputs a delayed pulse signal to control the output circuit, and controls the operation of the first and second timer circuits using only the pulse signal for each arbitrary bit of the pulse signal group, thereby controlling the operating state of the output circuit. A timer device. (2) The blocking circuit is a switch element that is connected between an input terminal and ground and operates to forcibly lower the potential of the input terminal to a low level. Claim 1 of the Utility Model Registration Claim The timer device described in . (3) The timer device according to claim 1, wherein the delay circuit is an integrating circuit consisting of a resistor and a capacitor.