JPS61152115A - Digital filter - Google Patents

Abstract

PURPOSE:To multiply the conversion rate of sampling frequency by N and 1/N with a reduced circuit size by providing a memory and a memory counter relating to coefficient data and multiplied data, respectively. CONSTITUTION:In cased an inputted function selecting signal multiplies the sampling frequency by N, a counter control circuit 57 controls an output value so as to be shifted by one whenever said circuit 57 counts the action of a ROM address counter 56 at every m-times in a m/N-adic terms, and writes the multiplied data in the memory 52 while m/N-number of multiplied data are read out N-times. On the other hand, where the function selecting signal multiplies the sample frequency by 1/N, the counter control circuit 57 sets the action of the counter 56 in (m-1)-adic terms, divides the multiplied data into N-series with respect to the memory 52 so as to read the data at every series, and writes new multiplied data once whenever each series is read out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital filter applied to digital signal processing.

[Technical background of the invention and its problems]

Recently, in the field of audio equipment, PCM recorders and DAD (digital audio disc) players, etc., which utilize PCM (Palace Code Modification) technology, have been introduced in an effort to achieve as high fidelity playback as possible. Digital recording and reproducing devices are becoming popular. Therefore, the basic configuration of this digital recording/reproducing apparatus will be explained with reference to FIG. 5. First, an analog signal such as an audio signal is supplied to the input terminal I.

After unnecessary high frequency components are removed by the low-pass filter αa, the signal is supplied to the sample/hold circuit 0 and set at a predetermined sampling frequency (for example, 4 in the case of a DAD player).
sampled at periodic intervals of 4.1 KHz).

This sampled analog signal.

After being quantized and encoded into a digital signal by the human/D (analof to difltal) converter a4, and subjected to error correction code addition and digital modulation processing by the digital processing circuit α9, it is transferred to a tape, disk, etc. The reproduction signal is recorded on the recording medium (IQ) and taken out from the recording medium section during reproduction.

A digital demodulation processing circuit (17) performs demodulation and correction of errors caused by defects in the recording medium αe, and returns the signal to the original digital signal. This digital signal is D/A (dlI
After being converted into a step-like analog signal by a converter (to analog), it is passed through a low-pass filter (1
1, harmonic components that become noise are removed, and a continuous analog signal, that is, the original audio signal, is output from the output terminal (to).

By the way, in the digital recording/reproducing device as described above, when an analog signal is sampled and restored again, a harmonic component that is folded back around the sampling frequency is generated in the frequency component included in the original signal, and as a result, the original signal is Since harmonics are distributed near the upper limit of the signal band, it is necessary to remove them, so the 6-/<s filter α is provided with a very steep filter characteristic. However, if a digital filter Cυ shown by a dotted line in FIG. 5 is interposed after the A/D conversion converter α or before the D/A conversion converter, the harmonic components can be removed at the digital signal stage.

Low pass filter 0. The filter characteristics of a9 can be reduced.

Here, the above-mentioned digital filter Q1) will be explained. Normally, when giving filter characteristics to a digital signal 1
There are methods that operate in the frequency domain and methods that operate in the time domain. Therefore, the method of operating in one frequency domain is to convert the input sequence (j(→)) in the time domain of the digital signal to FF
T (fast Fourier transformer) to a value X in the frequency domain) to obtain a transfer function G having desired characteristics in the same wavenumber domain
(b), and then the product Y(→ is processed by IFFT (inverse fast Fourier transformer)
(→). However, this method requires an input sequence (real-time processing is difficult when j(→) continues for a long time) and dedicated hardware for FFT and IFFT, resulting in a large circuit scale and high cost. However, Kana is relatively expensive.

On the other hand, the above method of operating in the time domain is the input series (
1 (→) and the impulse response sequence (& (ru)) that has the desired filter characteristics (b ==Q, 1.2. ・+ m
) by finite convolution with the output series (yTh) )
This is what you get. That is, this operation is to cumulatively add the convolution calculation formula 4(A), and the circuit configuration for this purpose is generally shown in FIG. In other words.

Each input signal of the input series (j(-)) is routed through multiple delay elements (
These multiple input signals are each multiplied by the corresponding coefficient data by the stationary multiplier (to), and these values are then input to the adder (to). It is added in total. but.

Even if this method is adopted, if the order of the convolution operation is high, the number of required delay elements (for example, shift registers) and multipliers will become enormous, and the size of one circuit will inevitably increase. For example, in a digital filter that handles an input signal containing many harmonic components, such as the one mentioned above,
In setting the filter characteristics, a considerably large number of coefficient data must be obtained, resulting in high-order calculations.

For this reason, as an improvement to the circuit shown in FIG. 6, it has been proposed to store input signals and coefficient data in respective storage elements, read them out sequentially, and perform multiplication and addition. That is, as shown in FIG. 7, it is the coefficient data J(A)
is stored in the coefficient ROM (read-only memory) Gυ, and the input signal 2 is stored in the memory (memory that can be written at any time! J) (33).

Read them sequentially using an address counter (to) and (2) a cumulative adder having a multiplier and an adder (to)
Therefore, the purpose is to obtain a calculation output of 1 (→= 2 (=) 2 (=)), and it is an attempt to construct a practical circuit.The first problem is that the above address This is the setting of the counter (to), (to) and the timing control circuit (to) that controls it, and by devising these settings, the above calculation can be executed continuously for a long time, and it can be realized with a simple circuit configuration. is considered to be Sa.

Furthermore, in the digital filter Qυ for digital audio described above, the low-pass film α3. In order to reduce (the filter characteristics of Ll) and achieve high-fidelity reproduction, it has been considered to increase the sampling frequency of the output signal by N times or i times the input signal. For example, in the digital filter Cυ installed before the D/A converter α, the sampling frequency is converted by N times in order to separate the harmonic components from the frequency components of the original signal and remove aliasing distortion. It is preferable that the digital filter (21) be installed after the A/D converter α4, and conversely, it is desirable to convert the signal to a factor of 1. Therefore, when performing such an operation, it is expected that the filter configuration will become more complicated and the circuit scale will become larger, and to avoid this, an unprecedentedly sophisticated control system will be required.

[Purpose of the invention]

The present invention was made in consideration of the above-mentioned technical background, and contributes to the reduction of the scale of one circuit, and is capable of processing both the processing of increasing the conversion rate of the sampling frequency by N times and the processing of increasing it by 1. The purpose is to provide a digital filter that

[Summary of the invention]

The digital filter of the present invention has 1m coefficient data &
(Nsu*'(Nmu+1),...&(NA+N-1)(
However, N is an integer, A=0.1.・・・F 1 ) N
A first memory divided into series and stored therein, an m-ary 10th counter for specifying an address for reading out the coefficient data for each series with respect to the first memory, and input multiplicand data are stored therein. a second memory; a second counter addressing the second memory;
counter control means for controlling the operation of the counter; memory mode specifying means for specifying the operation mode of the second memory; and coefficient data output from the first memory and the second memory.
and an accumulative adder that performs multiplication and addition with the multiplicand data output from the second memory or the multiplicand data directly input when the second memory is in the write mode, and the input function selection signal is sampled. If the signal instructs to convert the frequency by N times, the counter control means controls the operation of the second counter in W-adism so that the output value shifts by one every time m counts are made; The memory mode designation means designates the second memory to write multiplicand data that is folded once within N times of reading M multiplicand data, while the function selection signal designates to convert the sampling frequency to i times. If the signal is an instruction signal, the counter control means controls the operation of the second counter so that it becomes substantially Km-1, and
The memory mode specifying means sends the multiplicand data to the second memory (CN/), g(N/+l).

...2(rQ+N-1) (J is any integer) (J is an arbitrary integer) divided into N series, read out each series, and specifies that multiplicand data that is refracted once in each cycle is read out. shall be.

[Embodiments of the invention]

As an embodiment of the present invention, the sampling frequency is converted to 2.
Taking as an example the case where the size is multiplied by T, the explanation will be given below with reference to the drawings. In this embodiment, the filter coefficient length (number of coefficient data) is set to 32.

First, FIG. 1 schematically shows the filter circuit of this embodiment. In the figure, the RAM 5a and υ multiplicand data are output to the cumulative adder 61), which has one multiplier and an adder, and υ coefficient data J(L) is output from the ROM 53 in synchronization with this. Output. In addition.

Here, both the multiplicand data and the coefficient data are assumed to be 16-bit data, but in reality, any number of bits may be used. The input data, which becomes the multiplicand data, is converted into a parallel signal by the 5IPO (serial-to-parallel converter) C54, and is taken into the RAM 61 at the timing described later, and when the RAM eia is in the write mode, the cumulative adder 6DK is also directly input. is input.

Here, it is assumed that the input data WDCK (word clock) and BCK (bit clock) are synchronized with the system clock in the circuit. Also.

The coefficient data is set in advance as a desired filter characteristic, and is stored in the ROM 63 in a predetermined arrangement.

Therefore, RAM eia and ROM al are controlled by 5-pit address signals output from the R and AM address counters (to) and the ROM address counter, respectively. And the mode of action of RAM@3 (
R, /W) are designated by the M control circuit 6η, and this RAM control circuit 6η generates the R/'W signal based on the output of the ROM address counter, and furthermore, the R, AM address counter (to) 4, which also generates and outputs a decimal number switching signal and control number 1, which will be described later. The generation is performed in accordance with a function selection signal that instructs the selection of the operation to be performed by this circuit, that is, whether to double or seven times the conversion rate of the sampling same wave number.

Next, the operation of this embodiment will be explained using FIGS. 2 to 4. Note that Figure 2 shows the operation of doubling the sampling frequency (D/A time since the audio digital filter mentioned above uses D/111K), and Figure 3 shows the operation of doubling the sampling frequency. This figure shows the operation of the doubling process (during A/D).
Figure 3 (a) is at D/A time, S3 (Figure 3) is ~1 o'clock) and O
Array of coefficient data 4 (L) in M (to) (Figure 3 (C)
). As can be seen from these figures, in the image processing during D/A and A/D, the address signal of the ROM address counter that controls the coefficient data related to the processing and its output is It does not change, and this point is also a feature of the present invention.

First, the D/A processing shown in FIG. 2 will be explained. In the same figure, RAM address AD, ~ person D4
is the address signal output from the RAM address counter 15, and RAM data 21 (b) is the address signal output from the RAM address counter 15.
The multiplicand data output from 53 or the input data to be written are indicated by only the number i. Also, ROM
-Addresses AD0 to AD are address signals that are output many times (ROM address counter).
Data μ indicates coefficient data output from RIOMai, and only the number amount is recorded. Then, C0NV, output yh) is an output written as a result of cumulative addition of multiplicand data j1 (?I) and coefficient data JL (L), which are synchronously input in the cumulative adder 6I), and is taken out at a constant cycle. It will be done.

The processing performed by this ζ satisfies the first-order convolution calculation formula (%), and each time one piece of input data is taken in, the two operations of equation (1) above are executed, and the input data is Output data is obtained at twice the frequency. Here, the multiplicand data used for one convolution is animal milk -
A) There are 16 pieces of (A=Q, 1..., 15),
On the other hand, the coefficient data having β pieces is shown in Fig. 3 (c
) as shown in the upper and lower rows of the figure.

It is divided into two series, 4 (2A+1), and corresponds to each series. That is, the multiplicand data (%-0 is returned twice and output from RAM C53. Therefore, when the 1 function selection signal instructs processing at the time of D/A, the M control 4- is sent to B. The hexadecimal counter operation is performed by the hexadecimal counter circuit 6η, which uses a hexadecimal switching signal for the M address counter (to) so that the address output AD4 is always K ``L'''. While the data g (%-) is output repeatedly twice.

几/W signal goes from @H″ (reading mode specification) to 1
L" (write mode designation), and the oldest of the multiplicand data stored up to that point is rewritten to the input data. In other words, the period when R/W No. 1 becomes @L" is n-adic. This coincides with the period in which the ROM address counter makes one cycle, and for this reason, in this embodiment, the RAM
Control circuit 6? ), ROM address AD
, ~AD, are all 'H' and AD is 'IIL', the control signal is set to 'L'.Here, the rewriting of the multiplicand data in the RAM 53 is as follows. , the data arranged on the left side of Fig. 4(a) is rewritten in order of the data on the right side. In the figure, the larger the number, the newer the data. In updating this multiplicand data, Well, RAM
Since it is necessary to shift the addresses sequentially, the control signals (in this case, ROM addresses AD, ~AD) are all "H".
(becomes @H''' when ``fi''), an operation is performed to increase the output of the RAM address by +2. That is,
When the control signal is @H”, the RAM address counter (to) is AD.

is held and AD is inverted.

Therefore, in order to clarify the above, some of the operations performed according to the timing shown in FIG. 2 will be listed.

P (30) = j (30 houses (0) + 1 (28) -
(1) + 4 (26) J (2) 4-・・・-・+ Direct (2)' (14) + 4 (0 houses (15) y (31) =
LC31) j(0) + Q29)'(1) + 4
(27)1(2)+・・・+4(3)j(14)+
4 (1) Liao (15) Y (32) Ko L (30 houses (1) + 4
(2B)s(2)+4(26)j(3)+・・・・・・+
A(2) '(15) + 4(0) x (16)
- It can be confirmed that these calculations conform to the above-mentioned formula (1).

Next, the A/D processing shown in FIG. 3 will be explained.

The meaning of each signal in FIG. 1 is the same as that in FIG. 2. Therefore, in this case, R
The AM control circuit 57) uses the decimal number switching signal to
It causes the AM address counter (g) to perform a 31-base counter operation, and the control signal is always "L". By setting the RAM address counter (to) to 31 decimal in contrast to the 32 decimal ROM address counter (to) K, the multiplicand data naturally shifts with respect to the coefficient data / when moving to the primary operation. This is what I asked him to do. Also, the R/W signal is the ROM address counter (to)
The ROM address AD, -L AD,
becomes @L” when all are @H″.

Here, the processing at the time of A/D satisfies the first-order convolution calculation formula, and the calculation output of the above formula (2) is obtained every time two pieces of input data are taken in.

However, the calculation performed at the timing shown in FIG. 3 is as follows, but this is essentially no different from the calculation in equation (2) except that the numbering of the multiplicand data is shifted by one. Therefore, the coefficient data used in this calculation is divided into a j(2) series and a z(2a+1) series and output for each series, similar to the processing at the time of D/A, and the multiplicand data is also output as a 4th series. As shown in figure Φ), the series of j(2/) and “C2/+1
> is divided into series. Then, the coefficient data and the multiplicand data are multiplied correspondingly for each series (in the case of FIG. 3, J(24) vs. j(27+1)).

Q2A+1) versus j(2/)). Note that since the multiplicand data is shifted relative to the coefficient data each time new input data is input, the correspondence between the coefficient data and the multiplicand data for each series is maintained.

Therefore, some of the calculations performed in this way are shown in Figure 3.

y(30) TomiA(ao)z(-t) +z(28 houses(
1)+・・・・・・+4(2)j(27)−+−J(
0)x(29)+J(31)g(0)+4(29)s(
2)+ −−・−・−・+ z(3)jl(2s) +
'(1)χ(30)YC32) -a(ao doorQ)+
4(28)jl(3)+・・・・・・・+J(2) Kei(
29) + J(0)”(31)+J(at)*(2)
+4 (29 houses (4) +...+ '<3>' (
30) + &(1)''(32), which complies with Equation (2).

As described above, in the above embodiment, one type of coefficient data stored in the ROM and one 80M address counter are used, and the sampling frequency is doubled and seven times the sampling frequency without changing the output order. It is possible to perform both types of processing, and the circuit configuration is simplified. Nevertheless, both of the above processes are executed appropriately. Note that other methods may be considered for the details of the above embodiment.

For example, when shifting the multiplicand data at the time of D/A, in the Ueyu embodiment, a control number that is +2 of the address was used.
The address signal may be held for one data. In addition, if a +2 control signal is used at A and 4 o'clock, the m-ary counter will essentially perform an m-1-ary counter operation.

Furthermore, the present invention is not limited to the above-mentioned embodiments, and it is possible to convert the sampling frequency by N times or M times. In this case, −m coefficient data are &(NA).

&(NA+l), . . . , A(NA+N-1), which are stored in the ROMK, and read out for each series. And when increasing the sampling frequency by N times.

In order to satisfy the above equation, the operation of the address counter that controls the multiplicand data may be made to be a ma-ary, and the multiplicand data may be shifted every time the series of operations described above is executed.

Also, when increasing the sampling frequency by 7 times, K is.

In order to satisfy
(NJ) 1M (NJ+1),..., s(N/+N-
1), it may be divided into N series, and each series may be associated with coefficient data.

〔Effect of the invention〕

As explained above, the present invention contributes to reducing the scale of one circuit and increases the sampling frequency conversion rate by N times.
It is possible to provide a practical digital filter that enables both doubling and doubling processing.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a digital filter according to the present invention, and FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment. FIG. 4 is an explanatory diagram for explaining the method of storing data in the memory in the same embodiment, FIG. 5 is a block diagram showing the basic configuration of the digital recording and reproducing apparatus, and FIGS.
The figure is a circuit configuration diagram showing a conventionally proposed digital filter. 51... Accumulative adder, 52... RAM, 53...
R, OM, 55...RAM゛ address counter,
56...ROM address counter. 57...RAM control circuit. Figure 1 s 4 Figure (a) (b) (C) Figure 5

Claims (1)

[Claims] m coefficient data are k(Nk), k(Nk+1),...
・k(Nk+N-1) (where N is a predetermined natural number, k=
A first memory which is divided into N series (0, 1, ..., m/N-1) and stored therein, and an address specification for reading out the coefficient data for each series from this first memory. a first m-adic counter; a second memory for storing input multiplicand data; a second counter for addressing the second memory; and controlling the operation of the second counter. a counter control means, a memory mode designation means for designating an operation mode of the second memory, and a first
and an accumulator that multiplies and adds the coefficient data output from the second memory and the multiplicand data output from the second memory or the multiplicand data input directly when the second memory is in write mode. However, when the input function selection signal is a signal instructing to convert the sampling frequency by N times, the counter control means controls the operation of the second counter in m/N base and every m times it counts. control so that the output value is shifted by one, and the memory mode specifying means shifts the output value by one while reading m/N multiplicand data from the second memory N times.
If the function selection signal is a signal instructing to convert the sampling frequency to l/N times, the counter control means controls the operation of the second counter. substantially m-
At the same time, the memory mode specifying means transfers the multiplicand data to the second memory x(N
j), x(Nj+1), x(Nj+N-1) (however, j
is an arbitrary integer), the digital filter specifies to read out each series and to write new multiplicand data once in a cycle in which each series is read.