JPH01296706A - Digital filter - Google Patents

Abstract

PURPOSE:To decrease the circuit scale and to reduce the circuit space and the cost by constituting an accumulator being a component of a digital filter separately into (n) ((n) is an integer of two or over) systems separately and using a multiplier so as to process the n-system of input digital data. CONSTITUTION:The title filter consists of a multiplier 13, an adder 18, the 1st - n-th ((n) is an integer of two or over) accumulators 20A, 20B and the 1st and 2nd data selectors 21, 22. With the input digital data of the 1st - n-th systems supplied, the output data of the 1st - n-th accumulators 20A, 20B are selected respectively in the 1st and 2nd data selectors 21, 22. The accumulators 20A, 20B being components of the digital filter are constituted separately into n-system and one multiplier 13 processes n-system of input digital data, then it is possible to use one and same circuit as the interpolation and interleaving filter. Thus, the circuit scale is decreased and the circuit space and the cost are reduced.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Prior art D. Problem to be solved by the invention E. Means for solving the problem (Fig. 1) F. Effect G. Example H. Effect of the invention A. Field of industrial application The present invention relates to a digital filter suitable for use in a recording system and a reproducing system of a recording/reproducing apparatus that records and reproduces, for example, a plurality of channels of audio signals on a magnetic tape using a fixed head.

B. Summary of the Invention The present invention separates and configures n (n is an integer of 2 or more) systems of accumulators constituting a digital filter, so that one multiplier can process input digital data of n systems. By doing so, the circuit scale is reduced, thereby reducing circuit space and cost.

C. Prior Art Conventionally, recording and reproducing apparatuses have been known that record and reproduce audio signals of a plurality of channels, for example, 24 channels, onto a magnetic tape using a fixed head.

Figures 11 and 12 show the recording system and re-i
This shows the configuration of the main parts of the system. In FIG. 11, the A channel audio signal SA and the B channel audio signal SB supplied to the input terminals (51A) and (51B) are respectively connected to an amplifier (52A).
and (52B') through a low-pass filter (
53A) and (53B). These low pass filters (53A) and (53B)
, the audio signals SA and SB are the 13th
Bandwidth is limited as shown in Figure A. In Figure 13,
Fs is, for example, 44.1 kHz.

Also, low pass filters (53A) and (53B
) output signal is sent to the sampling hold circuit (54
A) and (54B) with frequency 2F
After sampling and holding at s, the A/D converter (5
5A) and (55B) and converted into a digital signal. FIG. 13B shows the frequency spectrum at this time, in which the frequency spectrum of the original analog signal and the frequency spectrum generated by sampling are overlapped in the band from Fs/2 to 3Fs/2.

Also, A/D converter (55A) and (55B)
The output data is supplied to a digital filter (56), which limits the band as shown in FIG. 13C, and then converts the sampling frequency to Fs. The thirteenth diagram shows the frequency spectrum of the A channel and B channel data output from the digital filter (56).

Although not shown, the output data of the digital filter (56) is added with an error detection/correction code and modulated, and then supplied to the magnetic head and recorded on the tape.

By the way, in the circuit shown in FIG. 11, the gain characteristics of the low-pass filters (53A) and (53B) are
These low-pass filters (
53A), (53B) may be sampled and processed at the frequency Fs, but the 14th
As shown by the broken line in the figure, the group delay characteristics deteriorate. Therefore, in the circuit shown in FIG. 11, the gain characteristics of the low-pass filters (53A) and (53B) are
As shown by the broken line a in FIG. 4, the slope is smooth, and a digital filter (56) is also used. In that case, the group delay characteristics of the low-pass filters (53A) and (53B) are as shown by the broken line in FIG.
It becomes approximately flat at a frequency of s/2.

Next, in FIG. 12, although not shown, the signal reproduced from the tape by a magnetic head is subjected to demodulation and error detection.
The corrected A channel and B channel data are supplied to a digital filter (61).

FIG. 16A shows the frequency spectrum of input data to the digital filter (61), and is the same as that shown in FIG. 13.

In the digital filter (61), the sampling frequency is converted to 2Fs after being band limited.

FIG. 16B shows the frequency spectrum of the output data of the digital filter (61).

Also, the A output from the digital filter (61)
Channel and B channel data are respectively D
After being supplied to /A converters (62A) and (62B) and converted into analog signals, the signals are supplied to low-pass filters (64A) and (64B) via deglitch circuits (63A) and (63B). The solid line in Figure 16C is a low-pass filter (64A)
'b and (64B), and the broken line in the figure shows the frequency spectrum of the output signal of the low-pass filter (64B).
It shows the gain characteristics of A) and (64B).

Also, low pass filters (64A) and (64B)
The output signals are supplied to output terminals (66A) and (66B) via amplifiers (65A) and (65B) as A channel audio signal SA and B channel audio signal SB, respectively.

The 16th diagram shows the output terminals (6, 6A) and (66
B) shows the frequency spectra of the audio signals SA and SB obtained in FIG.

Here, Day! in the example of FIG. 11 and the example of FIG. 12! i
This RAM is RAM (Random Access Memory).
Input data DA and DB of the A channel and B channel are supplied to (71) and sequentially written.

Further, (72) is a ROM (read only memory), and coefficient data is written in advance in this ROM (72). For example, in an N-order digital filter, N pieces of coefficient data are written.

Then, data is sequentially read from the RAM (71) and supplied to the multiplier (73), and multiplied by coefficient data sequentially read from the ROM (72) and supplied to the multiplier (73).

Further, the output data of the multiplier (73) is supplied to the adder (74), the output data of this adder (74) is supplied to the adder (74) via the accumulator (75), and the output data of the multiplier (73) is supplied to the adder (74) via the accumulator (75). Multiple output data are added sequentially. And the added data is stored in the accumulator (
75) to a register (76), and output data DA' and DB' of the A channel and B channel are output from this register (76).

D Problems to be Solved by the Invention Here, the digital filter (61) is supplied with input data DA and 'DB at a sampling frequency of 2Fs from the sampling frequency of FS, but output data DA' is supplied at a period of 1/2Fs. , DB' must be output. In this case, since the interpolated data is actually zero, there is no need to perform calculations, and the number of calculations required to obtain one output data may be N/2 as shown in FIG. 18A. Therefore, the multiplier (73) is capable of calculating 2N times within 1/Fs, and this multiplier (73) is used alternately to process the input data DA and DB of the A channel and B channel. . FIG. 18B shows the output timing of output data DA' and DB'.

Further, the digital filter (56) converts the sampling frequency from 2Fs to the sampling frequency of Fs, so it becomes a thinning type N-th oversampling filter. In this case, input data DA and DB are supplied at a 1/2 Fs cycle, but output data DA' and DB' need to be output at a 1/2 Fs cycle. in this case,
The number of operations required to obtain one output data is N times, and the multiplier (73) has 2N times within 1/Fs.
The input data DA and DB of the A channel and B channel are processed. However, in this case, unlike the digital filter (61), the multiplier (73) cannot be operated alternately every N/2 times, but can only be operated alternately every N times as shown in FIG. 19A. Accumulator (75) for N/2 alternations
This is because the contents of two channels are mixed. FIG. 19B shows the output timing of output data DA' and DB'.

In this way, the digital filters (56) and (61
) are how to import input data, and ROM (7
There are many different parts such as address values in 2), and a separate circuit is required.

In addition, to simply avoid changing these, 1/F
It is conceivable to configure it using two multipliers, adders, and accumulators that can perform N operations in s, but
Since these parts account for more than half of the circuit scale of the digital filter, the circuit scale becomes enormous.

The present invention takes these points into consideration, reduces the circuit scale, and
The purpose is to reduce circuit space and cost.

E Means for Solving the Problem (Fig. 1) The present invention comprises a multiplier (13) that sequentially multiplies a plurality of input digital data by coefficient data, and a multiplier (13) that sequentially multiplies a plurality of input digital data by coefficient data.
an adder (18) to which the output data of 3) is sequentially supplied;
The first to nth (n is an integer of 2 or more) accumulators (2OA) to which the output data of this adder (18) is supplied.
(20B), and these first to nth accumulators (
a first data selector (21) to which the output data of (2OA) (20B> is supplied and the output data is supplied to the adder (18)); and the first to nth accumulators (2OA) (20B). and a second data selector (22) for selecting output data to which the output data is supplied, and when the first to nth systems of input digital data are supplied, the first and second data Selector (2
1) In (22), the output data of the first to n-th akinimulators (2OA) (20B) are selected.

F Function In the above-mentioned configuration, the accumulators (2OA) (20B) constituting the digital filter are constructed by separating n systems separately, and one multiplier (13) can handle the input of n systems with 4 cycles. Since the filter is configured to process - data, it is possible to use the same circuit as an interpolation type filter and a thinning type filter.

G. Example Hereinafter, an example of the present invention will be described with reference to FIG. This example is an example used as the digital filters (56) and (61) in the example of FIG. 11 and the example of FIG. 12, and is an example of a 96th-order oversampling filter of a thinning type and an interpolation type.

In the figure, (1) shows the digital filter of this example as a whole, and (2) is an input terminal to which input data DA and DB of the A channel and B channel are supplied.

In this case, the input data DA and DB are one sample (
1 word) m bits, for example 16 bits, and these input data DA and DB are supplied to the input terminal (2), for example in one of the following formats. The first form is
As shown in Figure 2, one sampling period (1/2Fs when used in the recording system in Figure 11, 1/Fs when used in the reproduction system in Figure 12); Figure 2A
), the input data DA is
This is a serial time division format in which DB and DB are supplied as serial data. The second format is a serial simultaneous format in which input data DA and DB are each supplied as serial data in the first half of one sampling period, as shown in FIG. 2C. In this case, the data supplied in the second half becomes undefined. In the third format, as shown in the second figure, the clock frequency is set to 172 of the second format, and the input data DA and DB are input in one sampling period.
is a serial simultaneous format in which the data is supplied as serial data. Furthermore, the fourth format, as shown in Figure 2E,
Input data DA (DAO~DAm) and DB (DBo~DAm) in the first and second half of one sampling period, respectively.
DBm) is supplied as parallel data in a parallel time division format.

Furthermore, the input data DA and DB supplied to the input terminal (2) are supplied to the 2-channel shift register (4) via the input buffer [3], and are supplied to the register sections for the A channel and the B channel, respectively. be done. In this case, as described above, the method of inputting to the shift register (4) is changed depending on the supply format of input data DA and DB. For example, when using serial time-sharing format,
First, input data DA is sequentially input as serial data to the register section for the A channel, and then input data DB is sequentially input as serial data to the register section for the B channel. Further, in the case of the serial simultaneous format, input data DA and DBfl are simultaneously and sequentially input as serial data to the register sections for the A channel and the B channel, respectively. Furthermore, in the case of parallel time division format, first the input data DA (D
Am-DAo) is input as parallel data to the register section for A channel, and then input data DB (D
Bm to DBo) are input as parallel data to the register section for the B channel.

In addition, shift registers (4) are added for each sampling period.
Input data DA and DB supplied to the register sections for A channel and B channel of , are sent to the data selector (
6). In this data selector (6), 1
In the first half of the sampling period, input data DA from the register (5A) is selected, and in the second half, input data DB from the register (5B) is selected. The input data selected by the data selector (6) is selected by the selector (7) as either two's complement or offset binary as the data format, and the order of the data is selected. Selector (8)
The data is supplied to the RAM (9) and data selector (10) via the RAM (9) and data selector (10). Input data DA and DB are sequentially written into RAM (9).

Furthermore, input data read from the RAM (9) is supplied to a data selector (10). Input data selected by this data selector (10) is supplied to a multiplier (13) via a register (11) and a buffer (12).

Further, (14) is a ROM, and coefficient data is written in advance in this ROM (14). In this example, since a 96-order oversampling filter is configured, 96 coefficient data are written.

Coefficient data read from this ROM (14) is supplied to a multiplier (13) via a data selector (15), a register (16) and a buffer (12). A multiplier (13) multiplies input data and coefficient data.

In this case, when used in the recording system shown in FIG. 11,
Input data DA and DB are output from the data selector (8) at a cycle of 1/2 Fs, but during the first 1/4 Fs period of a certain 1/Fs period, the data selector (8) is output from the RAM (9). ) 94, 92, ..., 2 pieces of input data before the input data DA output from
A is sequentially read out and supplied to a data selector (10), and this data selector (10) stores RAM (9
) from 47 input data DA and data selector (8
) is sequentially selected and supplied to a multiplier (13) via a register (11) and a buffer (12). As the 48 input data DA are sequentially supplied to the multiplier (13) in this way, the ROM (14) supplies the first, third, and 5th,..., 95th
The coefficient data of
) is fed to a multiplier (13) via a register (16) and a buffer (12).

Then, with this multiplier (13), the input data D
A and the corresponding coefficient data are sequentially multiplied.

Here, FIGS. 3A and B are 2Fs and Fs, respectively.
It shows a clock with a frequency of s, for example at time t,
The 95th input data D from the data selector (8)
When A is output, the 1st, 3rd, 5th, ..., 95th input data DA is input to the multiplier (13) as shown in FIG. 4A. supplied sequentially,
They are multiplied by the 1st, 3rd, 5th, . . . , 95th coefficient data, respectively.

In the next 1/4 Fs period, the 48 input data DB and the corresponding coefficient data are sequentially multiplied in the same way.

During the next 1/4Fs period, the input data DA output from the data selector (8) is input from RAM (9).
The input data DA 94 pieces earlier, 92 pieces earlier, ..., 2 pieces earlier are sequentially read out and supplied to the data selector (10), and this data selector (10) stores RAM
47 input data DA from (9) and one input data DA from data selector (8) are sequentially selected,
It is fed to a multiplier (13) via a register (11) and a buffer (12). As the 48 input data DA are sequentially supplied to the multiplier (13) in this way, the ROM (14) supplies the second, fourth, and The 6th, . . . , 96th coefficient data are read out, and the data selector (
15), is fed to a multiplier (13) via a register (16) and a buffer (12). Then, this multiplier (13) sequentially multiplies the input data DA by the corresponding coefficient data.Here, for example, at time t2, the 96th input data DA is output from the data selector (8). Sometimes, the 2nd, 4th, 6th, ..., 96th input data DA are sequentially supplied to the multiplier (13) as shown in FIG. It is multiplied by the second, fourth, sixth, . . . , 96th coefficient data.

In the next 1/4 Fs period, the 48 input data DB and the corresponding coefficient data are sequentially multiplied in the same way.

Furthermore, when used in the reproduction system of the example in FIG.
and DB are output, but in the first 1/4Fs period of a certain 1/Fs period, RAM (9) selects the input data 47 and 46 before the input data DA output from the data selector (8). Piece..., input data D before one piece
A is sequentially read out and supplied to a data selector (10), and this data selector (10) stores RAM (9
) from 47 input data DA and data selector (8
) is sequentially selected and supplied to a multiplier (13) via a register (11) and a buffer (12). As the 48 input data DA are sequentially supplied to the multiplier (13) in this way, the ROM (14) supplies the first, third, and 5th,..., 95th
The coefficient data of
), is fed to a multiplier (13) via a register (16) and a buffer (12). Then, this multiplier (13) sequentially multiplies the input data DA and the corresponding coefficient data. Here, FIGS. 5A and 5B show clocks with frequencies of Fs and 2Fs, respectively, and for example, at times t, /, the data selector (8
), when the 48th input data DA is output, the 1st, 2nd, 3rd, ..., 48th input data is output as shown in FIG. 6A. Data DA is sequentially supplied to the multiplier (13), and the first, third, and
It is multiplied by the 5th, . . . , 95th coefficient data.

In the next 1/4 Fs period, the 48 input data DB and the corresponding coefficient data are sequentially multiplied in the same way.

During the next 1/4Fs period, the input data DA output from the data selector (8) is input from RAM (9).
The input data DA 47th, 46th, .
47 input data DA from (9) and one input data DA from data selector (8) are sequentially selected,
It is fed to a multiplier (13) via a register (11) and a buffer (12). As the 48 input data DA are sequentially supplied to the multiplier (13) in this way, the ROM (14) supplies the second, fourth, and The 6th, . . . , 96th coefficient data are read out, and the data selector (
15), is fed to a multiplier (13) via a register (16) and a buffer (12). Then, this multiplier (13) sequentially multiplies the input data DA and the corresponding coefficient data. Here, for example, when the 48th input data DA is output from the data selector (8) at time 1, /, the first, second, and third input data DA are output as shown in FIG. Eye, 48th
The input data DA is sequentially supplied to the multiplier (13) and multiplied by the second, fourth, sixth, . . . , 96th coefficient data, respectively.

In the next 1/4 Fs period, the 48 input data DB and the corresponding coefficient data are sequentially multiplied in the same way.

Further, the output data of the multiplier (13) is supplied to the adder (18) via the register (17). The register (17) is used to shift the timing of multiplication processing in the multiplier (13) and addition processing in the adder (18) for the same input data by one clock.

Further, the output data of the adder (18) is supplied to the accumulators (2OA) and (20B) via data selectors (19A) and (19B). Then, the output voltage of the accumulator (2OA) is
-In the evening, the data selector (19A), (21) and (
22) and the accumulator (20B)
The output data is the data selector (19B), (
21) and (22). The output data of the data selector (21) is supplied to the adder (18), and the output data of the data selector (22) is supplied to the register (23).

In this case, in the data selector (21), the input data DA and DB are processed by the multiplier (13).
/4Fs period, the accumulator (2O
The output data of A) and (20B) are selected. In addition, in the data selector (19A), the adder (18) is used for each 1/4Fs period during which the input data DA and DB are processed by the multiplier (13).
and the output data of the accumulator (2OA) are selected. Also, in the data selector (19B),
Output data of the accumulator (20B) and the adder (18) are respectively selected every 1/4 Fs period during which the input data DA and DB are processed by the multiplier (13). In addition, in the data selector (22),
Output data of the accumulators (20B) and (2OA) are respectively selected every 1/4 Fs period during which the input data DA and DB are processed by the multiplier (13). Furthermore, accumulator (2OA)
and (20B) are cleared at a cycle of 1/Fs as shown in Figure 7 and J, respectively, when used in the recording system of the example in Figure 11, but when used in the reproduction system of the example in Figure 12, When it is cleared, it is cleared at a cycle of 1/2 Fs as shown in Figure 8 and J.

In addition, FIG. 7A and B are 2Fs and Fs, respectively.
8A and 8B are clocks with a frequency of Fs and 2Fs, respectively.

In the above configuration, when used in the recording system of the example in FIG. 11, the multiplier (13) is used for the first 1/4 Fs period of a certain 1/Fs period, as shown in FIG. During the period in which the 48 input data DA are sequentially multiplied, the output data of the data selector (19A), accumulator (2OA), and data selector (21) are multipliers as shown in Figure 7, F and H. The output data of (13) is added sequentially by the adder (18), and the data selector (19B)
, the output data of the accumulator (20B) and the data selector (22) are multiplied by the 96 input data DB of the B channel by the multiplier (13) and the adder (18) as shown in FIG. 7 E, G and K. and the result of the addition process, that is, the output data DB'.

During the next 1/4 Fs period, as shown in FIG.
19A), the output data of the accumulator (2OA) and the data selector (22) are shown in Figure 7.

As shown in F and K, 48 input data DA of A channel are sent to multiplier (13) and adder (
18) is the result of multiplication and addition processing, and the output data of the data selector (19B), accumulator (20B), and data selector (21) are multipliers as shown in Fig. 7 E, G, and H. The output data of (13) is sequentially added by the adder (18).

During the next 1/4 Fs period, as shown in FIG.
19A), the output data of the accumulator (2OA) and the data selector (21) is the 71st fflD.
.

As shown in F and H, the multiplier (
13) are sequentially added by the adder (18), and the output data of the data selector (19B), accumulator (20B), and data selector (22) are as shown in Figure 7 E, G, and K. The 48 input data of the B channel, DB, are multiplied and added by a multiplier (13) and an adder (18), resulting in a half operation result.

During the next 1/4 Fs period, as shown in FIG.
19A), the output data of the accumulator (2OA) and the data selector (22) are shown in Figure 7, F
and K, the 96 input data DA of the A channel are transmitted to the multiplier (13) and the adder (18).
) is the result of the multiplication and addition processing, that is, the output data DA', and the data selector (19B),
Accumulator (20B) and data selector (
21), the output data of the multiplier (13) is sequentially added to the half operation result held in the accumulator (20B) by the adder (18), as shown in Figure 7 E, G, and H. It will be added.

When used in the recording system shown in FIG. 11 in this way,
A thinning-type 96-order oversampling filter is configured, and output data DA', DB' are obtained from the data selector (22) at a cycle of 1/Fs.

On the other hand, when used in the reproduction system shown in FIG. 12, in the first 1/4 Fs period of a certain 1/Fs period, C
As shown in the figure, during the period in which the multiplier (13) sequentially multiplies the 48 input data DA of the A° channel, the data selector (19A) and the accumulator (2OA
) and the output data of the data selector (21) are sent to the multiplier (13) as shown in Figure 8, F and H.
) are sequentially added by the adder (18), and the output data of the data selector (19B), accumulator (20B), and data selector (22) are as shown in Figure 8 E, G, and K. The 48 input data DBs of the B channel are multipliers (13
) and the adder (18) perform the multiplication and addition processing, resulting in the calculation result, that is, the output data DB'.

During the next 1/4 Fs period, as shown in FIG.
19A), the output data of the accumulator (2OA) and the data selector (22) are shown in Figure 8.

As shown in F and K, 48 input data DA of A channel are sent to multiplier (13) and adder (
The result of multiplication and addition in step 18), that is, output data DA', is sent to the data selector (19B).
, the accumulator (20B), and the data selector (21) are obtained by sequentially adding the output data of the multiplier (13) by the adder (18), as shown in FIG. 8E, G, and H.

During the next 1/4 Fs period, as shown in FIG.
19A), the output data of the accumulator (2OA) and the data selector (21) are shown in Figure 8.

As shown in F and H, the output data of the multiplier (13) is added sequentially by the adder (18), and the data selector (19B) and accumulator (2
0B) and the output data of the data selector (22), the 48 input data DB of the B channel are multiplied and added by the multiplier (13) and adder (18) as shown in FIG. The result of the calculation is output data DB'.

During the next 1/4 Fs period, as shown in FIG.
19A), the output data of the accumulator (2OA) and data selector (22) are shown in Figure 8, F
and K, the 48 input data DA of the A channel are transmitted to the multiplier (13) and the adder (18).
) is the result of the multiplication and addition processing, that is, the output data DA', which is sent to the data selector (19B), accumulator (20B), and data selector (2
Is the output data of 1) the first one? As shown in IE, G and H, the output data of the multiplier (13)
The values are sequentially added in (18).

In this way, when used in the reproduction system shown in Figure 12,
An interpolation type 96-order oversampling filter is configured, and output data DA', DB' can be obtained from the data selector (22) at a cycle of 1/2 Fs.

Further, the output data of the register (23) is supplied to an overflow limiter (24) to limit the amplitude, and then supplied to a selector (25), which determines whether the data format is two's complement or offset binary. One of them is selected, and the order of the data is also selected. The output data of this selector (25) is then sent to the register (27A) via the register (26).
The output data D is supplied to this register (27A).
A' are held sequentially. Further, the output data of the selector (25) is supplied to a register (27B), and the output data DB' is sequentially held in this register (27B). In this case, the register (26) stores the output data D
This is inserted to match the timing between A' and output data DB'.

When used in the recording system shown in Figure 11, the selector (25
) is as shown in FIG. 9A, and the output data DA' and DB' have a period of l/Fs.

Here, the register (26) is supplied with a data holding clock corresponding to the end of the output data DA' as shown in the figure, and the contents of the register (26) become as shown in figure C. . Also, register (27^) and (27B
) is supplied with a data holding clock corresponding to the end of the output data DB' as shown in the same figure, and the contents of registers (27A) and (27B) are as shown in E and F of the same figure, respectively. , output data D
The timings of A' and output data DB' are matched. On the other hand, when used in the reproduction system shown in FIG. 12, the output data of the selector (25) becomes as shown in FIG. 10A, and the output data DA' and DB' have a period of 1/2 Fs. Here, the register (26) is supplied with a data holding clock corresponding to the end of the output data DA' as shown in the figure, and the contents of the register (26) are as shown in the figure C.
It becomes as shown in .

Further, as shown in the figure, a data holding clock corresponding to the end of the output data DB' is supplied to registers (27A) and (27B), and register (27A) and (27B) are supplied with a data holding clock corresponding to the end of output data DB'.
The contents of 7A) and (27B) are as shown in E and F of the figure, respectively, and the timings of output data DA' and output data DB' are matched.

Furthermore, the output data DA' and DB' from the registers (27A) and (27B) are led out to the output terminal 29) via the data selector (28), but as described above, they are output by the register (26). Data DA
Since the timings of ' and output data DB' are matched, these output data DA' and DB' are output in one of the following formats, for example.

The first format, as shown in Figure 2, has one sampling period (1/Fs when used in the recording system shown in Figure 11).
, when used in the reproduction system of the example in Fig. 12, it is 1/2Fs, and in the first half and second half of the serial mode (shown in Fig. 2), the output data DA' and DB' are output as serial data, respectively. It is a split format. The second form is
As shown in FIG. 2C, this is a serial simultaneous format in which output data DA' and DB' are output as serial data in the first half of one sampling period. in this case,
The data output in the second half is undefined. The third form is
As shown in the second diagram, the clock frequency is set to 172 in the second format, and the serial simultaneous format is used in which the output data DA' and DB' are each output as serial data in one sampling period. Furthermore, the fourth form is
As shown in FIG. 2E, the output data D A' (D A'
o ~D A'm) and D B' (D B'o ~
This is a parallel time division format in which data (DB'm) is output as parallel data.

In the example in FIG. 1, (30) is a clock counter, and this clock counter (30) has a terminal (3).
1), (32), and 33) respectively supply a master clock MCK, word synchronization signals \~'S, and power-on clear signal TCSR. The count output of this clock counter (30) is used as a timing signal and control (generator (34) of No. 8,
Write to RAM (9), read address signal 4 to DIA generator (35) and read address signal to ROM (14), supplied to ADRO generator (36).

Address signals ADIA and ADR8 generated by generators (35) and (36) are supplied to the above-mentioned RAM (9) and ROM (14), respectively.

In the example in FIG. 1, (37) is the address signal ADR.
8 is an output terminal, and (38) is an input terminal for coefficient data. Therefore, by supplying the address signal A D++o from the output terminal (37) to the external ROM (39) and supplying the coefficient data read from this ROM (39) to the input terminal (38), this ROM ( 39) to the data selector (1
5) and the input data D by supplying it to the multiplier (13) via the register (16) and the buffer (12).
It is also possible to multiply A and DB sequentially.

Thereby, various filter characteristics can be obtained.

In addition, in the above explanation, data storage>lid (8) ○
Output data is selector (7) and data 1> lid (8)
) via RAM (9) and data selector (1
]), but when similar data is supplied from the input terminal (2), this data is sent to RAM (9) via the buffer (3) and data selector (8). and a data selector (10).

In this way, according to this example, the accumulators (2OA) and (20B) for the A channel and the B channel are
) are configured separately and one multiplier (13) processes two systems of input data, so it can be used for the recording system in the example in Figure 11 and the reproduction system in the example in Figure 12. The same circuit can be used as the decimation type and interpolation type filters. Therefore, according to this example, the circuit scale can be reduced, and the circuit space and cost can be reduced. Further, when converting to an IC, there is an advantage that manufacturing becomes easier due to scale reduction.

In the above embodiment, a 96th order oversampling filter is constructed, but an Nth order oversampling filter can be constructed in the same manner. Further, according to the above embodiment, input data of two channels, A channel and B channel, is processed, but if n channels of accumulators are configured separately, one multiplier can process input data of n channels. It is clear that the system can be adapted to process input data.

H Effects of the invention According to the invention described above, the accumulators constituting the digital filter are separately configured into n systems, and 1
Since n systems of input digital data are processed by these multipliers, the same circuit can be used as an interpolation type filter and a thinning type filter. Therefore, the circuit scale can be reduced, and the circuit space and cost can be reduced. Further, when converting to an IC, there is an advantage that manufacturing becomes easier due to scale reduction.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram showing one embodiment of the present invention, Figures 2 to 1
Figure 0 is an explanatory diagram, Figures 11 and 12 are configuration diagrams of the main parts of the recording system and reproduction system, and Figures 13 to 16.
The figure is a diagram for explaining the same, FIG. 17 is a configuration diagram of a conventional example,
FIG. 18 and FIG. 19 are diagrams for explaining this. (1) is a digital filter, (9) is a RAM, (
13) is a multiplier, (14) is a ROM, (1g)
is an adder, (2OA) and (20B) are accumulators, and (21) and (22) are data selectors. Agent Mamukai Ito
Hidemori Matsukuma Figure 2 Figure 9 Figure 11 Shield of each sound β in the frequency recording system Special pot'
Figure 15 The number of five people β in the regeneration system Figure 16

Claims (1)

[Claims] A multiplier that sequentially multiplies a plurality of input digital data by coefficient data; an adder to which the output data of this multiplier is sequentially supplied; n (n is an integer greater than or equal to 2) accumulators, and these first to nth accumulators
a first data selector to which the output data of the accumulator is supplied and the output data is supplied to the adder; and a second data selector for output data selection to which the output data of the first to nth accumulators is supplied. and a data selector, when the first to nth systems of input digital data are supplied, the first and second data selectors select the output data of the first to nth accumulators, respectively. A digital filter characterized by: