JP2558356B2 - Digital to analog converter - Google Patents

Digital to analog converter

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Publication number
JP2558356B2
JP2558356B2 JP1195724A JP19572489A JP2558356B2 JP 2558356 B2 JP2558356 B2 JP 2558356B2 JP 1195724 A JP1195724 A JP 1195724A JP 19572489 A JP19572489 A JP 19572489A JP 2558356 B2 JP2558356 B2 JP 2558356B2
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Japan
Prior art keywords
digital
data
time
signal
converter
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP1195724A
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Japanese (ja)
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JPH0360223A (en
Inventor
孝 徳山
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アルパイン株式会社
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Priority to JP1195724A priority Critical patent/JP2558356B2/en
Publication of JPH0360223A publication Critical patent/JPH0360223A/en
Priority claimed from US07/795,245 external-priority patent/US5182559A/en
Application granted granted Critical
Publication of JP2558356B2 publication Critical patent/JP2558356B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

The present invention relates to a digital / analog converter, and more particularly to a digital / analog converter suitable for use in converting digital audio data into an analog signal.

<Prior Art> A compact disc player (CD player) or a digital audio tape device (DAT device) converts a digital audio signal into an analog signal and outputs it from a speaker.

A commonly used digital / analog converter (DA converter) for playing music converts digital data into a direct current, converts the current into a voltage for each sampling period, and holds the voltage. The signal is shaped into a continuous smooth analog signal by the filter and then output. The most serious problem with such a DA converter for reproducing music is the phase distortion due to the low-pass filter, which causes deterioration in sound quality.

Therefore, the inventors of the present application have proposed the digital-analog converter shown in FIG. 10 as Japanese Patent Application No. 62-78878. This digital-analog converter includes a digital data generator 10 that generates digital data at predetermined time intervals T,
The latest m digital data V generated at every predetermined time T
-4 to V +4 are sequentially shifted and stored while sequentially storing a digital data storage unit 11 having a shift register (11 -4 to 11 +4 ) configuration and a unit pulse response signal SP (see FIG. 11). , And the m number of analog partial signals S -4 obtained by dividing
To S + 4 and unit pulse response signal generator 12 with partial signal generator (12 -4 to 12 +4) repeatedly generated every (FIG. 12 reference) time T, each subsignal S i and the Multipliers 13 each having a multiplication DA converter (13 -4 to 13 +4 ) for multiplying the predetermined digital data V i stored in the shift register corresponding to the partial signal, and the output of each multiplication DA converter It has a combining unit 14 that combines the voltages and outputs an analog signal.

According to this method, it is possible to smoothly interpolate between the digital data of the cycle T using the pulse response signal without using a low-pass filter, and to generate a continuous analog signal without phase distortion.

<Problems to be Solved by the Invention> However, in the digital-analog converter of FIG. 10, a digital storage unit, m analog partial signal generators,
Requires m multiplying DA converters and analog synthesizer,
The device becomes large in size and the number of parts increases, resulting in large size, which is not suitable for weight reduction and miniaturization. Furthermore, due to the increase in size and the number of parts, a special IC chip for multiplication DA converter is required. Therefore, there is a problem that it becomes considerably expensive.

In addition, since there are many adjustment points with the variable volume in the multiplication DA converter and the analog partial signal generator, it takes a lot of skill to make adjustments, and it is necessary to readjust them when re-adjusting due to aging or when changing the unit pulse response signal waveform. Adjustment was troublesome.

Further, since the adjustment point shifts depending on the temperature, if the adjustment is strictly performed according to the temperature, the adjustment work becomes more and more troublesome.

Further, since each of the partial signal generators and the multiplying DA converter use a large number of parts with large variations such as capacitors, there is a problem that variations easily occur, and this variation causes minute spike noise to be added to the analog signal. .

In view of the above, an object of the present invention is to provide a digital action converter that can minimize the number of adjustment points and the analog circuits that vary widely.

Another object of the present invention is to provide a digital-analog converter that interpolates input digital data with a plurality of digital data and DA-converts the interpolated data to output a continuous analog signal.

Still another object of the present invention is to digitally generate a unit pulse response signal, digitally interpolate between input digital data using the unit pulse response signal data, and DA-convert the interpolation data. Thus, an analog-digital converter that outputs a continuous analog signal of input digital data is provided.

<Means for Solving the Problem> In the present invention, the above-mentioned problem is a partial signal time-series data generator that digitally repeatedly generates each partial signal of a unit pulse response signal with time-series numerical data, and the latest m A digital data storage unit that sequentially stores the digital data of
This is achieved by a digital arithmetic unit and a converter for converting output data of the digital arithmetic unit into analog.

<Operation> The unit pulse response signal is divided at a predetermined time interval T and m
Each of the partial signals is digitally repeatedly generated with n time-series numerical data, and the latest m digital data generated at every predetermined time T are sequentially stored.
The time-series numerical data of each partial signal and the digital data corresponding to the partial signal are respectively multiplied, and the multiplication results are added and converted into an analog signal.

<Embodiment> FIG. 1 is a block diagram of a digital-analog converter according to the present invention. Reference numeral 1 denotes a digital input interface circuit for converting digital audio data from a CD player, a DAT device, or a satellite broadcasting tuner (not shown) into a form that can be processed in the subsequent stage for each of L channel and R channel, and outputting the digital input data.
Reference numeral 2 is a digital signal processing block, for example, a digital signal processor (DSP) that digitally interpolates between digital data input at a sampling period T. Reference numeral 3 is a digital output interface, 4 is a DA converter for DA converting the interpolation data output from the digital signal processing block 2, and 5 is a buffer circuit. Although the digital signal processing block 2, the digital output interface circuit 3, the DA converter 4, and the buffer circuit 5 are provided for each of the L channel and the R channel, FIG. 1 shows only one channel.

The digital signal processing block 2 shifts and stores the latest m digital data Xi (i = 1 to m) generated every predetermined time T, and a unit pulse response signal at a predetermined time interval. Divide by T (m + 1)
Number of time-series numerical data obtained by sampling each partial signal SPj (j = 0 to m) at a sampling cycle T / n according to the following table. , The partial signal time-series data generator 2b repeatedly generated, the time-series numerical data of each partial signal output from the partial signal time-series data generator 2b, and the digital data corresponding to the partial signal are respectively multiplied and multiplied. It has a digital operation unit 2c for adding the results.

The partial signal time-series data generator 2b has a memory for storing the numerical values in the above table and each partial signal SPj (j = 0 to 0) for each T / n.
m) at a predetermined time T · i / n (i = 1,2, ... n), numerical data c 0i , c 1i , c 2i , c 3i , ..., c mi are read out and the digital arithmetic unit 2c is read. It is composed of a reading unit for inputting to.

As shown in FIG. 2, the digital input interface circuit 1 includes a bi-phase signal receiving circuit 1a that receives a bi-phase modulated data string, a waveform shaping circuit 1b that shapes the bi-phase modulated data, and a bi-phase data. A data format conversion circuit 1c that demodulates and converts to a format that can be processed at the subsequent stage and outputs it, and bit clock BCL, word clock WCL, channel clock LRCK, data (L channel data, R
Data timing circuit 2d for outputting channel data)
have.

As shown in FIG. 3, the digital output interface circuit 3 has two stages of data buffer circuits 3a and 3b, a ternary counter 3c, and a decoder 3d, and each data buffer circuit has three registers of 8 bits each. The counter 3c counts up each time 8-bit data is input, and the decoder 3d decodes the count value to instruct the registers R11-R13 that should store 8-bit input data. To do. The data input from the digital signal processing block 2 in 8-bit units is sequentially stored in the registers R11, R12, R13 of the data buffer circuit 3a, and the 24-bit data stored in the data buffer circuit 3a is the data buffer of the next stage. The data is shifted in parallel to the circuit 3b, 24-bit data is output from the data buffer circuit 3b to the DA converter 4 (FIG. 1), and at the same time, the next data is transferred to the previous data buffer circuit 3a.
It is designed to be input to.

FIG. 4 is a block diagram of the digital signal processing block 2, and FIG.
The figure is a time chart showing a word clock WCL for data shift and a clock MCL showing the timing of reading and multiplication of time-series numerical data.

In FIG. 4, M1 to Mm are m generated at each time interval T.
Shift registers for sequentially storing the latest digital data Xi, K0 to Km are partial signals SPj (j = 0).
~ M) time-series numerical data c 0i , c 1i , c 2i , c 3i , ..., C mi at a predetermined time T · i / n, and digital data stored in the shift register corresponding to the partial signals. A multiplier that multiplies X0 to Xm at each time T / n, and SUM is an adder that adds the multiplication results. Numerical data indicated by is output for each T / n.

Therefore, in FIG. 4, n = 4, m = 2, and the four time-series numerical data of the three partial signals SP0 to SP2 are SP0: c 01 , c 02 , c 03 , c 04 SP1: c 11 , c. If 12 , c 13 , c 14 SP2: c 21 , c 22 , c 23 , c 24 , the 6th
The time-series data of the unit pulse response signal shown in the figure can be obtained.

FIG. 7 is a digital data sequence, FIG. 8 is a data sequence of a pulse response signal for each digital data, and FIG. 9 is an explanatory diagram in which the time axis between the time slots T 1 of FIG. 8 is enlarged.

Assuming that the digital data in each time slot Ti for each time T is Xi as shown in FIG. 7, the continuous time signal for the digital data is the pulse response signal weighted by each digital data Xi input momentarily. Obtained by stacking along the axis.

Since the data sequence Mi of the pulse response signal for each digital data Xi is the time-series numerical data (FIG. 6) of the unit pulse response signal multiplied by Xi as shown in FIG. If they are combined in turn, Y 11 to Y 14 in FIG.
As shown in, the four digital data can be interpolated within the time width T.

Incidentally, assuming that the digital data X0 is generated in the time slot T 0 and the digital data X1 and X2 are stored in the shift registers M1 and M2 of FIG. 4 at this time, the time T / 4
Each multiplier K0, K1, K2 time-series numerical data c 01, c 11, c 21 , c 02, c 12, c 22, c 03, c 13, c 23 each, c 04, c 14, c 24 Are sequentially input, and from each multiplier K0, K1, K2, as shown in FIG. 9, X 0 · c 01 , X 1 · c 11 , X 2 · c 21 , X 0 · c 02 , X 1 · c 12 , X 2・ c 22 , X 0・ c 03 , X 1・ c 13 , X 2・ c 23 , X 0・ c 04 , X 1・ c 14 , X 2・ c 24 are output and adder SUM Then, Y 11 , Y 12 , Y 13 , and Y 14 are sequentially output.

After that, the output data Yij of the digital signal processing block 2
Is applied to the DA converter 4 via the digital output interface 3, converted into an analog signal here, and output via the buffer circuit.

In summary of the digital-analog converter of the present invention, the input digital data string of the sampling period T is interpolated by a plurality of digital data using the time-series numerical data of the unit pulse response signal, and the interpolated data is interpolated. Converts to an analog value and outputs the analog signal through a buffer circuit.

Although the case where n = 4 and m = 2 has been described above, it is possible to generate time series numerical data of an arbitrary unit pulse response signal waveform by changing n, m and time series numerical data Cij. it can.

<Effects of the Invention> As described above, according to the present invention, it is configured to digitally interpolate between input digital data and DA-convert the interpolated data to output a continuous analog signal. Therefore, even if a low-pass filter is not used, A smooth analog signal with little distortion can be obtained.

Further, according to the present invention, since the analog circuit is only the DA converter at the final stage, no adjustment is required, and it is possible to withstand aging and temperature changes.

Further, according to the present invention, since all except the DA converter at the final stage can be configured by digital processing such as a digital signal processing block, the device can be downsized, the number of parts can be reduced, and the cost can be reduced. The signal waveform can be easily changed digitally.

[Brief description of drawings]

1 is a block diagram of a digital-analog converter according to the present invention, FIG. 2 is a block diagram of a digital input interface circuit, FIG. 3 is a block diagram of a digital output interface circuit, and FIG. 4 is a digital signal processing block 2. Fig. 5, Fig. 5 is a clock time chart, Fig. 6 is an explanatory diagram of time series numerical data of a unit pulse response signal, Fig. 7 is a digital data string, and Fig. 8 is a pulse response signal for each digital data. Example of sequence numerical data, FIG. 9 is an explanatory diagram in which the time axis of the time slot T 1 is enlarged, FIG. 10 is a block diagram of a conventional digital-analog converter, FIG. 11 is a unit pulse response signal waveform diagram, and FIG. The figure is a partial signal waveform diagram. 2 ... Digital signal processing block 2a ... Digital data storage unit 2b ... Partial signal time series data generation unit 2c ... Digital operation unit 4 ... DA converter

Claims (1)

(57) [Claims]
1. A unit pulse response signal is divided at a predetermined time interval T into m partial signals, and n partial time series numerical data obtained by sampling each partial signal at T / n are digitally obtained. A partial signal time series data generation unit that repeatedly generates, a digital data storage unit that stores the latest m pieces of digital data that occur every predetermined time T, and an i-th time when the time interval T is divided into n equal parts. In i · T / n, a digital operation unit that multiplies the i-th time-series numerical data of each partial signal by the digital data stored in the storage unit corresponding to the partial signal and adds the multiplication results And a converter for converting digital numerical data output from the digital operation unit into analog, a digital-analog converter.
JP1195724A 1989-07-28 1989-07-28 Digital to analog converter Expired - Fee Related JP2558356B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1195724A JP2558356B2 (en) 1989-07-28 1989-07-28 Digital to analog converter

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1195724A JP2558356B2 (en) 1989-07-28 1989-07-28 Digital to analog converter
US07/795,245 US5182559A (en) 1989-07-28 1991-11-15 Digital-analog converter with plural coefficient transversal filter

Publications (2)

Publication Number Publication Date
JPH0360223A JPH0360223A (en) 1991-03-15
JP2558356B2 true JP2558356B2 (en) 1996-11-27

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653835A (en) * 1992-08-03 1994-02-25 Mitsubishi Electric Corp D/a converter
JP3992849B2 (en) 1998-07-16 2007-10-17 新潟精密株式会社 Digital-analog converter
US6968857B2 (en) * 2003-03-27 2005-11-29 Emerson Process Control Pressure reducing fluid regulators

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0479180B2 (en) * 1983-06-18 1992-12-15 Sony Corp

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