JPS60205671A - Convolutional arithmetic circuit - Google Patents

Abstract

PURPOSE:To make good convolutional operation in time area and enable multifarious use by providing a cumulative adding device, a selecting device, a ROM address counter, a RAM address counter and storing devices. CONSTITUTION:The cumulative adder 41 multiplies a digitalized coefficient data string and a multiplicand data string and makes addition, and connected in parallel to the first ROM43 and the second ROM44 which store a peculiar coefficient data string through a ROM selector circuit 42. Input terminals AD0-AD3 are connected to the output terminal of a ROM address counter 45, and address signal of a ROM47 is formed by an address counter 48. By providing the adder 41, the circuit 42 and the counters 45, 48 to constitute an i circuit and by using the first ROM43 and the second ROM44 selectively, convolutional operation can be changed according to use or preference. Thus, good convolutional operation can be made in time area, and can be used multifariously.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a nine-fold convolution calculation circuit applied to a digital signal processing system such as a digital filter.

[Technical background of the invention and its problems]

Recently, in the field of audio equipment, PCM (Pulse Code Modification) technology has been used to achieve high-fidelity playback as much as possible in digital equipment such as PCM recorders and DAD (Digital Audio Disk) players. Recording and reproducing devices are becoming popular. Therefore, the basic configuration of this digital recording/reproducing apparatus will be explained with reference to FIG. First of all,
Analog signals such as audio signals supplied to the large sword terminal I are
After unnecessary high-frequency components are removed by a low-pass filter, the signal is supplied to a sample-and-hold circuit (2) and sampled at a periodic interval of a predetermined sampling frequency (for example, 1, or 44.1 KHz in the case of an AD player). This sampled analog signal, VD (an
After being quantized and encoded into a digital signal by the alog to digital converter (141), and subjected to error correction code addition and digital modulation processing by the digital processing circuit (to), it is recorded on a tape, disk, etc. The reproduced signal outputted from the recording medium Qe during reproduction is demodulated by the digital demodulation processing circuit αη and corrected for errors caused by defects in the recording medium Utt, etc., and becomes the original digital signal. This digital signal q i)/A(digita
l to analog) is converted into a step-like analog signal by the converter ue, and the low-pass filter (6
) to remove harmonic components that become noise, and output it as a continuous analog signal, that is, the original audio signal, through the output terminal (2).

By the way, when the above digital recording/reproducing device samples an analog signal and restores it again, harmonic components that are folded back around the sampling frequency are generated in the frequency components included in the original IH signal, resulting in Since the harmonics are distributed near the upper limit of the band of the original signal, it is necessary to remove them, so the low-pass filter 4 is provided with steep filter characteristics. However, a digital filter (2) shown by the dotted line in Fig. 1 is inserted after the A/D converter α or before the D/A converter 4 to remove the harmonic components at the digital signal stage. By removing this, the filter characteristics of the low-pass filter 0 can be reduced. At this time, an operation is performed in the digital filter 9 to increase the sampling frequency of the input signal by several times or even by a fraction.

Here, the above-mentioned digital filter eυ will be explained. Usually, a digital filter consists of an input sequence (xn) and an impulse response sequence (hi) ("'Os
The output sequence (yn) is obtained by a finite convolution operation with LL..., m). In the past, as shown in Figure 2, the input series (xn) is processed by FFT.
(Fast 7-Rier transformer) 6 transforms into the frequency domain xn, and the product Yn of this and the frequency characteristic H (b) of the impulse response sequence (hi) is calculated by a multiplier), and then IFFT (Fast Fourier Inverse Transformer)
&l to obtain a time domain output series (Yn). This method has faster calculation speed than the method of directly convolving the discrete input sequence (xn) and the impulse response sequence (h) in the time domain, so it is possible to widen the band of input signals that can be processed.

However, when designing a digital filter using this method, the
- Since hardware is required, the circuit configuration becomes large, and the cost is also relatively high. Therefore, there are many practical disadvantages in using such a digital filter in the above-mentioned digital recording and reproducing apparatus.

Note that the above method of convolution calculation in the time domain conventionally involves sequentially delaying each input signal of the input series (xn) using a plurality of delay elements, and combining these delayed input signals with the impulse response series 1h1). Each coefficient data is simultaneously multiplied by a plurality of multipliers and the values are added. However, this method requires an enormous number of delay elements and multipliers. Furthermore, if the above-mentioned multipliers were to be used in a time-sharing manner, there would be a problem that the calculation speed would be slow.

Therefore, it is difficult to develop a convolution arithmetic circuit with a simple configuration and capable of high-speed processing, which has not yet been realized by Digital Filter Corporation and which is used in the digital recording and reproducing device described above and has sufficient functionality. It was wanted. (9) When using the convolution calculation circuit as a digital filter, the coefficient sequence that becomes the impulse response sequence can be freely set according to the desired filter characteristics, so it can be used in a variety of ways depending on the purpose of use or preference. ideal.

[Purpose of the invention]

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide a convolution operation circuit that performs a good convolution operation in the time domain and can be used in a variety of ways.

[Summary of the Invention] The convolution arithmetic circuit of the present invention includes a cumulative addition means for multiplying and adding a coefficient data string and a multiplicand dibinary sequence, which are both digitized, and a multiplicand data string supplied to the cumulative addition means. input means for introducing input data to be multiplicand data into the first storage means; first counting means for addressing the first storage means; a second storage means storing a plurality of sets of coefficient data strings to be supplied to the addition means; a second counting means for specifying addresses of the second storage means; and a plurality of coefficient data strings stored in the second storage means. The present invention is characterized by comprising a selection means for selecting a coefficient data sequence to be supplied to the cumulative addition means from a set of coefficient data sequences.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

First, FIG. 3 shows the circuit configuration of an embodiment of the convolution calculation circuit of the present invention. In the figure, one input terminal (IhL
8B to IhMsn) are connected in parallel to the first ROM@3 and second ROMg4, each storing its own coefficient data string h(n), through a ROM selection circuit (to be described later). Address input terminal (AD.

~AD3) are connected to the output terminals (00~θ5) Ic of ROM address counter 4, which is a hexadecimal synchronous counter. Also, the other input terminal (I
XL8B to IXM8B) input data supplied from an external device to its respective pins) (XL8jl-XM8B
) is input at a predetermined timing via a plurality of tri-state buffers arranged in parallel corresponding to
The input/output terminal (OLs n-l10M5B) of v) will input the multiplicand data string ), and the counting operation of this RAM address counter is controlled by the RAM control circuit. In addition, this RAM control circuit) is R, A
The operation of the RAM (e) is controlled according to the output of the ROM address counter (the RAM address counter), and the operation mode of the RAM (e) and the operation of the tri-state buffer are controlled by the control signal of the RAM address counter. R
/W signal is generated.

ζHere, the ROM selection circuit) sends only the output of one of the first ROMg3 and the second ROMg4 to the cumulative adder (
6), and the selection is made by the U/D signal. That is, when the U/D signal is set to rHJ level, the tri-state output of the second OM@ilQ becomes NO.
When the first ROMg is in the high impedance state, the output of the first ROMg is supplied to the cumulative adder @υ. Also, if the U/D signal is
In contrast, when the second ROJ4 is set to the "L" level, the output of the second ROJ4 is supplied to the cumulative adder @p. Therefore, the first
Coefficient data strings having different characteristics are stored in the ROM1i19 and the second ROMg4, and by switching between them as needed, it is possible to satisfy two functions with one circuit.

Next, the operation of this embodiment will be specifically explained with reference to FIG. Therefore, 16 coefficient data h(0) to h(g) for quadrupling the sampling frequency are stored in the 11th (,0M1l13), and the U/D signal is at the rHJ level. Assume that this first ROMvL3 is used.In addition, in Fig. 4, the R/W signal is rH
When the J level input data is input to the cumulative adder (b) and R
AM(e) and when it is at “L” level, the RAM
@7) becomes the read mode. Also, the RAM output (represented by t in the figure) is output from the RAM according to the RAM address.
The ROM output output (n) (represented by y in the figure) shows the coefficient data output from the first ROMg3 according to the ROM address.
Soshite, C0NV, 0UT (11 forces including Tatami) y(k
) RAM output and RO in the % product adder (6)
This is the output obtained as a result of cumulatively adding the M outputs (n). -R when the nine-dashi RAM@7) is in write mode.
The input data converted to AM output is directly used for calculation.

Therefore, the convolution operation performed at the timing shown in FIG. 4 is as follows: y(4j) -Σ j-p)h(4p+x)P
=O y(4j+2)-Σ x(j-p)h (4P+2)P
vote O )'(4j+3),, J X(j-P)h(4F+3
) is defined as Toυ, and the four convolution operations in the above equation are executed every time one sample of the input signal is input. That is, C0NV, OUT y(k) is YQa-
xta) htt) + (2) h (a) + X (L) 11 (
9)+X(0)hoa. Note that the detailed operation can be confirmed from FIG. 4, so the explanation will be omitted.

As described above, the convolution operation circuit of this embodiment realizes the convolution operation in the time domain with a simple configuration, and moreover, by selectively using the first OM&l and the second ROM@4. The convolution operation can be switched depending on the application or preference. for example,
If the coefficient data string for multiplying the sampling frequency by μ is stored in the second ROM@4, the relationship between the two functions will become stronger. If you set the coefficient data string in , you will be able to select it according to your preference.

Note that the present invention is not limited to the above embodiments, and various changes and applications are possible. For example, it is conceivable to provide a circuit for selecting a ROM on the address input side, and it is possible to prepare a coefficient data string (the number of ROM sides can also be set freely).

〔Effect of the invention〕

SUMMARY OF THE INVENTION As described above, it is possible to provide a convolution operation circuit that performs good convolution operations in the time domain and can be used in a variety of ways.

[Brief explanation of drawings]

Figure 1 is a block diagram showing the basic configuration of a digital recording/reproducing device, Figure 2 is a block diagram showing the basic configuration of a conventional convolution operation circuit, and Figure 3 is a block diagram showing the basic configuration of a conventional convolution operation circuit. FIG. 4 is a circuit configuration diagram showing one such embodiment, and a timing chart for explaining the operation of the same embodiment. 41...cumulative adder, 42...)LO
M selection circuit, 43...Ith ROM, 44...
...2nd ROM, 45...ROM address counter, 47...RAM, 48...R
AM address counter. Agent Patent Attorney Kensuke Chika (1m or 1 person) 1st
Figure 2 Figure 3

Claims (1)

[Claims] a cumulative addition means for multiplying and adding a coefficient data string and a multiplicand data string that are both digitized; a first storage means for storing the multiplicand data string supplied to the cumulative addition means;
an input means for introducing input data to be multiplicand data into the first storage means; a first counting means for specifying the address of the JIII storage means; and a plurality of coefficient data strings supplied to the cumulative addition means. a second storage means for storing a set of data; and a second storage means for specifying an address for the second storage means.
counting means, and the cumulative addition means from the plurality of sets of coefficient data strings stored in the second storage means.