JP2668676B2 - Filter parameter supply device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a filter filter for a digital filter.
Electronic musical instruments and other musical tone generators for parameter supply devices
Functioning equipment or digital audio processing equipment, etc.
Are used. [Prior Art] Using digital filters in the tone circuit of electronic musical instruments
Is, for example, indicated in JP-A-59-44096.
I have. One set of filter parameters is a digital filter
And the filter characteristics (amplitude vs. frequency)
Characteristics) are set. Corresponding to each content of timbre determinant
A plurality of sets of filter parameters are stored in a memory in advance,
A set of filters depending on the selected timbre determinants
The parameters are read. [Problems to be Solved by the Invention] Conventionally, a plurality of timbre determining factors (for example,
Key touch, range, steady tone selection information,
Information, such as the amount of operation of manual controls such as brilliance controls.
If you want to perform different tone control depending on
Multiple sets of filters with one-to-one correspondence to constant factor combinations
The parameters had to be stored in memory.
For example, 44 ranges, 16 key touch groups, 32
One pair for all combinations of street tone (22,528 ways)
If you want to store the filter parameters individually corresponding to 1
Parameter memory, 22528 sets of parameters are stored
A large capacity is required. The present invention has been made in view of the above points, and
Depending on the combination of timbre determinants (parameter determinants)
Supply a set of filter parameters to a digital filter
The parameter memory capacity
Filter parameter supply device that can save
It is something to offer. [Means for Solving the Problems] The filter parameter supply device according to the present invention
Parameter storage means storing a set of filter parameters
And, corresponding to a combination of a plurality of parameter determinants,
Filter parameters to be read from parameter storage
The address of the parameter in the parameter storage means.
Address data is stored in each
The parameter determination is included in each of the address data.
Parameter storage means for different combinations of constant factors
Characterized by the fact that some address the same address in
Parameter address storage means and parameter determination
In response to an input that specifies a combination of factors,
Corresponding to the combination of parameter determinants specified
Parameter address storage means for storing fixed address data
From the memory, and according to the read address data,
Reading a set of filter parameters from the parameter storage means
It is characterized in that it has read-out means for projecting. this
FIG. 1 is a schematic diagram of FIG.
Parameter storage means, 111 is a parameter address storage
Stage, 112 is read means, 113 is a set of read filters
A digital filter to which the parameters are supplied.
As the data showing the parameter determinant, for example,
Key code indicating a pressed key, touch data indicating a key touch,
Tone code indicating the selected stationary tone, depending on the passage of time
Information, appropriate manual operator output information, etc.
Can be. [Action] The parameter corresponding to the combination of
The filter parameters are read directly from the storage means
Instead of the parameter address storage means
Address data for reading the data storage
The parameter storage means according to the address data.
A set of filter parameters is read from. Follow
Corresponding to the combination of parameter determinants.
The data is stored in the parameter address storage means.
Yes, it is not a parameter storage means. Parameter address
The storage means simply stores only the address data.
There is not so much capacity required. Parameters
The storage means stores a plurality of sets of filter parameters
And a set of filter parameters is a multi-order filter.
Relatively large capacity.
Required. However, it corresponds to the combination of parameter determinants
Parameters are read based on the stored address data.
Since it is an indirect address method that is designed to be issued,
One-to-one correspondence for all combinations of data determinants
It is no longer necessary to store data parameters
The number of parameter sets less than the number of combinations
Will be sufficient. That is, the parameter
Filter parameters even if the combination of
May be able to use common things
Is a set of parameters stored in the parameter storage means.
You can reduce the number, which saves memory space
it can. For example, from the above-mentioned range, key touch, and tone type
For 22528 combinations, only 2620 sets of parameters
If the meter is stored in the parameter storage means,
This is shown in the examples below. like this
In some cases, parameters are determined according to a certain combination of parameter determinants.
The address data read from the meter address storage means
Address data read according to another combination
May be the same, and the parameter storage
Read the same parameters for each of the different combinations of
put out. [Effects of the Invention] Therefore, according to the present invention, the combination of parameter determinants
Stored in the parameter storage means in comparison with the total number of
Since the number of parameter sets can be reduced, memory
You can save space. Especially, key touch and range
Various types of parameter determinants such as time
When trying to perform delicate tone control with various combinations
The same as the saved parameter memory configuration
This is advantageous because such tone control can be performed.
You. That is, according to the present invention, a plurality of parameter
Reading parameter storage means corresponding to each combination of constant factors
Parameter address storage means for outputting address data
You can store multiple parameters in each
Various control of timbre control according to the combination of meter determinants
High quality products that can be performed in a state and are optimal for each combination
It has the effect that quality tone control can be performed.
And each of these address data contains
Parameter memory for different combinations of data determinants
Note that some indicate the same address in a column.
The parameter storage means
Determine the number of parameters actually stored,
It can be smaller than the number of combinations of factors,
The effect is that the amount can be saved. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Let me explain. <Description of Overall Configuration of One Embodiment> In FIG. 2, the keyboard 10 indicates the pitch of a musical tone to be generated.
It has a plurality of keys for setting. Key touch detector
11 detects the touch applied to the key pressed on the keyboard 10
The initial touch or after
Any of the switches may be detected. Tone selection
The device 12 is operated from a group of controls for selecting a tone of a musical tone to be generated.
It consists of Pitch bend operator 13 should occur
The pitch of the musical tone is continuously modulated according to the manipulated variable.
For example, a dial-type control
You. The microcomputer 14 has a CPU (central processing unit).
G) RO that stores programs and other data
M (read only memory) 16, working and data
Includes RAM (random access memory) 17 for storage
Via the data and address bus 28
Sends and receives data to and from the circuit and depresses keys on the keyboard 10.
Detection processing and generation of pressed keys for multiple sound channels
Tone assignment processing, tone color selection operation of the tone color selection device 12
Detection processing, detection of the operation amount of the pitch vent operator 13
Processing and other various processing are executed. The tone generator 18 has multiple pronunciation channels
Capable of independently generating digital tone signals
And the key code KC that shows the key assigned to each channel.
And a key-on signal KON that indicates whether the key is on or off.
The necessary data is transferred from the microcomputer 14 via the bus 28.
And receive digital music on each channel based on this.
Generates a sound signal. The tone generator 18 has a
Switch synchronization signal generation circuit 19, and each channel
A pitch synchronization signal that synchronizes with the pitch of the generated tone signal
Occurs for each channel. In the use of this embodiment, the tone generator 18
Is the total of 16 channels of the 1st to 16th channels (Ch1 to Ch16)
The digital tone signal is generated in a time-division manner in the channel. G
Output from the time generator 18 in a time-division multiplexed manner.
The digital tone waveform sample value data is indicated by TDX. Master
Master clock pulse generated from clock generator 20
φ controls the basic operating time of the tone generator 18
Is what you do. Digital tone waveform sample value data
One cycle of TDX time division multiplexing is the master clock pulse.
64 cycles of each cycle φ.
When the time slots for each cycle are numbered from 1 to 64
It is as shown in FIG. The figure shows a multiplexed digitizer.
Le tone waveform sampled data TDX channel timing
The specifications of groups 1 to 16 are also shown. For example, the first channel
Data TDX is divided into 4 slots of time slots 33 to 36
Have been assigned. In the specification of this embodiment, the tone waveform sample value data is used.
Data TDX uses 16 channels of data as described above.
Are multiplexed and output.
The period signals SP1 and SP2 are divided into two systems and the time is divided every 8 channels.
The output is divided and multiplexed. One pitch synchronization signal PS1
Is the time division multiplex of the first to eighth (Ch1 to Ch8) pitch synchronization signals.
The channel timing is shown in FIG.
It seems. The other pitch synchronizing signal PS2 is shown in FIGS.
Time-division multiplexed pitch synchronization signals (Ch9 to Ch16)
Therefore, the channel timing is as shown in FIG.
As can be seen from the figure, the pitch synchronization signal of each channel
PS1 and PS2 occur in the width of one time slot, and the time division
One cycle of multiplexing is 8 time slots. Two series of adaptive digital filter devices (hereinafter
(ADF is sometimes abbreviated as ADF) 21 and 22
Digital filter configured for filtering
And 8 channels each in the specification of this embodiment.
Filtering of the tone signal for
The ADF21 is a filter filter for the tone signals of channels 1 to 8.
ADF21 performs music on channels 9 to 16
Filter sound signals. Inside this ADF21,22
Is a digital filter circuit or filter
Control the supply of parameter memory and filter parameters
Synchronized with the pitch of the tone signal to be filtered and various circuits
The control circuit and filter
Pitch to output the applied tone signal in synchronization with the pitch
Includes circuits for various functions, such as a synchronous output circuit.
The configuration is suitable for filtering sound signals. Digital music output from tone generator 18
The waveform sample value data TDX is input to ADFs 21 and 22.
The pitch synchronization signal PS1 of the first to eighth channels is ADF
21 is input to the pitch synchronization signal of the 9th to 16th channels
PS2 is input to ADF22. ADF21 and 22 have the same pitch
Time when the period signals PS1 and PS2 were generated (signal became "1")
The data TDX of the channel corresponding to the slot is acquired internally.
The sampled data of that channel
Perform a filter operation. Therefore, in one ADF21,
In response to the pitch synchronization signal PS1,
The filter operation of the sound signal is performed, and the other ADF22
9th to 16th channel tone signals according to the sync signal PS2
Performs a signal filter operation. In this way, ADF21 and 22
Filter calculation unit time (synchronized with sampling cycle
Of the tone signal to be filtered.
The pitch is synchronized with the pitch, and the filter
As the calculation time fluctuates, the flow formant characteristics
Filtering is realized. Note that the basic operation of the circuit
With master clock pulse φ to control the timing
System sync pulse SYNC is given to ADF21 and ADF22.
You. The system sync pulse SYNC is as shown in FIG.
This is a pulse that occurs in a 64 time slot period and
Time-division multiplexing of the tone signal
You. Also, the ADFs 21 and 22 control the filter operation.
Data for the microcontroller via the bus 28
Given under the control of the data 14. In the ADFs 21 and 22, the actual filter operation
Works in synchronism with the pitch of the tone signal to be filtered.
As well as filtered tone waveform sample values
Data is re-sampled in synchronization with the pitch,
It is designed to output with all pitches synchronized
You. This filtered data is resampled in sync with the pitch.
Pitch synchronization signals PS1 and PS2 are also used for pulling.
It is. ADF21 and ADF21 digital output of each channel
The sound waveform sample value data is summed by the accumulator 23,
Musical sound waveform that sums up sample value data for 16 channels
Find sample value data. Output data of accumulator 23
Analog tones with digital / analog converter 24
It is converted into a signal and is pronounced via the sound system 25. In the specifications of this embodiment, the supply of filter coefficients is 2
Controlled in one mode. One is "Static mode
This means that the filter coefficient must be
This is the mode that does not change. The other is "Dynamic model.
Mode, which is the filter coefficient
Is a mode that changes over time.
It is possible to obtain the temporal change of the timbre. Static mode
Filter coefficients for ADF21 and ADF22
Stored in the parameter memory. dynamic
The filter coefficients for the mode are
Stored in the parameter memory 26,
Timed under the control of the computer 14
The data is supplied to ADFs 21 and 22 via a bus 28. Dyna
Mick / static selection switch 27 has a filter coefficient
To select in which mode to control the supply of
Switch. An example of the clock frequency is the master
The clock pulse φ is about 3.2 MHz, and the pitch synchronization signal PS
Repetition of 1 PS2 time division 1 cycle (8 time slots)
The frequency is 400 kHz and the digital tone waveform sample is
One time-division cycle of value data TDX (1 in the filter
The repetition frequency of the calculation cycle) (64 time slots)
50 kHz. Next, a detailed example of each circuit in FIG. 2 will be described.
You. <Generation of Pitch Synchronization Signal> FIG. 4 shows an example of the pitch synchronization signal generation circuit 19.
This is the pitch of one system (channels 1 to 8).
H sync signal PS1 is generated. The other pitch synchronization signal P
S2 is also generated by the same configuration as in FIG. The pitch synchronization signal PS1 is read from the P number memory 29.
The P-numbers are time-divided by the counter 30 for each channel.
It is generated based on counting. What is P number?
A cycle corresponding to each note name C-B in a certain reference octave
Number indicating the number of sample points in one cycle of a musical tone waveform having a wave number
It is. The pitch synchronization signal PS1 is set to 8 channels as shown in FIG.
If you want to occur in the channel time division, the basic
Sampling frequency (in other words, pitch synchronization signal PS1
Resolution) is 1/8 frequency of master clock pulse φ
(For example, 400 kHz), which is common to all note names.
You. On the other hand, the basic sampling frequency is common.
Therefore, the P number of each note name is assigned to the husband corresponding to the note name frequency.
Show different values. Of a certain note name in the standard octave
Let fn be the frequency and use the common sampling frequency (40
0kHz) is fc, the P number corresponding to the note name is
It is decided like. P number = fc / fn (1) Here, the common sampling frequency fc is fc = 400kHz, the sound
Assume that the frequency fn of name A is fn = 440 Hz (that is, A4 sound).
Then, the P number of the note name A is P number of the note name A = 400000 ÷ 440 = 909 from the above formula. On the other hand, the tone waveform that can be generated in the tone generator 18
The number of sample points with different sample point amplitude values per cycle is
Assuming 64, the effective sampling frequency of frequency fn
fe becomes fe = fn × 64 (2), and when fn = 440Hz, fe = 440 × 64 = 28160Hz. Similarly, the P of each note name in a certain reference octave
The number and the effective sampling frequency fe are the P number of each note name
And the effective sampling frequency fe are determined as shown in the table below.
be able to. In this case, the reference octave is F4
One octave up to the # 5 note. In the counter 30 of FIG.
Is the common support established based on the master clock pulse φ.
To divide the sampling frequency fc according to the P number
Is obtained. As is clear from the above, the P number is 1
The number of periods of the common sampling frequency fc in the periodic waveform,
The number of samples, while the tone generator 18
The effective number of sample points per cycle of the tone waveform that can be generated is
As mentioned above, it is 64. Therefore, the common sampling frequency
Assuming that the frequency dividing frequency of fc is frequency dividing number = P number ÷ 64 (3), the frequency dividing output is four parameters per musical tone cycle.
And obtain 64 effective samples.
All pull points can be established. Like this
Divide the common sampling frequency fc by the determined dividing number
Then, from the above equations (1), (2), and (3), fc / frequency division number = (fn x P number) ÷ (P number ÷ 64) = fn x 64 = fe (4) Change the sampling point address according to the frequency output
To establish the effective sampling frequency fe
Can be The effective sump established in this way
The ring frequency fe is in harmony with the pitch frequency fn.
H synchronization is realized. Each char generated from counter 30
Channel pitch sync signal PS1 is assigned to that channel
As shown in the above equation (4),
Output signal, that is, the effective sampling frequency fe.
One signal. By the way, when the frequency division number determined by the above equation (3) becomes an integer,
Is not limited, and often includes decimal numbers. For example, the place of note name A
In this case, the division number is 909 ÷ 64 ≒ 14.20. Therefore, the frequency division operation of the counter 30 will be described later.
And two integers close to the division number determined by equation (3)
Frequency division as appropriate, and the average result is determined by equation (3)
To get the same result as dividing by the divisor
You. In FIG. 4, the P number memory 29 is as shown in Table 1 above.
The P number of each note name in the reference octave as shown
It is stored in advance. Key key assigned to each channel
-Code KC is applied to tone generator 18 via bus 28.
First, the first to the first in the tone generator 18
The key code KC of the 8th channel is the channel of PS1 in Fig. 3.
Time-division multiplexing at the timing shown in the
The key code KC of the 9th to 16th channels is the PS of FIG.
When the timing is as shown in Channel timing 2
Division multiplexing is performed. In this way, time division multiplexed first to first
The key code KC of the 8th channel enters the P number memory 29
Is forced. The P number memory 29 stores the inputted first to eighth channels.
The P number corresponding to the key name of the channel key code KC
Read out in a divided manner. Is the counter 30 a P number memory 29?
Adder 31 for inputting the P number read from
A selector 32 that inputs the output of the arithmetic unit 31 to the “0” input;
8-stage shift register that receives the output of the selector 32
And the lower bits (decimal point) of the output of the shift register 33
Gate 34 which gates the second part) and supplies the other input to the adder 31
And the upper bits (integer part) of the output of the shift register 33
Input all "1" consisting of 7 bits with all bits "1"
And an adder 35 for adding the signal. P number it
The signal itself is a 12-bit binary coded signal.
The output includes one extra bit as a carry signal bit
It consists of a 13-bit signal. Reverse key-on pulse ▲ ▼ and carry of adder 35
The signal output from OUT output CO is input to AND circuit 36
The output of the AND circuit 36 is selected by the selector 32.
Add to selection control input. The output signal of the AND circuit 36 is "0".
Is added from the adder 31 to the "0" input of the selector 32.
Is selected, and when it is “1”, it is given to the “1” input.
Is selected. The “1” input of the selector 32 is
Lower bit (decimal part) of the output of the shift register 33 and the adder
13-bit signal consisting of 35 output 7 bits (integer part)
Is given. The key-on pulse KONP starts when the key is pressed.
This signal is “1” only once,
The corresponding ones are time division multiplexed. Invert key-on
Pulse ▲ ▼ reverses this key-on pulse KONP
Signal. The selector 32, the shift register 33, and the adder 35
Confirm the frequency division number as shown in the above equation (3) according to the P number.
The common sampling frequency according to the integer part of this frequency division number.
This is a circuit for dividing the frequency fc. The adder 31
The value of the integer part is adjusted according to the decimal part of the division number.
It is for In the formula (3), the divisor 64 is 2 ⁶ , The division number
Without doing any special division to find
Only by treating the lower 6 bits of the
A frequency division number corresponding to the frequency can be established. Therefore,
Output signals of the adder 31, the selector 32 and the shift register 33
The lower 6 bits of the 13 bits are the weight of the decimal part.
The seven bits are the weight of the integer part. Adding all “1” signals in the adder 35 is one
Equivalent to subtracting. Therefore, in the adder 35,
Above, subtract 1 from the integer value of the output of the shift register 33.
And do. The subtraction result of this adder 35 was not calculated
"1" input of selector 32 together with 6-bit data of decimal part
Is returned to the adder 35 via the shift register 33.
Is entered. Shift register 33 is the master clock pulse
Since the shift is controlled by φ, the signal of the same channel
Signal is output from the shift register 33 in the master clock cycle.
8 times the clock pulse φ, that is, the common sampling frequency
This is a cycle of several fc. The key to which the key was assigned when the key was first pressed.
Inverted key-on pulse ▲ ▼ is
At the same time, and at this time, the “0” input of the selector 32
The P number of the key is selected via. Of this P number
The integer part is given from the shift register 33 to the adder 35, and the
1 is repeated from the integer part at the cycle of the continuous sampling frequency fc
Is subtracted. When the subtraction result of the integer part is 1 or more,
Carry out continuously from the carry-out output CO of the adder 35
OUT signal “1” is output and the condition of AND circuit 36 is satisfied
Therefore, the selector 32 continues to select the "1" input. Decrease
The output of the adder 35 eventually becomes “0” due to the repetition of the operation.
In other words, the period of fc equal to the number of integer parts of the P number is
When the elapsed time, the carry-out signal of the adder 35 is output.
Therefore, the condition of the AND circuit 36 is not satisfied. At that time,
The selector 32 selects the “0” input, and sets the P number and shift register
Adds the lower 6 bits (decimal part data) of the
Select the output of the calculator 31. Thus, the addition of decimals
Thus, the P number of the changed value is stored in the shift register 33.
Given, this time minus one from the integer value of the changed P number
Is repeated. The gate 34 is an inverted key
Impulse ▲ ▼ can only be used when the key is pressed.
Otherwise, the decimal data is always added to the adder 31.
Give to. Decimal part data for P number in adder 31
The integer value of the frequency division number actually used for the minute by adding the data
Is 1 greater than the integer value of the frequency division number obtained from the P number.
Sometimes. For example, the P number of note name A is 909.
The division number is 14.20, but initially its integer value is 14.
Is divided according to, but the next is 14.20 + 0.20 = 14.40
, The frequency becomes 15.00 and the frequency is divided according to the integer value of 15.
It will be. In this way, the frequency division obtained by the P number
If the integer value of the number is the same or one greater than
The average sampling frequency fc is divided and averaged.
The division operation according to the division number obtained by the P number is
Achieved, the signal at the carry-out output CO of the adder 35 is
It is equivalent to the frequency division output.
The signal inverted in 37 is output as the pitch synchronization signal PS1.
You. For better understanding, the selector 32
4 shows an example of a change in the output of the above. Change timing is common sun
This is the cycle of the pulling frequency fc. At first P number 909
The corresponding divide number is 14.20, then the integer value is decremented by 1.
12.20, 11.20, 10.20, ... 2.20,
1.20 and its integer value decrease by one. 14th cycle of fc
The signal applied to the “1” input of the selector 32 becomes 0.20
When the carry-out signal becomes “0”, the pitch sync signal is output.
The signal PS1 becomes “1” and the selector 32 selects “0” input.
I do. Corresponds to P number 909 for "0" input of selector 32
The division number given by shift register 33 to
The value of 14.40 is added to the numerical value of 0.20. Follow
Thus, 14.40 is output from the selector 32. Then select
The output of data 32 is 13.40, 12.40, 11.40, ... 2.40, 1.40
Next, it decreases by one, and the selector 32
The value added to the “1” input is 0.40, and the adder 32
The carry-out signal of becomes "0" and the pitch synchronization signal PS
1 is generated. At this time, the output of the adder 31 is 14.20 + 0.40
= 14.60, which is through the “0” input of selector 32
To the shift register 33. Thus, note name A
If the frequency is divided by 14 or 15, the common
14 or 15 cycles of pulling frequency fc (eg 400kHz)
The pitch synchronization signal PS1 becomes "1" every time. The pitch corresponding to the other 9th to 16th channels
The period signal PS2 is also generated in the same manner as described above. <Description of Tone Generator> The tone generator 18
Using the pitch synchronization signals PS1 and PS2 of each generated channel
The sampling rate synchronized with the pitch of the musical sound to be generated.
Generating the tone signal according to the imming
Can be. Of course, not limited to this, it is not synchronized with the pitch
Generates tone signal according to sampling timing
It is also possible to do so. Address of sample point of musical tone to be generated (instantaneous phase angle)
Address data to specify the pitch of each channel
Period signals PS1 and PS2 are counted independently for each channel
Can be caused by. However, the same pitch
The period signals PS1 and PS2 are based on the aforementioned reference octave (G4 to F # 5).
The above address data
Is generated in the octave range of the tones
Accordingly, when counting the pitch synchronization signals PS1 and PS2,
It is necessary to switch the count rate. For example, G3 ~ F #
To generate a 4 octave tone,
0.5 is counted each time the signals PS1 and PS2 occur, and G4 to F #
To generate a 5 octave tone, pitch synchronization signal
Each time a signal PS1 or PS2 occurs, 1 is counted, and G5 to F # 6
To generate the octave tone, the pitch sync signal
Every time PS1 and PS2 occur, 2 is counted. Thus,
Changes in sync with the pitch and octave of the musical tone to be generated
Address data to be generated for each channel, and
A digital tone signal is generated based on the dress data. What is the tone signal generation method in the tone generator 18?
The following may be used. For example, the address
Data sampled in the waveform memory according to the data
There is a method to read data sequentially (memory reading method)
Or the above address data is used as phase angle parameter data.
To perform a predetermined frequency modulation operation
Method for obtaining data (FM method) or the above address
Predetermined amplitude modulation using data as phase angle parameter data
A method of performing arithmetic operations to obtain musical tone waveform sample value data
(AM method), or any other known method may be used.
No. When the memory reading method is used,
The tone waveform stored in the memory may be only a one-cycle waveform.
However, a multi-period waveform is preferable because sound quality can be improved.
Good. Store multiple cycle waveforms in waveform memory and read them
For example, as shown in JP-A-52-121313,
All the waveforms from the start to the end of the pronunciation are memorized and read once
Or the method shown in JP-A-58-142396.
Multi-period waveform of attack part and one or more rounds of sustain part
After storing the period waveform and reading the attack waveform once
A method of repeatedly reading the waveform of the sustaining part, or
Discretely sampled as shown in -147793
Stores multiple waveforms and sequentially reads the waveforms to be read
Switching and specifying, and repeatedly reading the specified waveform
Various methods such as a formula are known, and these are appropriately adopted.
May be. <Preliminary explanation of adaptive digital filter> Basically, the operation type of the digital filter is basically as follows.
Finite impulse response (FIR) filter and infinite impulse
There is a response (IIR) filter.
The FIR digital filters 21 and 22 have FIR filters.
Ruta is adopted. First, general related to FIR filters
The explanation is given. (A) Basic circuit configuration of FIR filter FIG. 5 is a basic circuit configuration diagram of the FIR filter.
(N) is the digital tone at any nth sample point
Shape sampled data, the input signal of the FIR filter
It is. z ^-1 Is a unit time delay element, one sample
This is to set the time delay of the logging cycle. Therefore, x
(N-1) is the digital tone at the (n-1) th sample point
Waveform sample value data, where x (n-N + 1) is n-
Digital tone waveform sample at N + 1th sample point
Value data. N is the duration of the impulse response
Corresponds to the order of the FIR filter. h (0) -h
(N-1) is an Nth-order filter coefficient. This filter
The triangular block with the input coefficients is a multiplying element,
Data x (n) of each sample point delayed by the delay element
Filter coefficients corresponding to x (n-N + 1)
Multiply h (0) to h (N-1). Multiplication output is input
The blocks marked with a + sign are addition elements, and each multiplication
The outputs are added and summed to obtain an output signal y (n). The impulse response Δh of such an FIR filter
The z-transform of (n)}, that is, the transfer function is It is expressed as (B) Linear phase characteristic of FIR filter One feature of such an FIR filter is that the phase characteristic is
That is, a linear phase can be obtained. Linear phase
Then, the phase between the input and output waveforms of the filter is completely
And the output waveform is not distorted. Follow
To filter signals such as music, voice, audio, etc.
It is suitable. In a linear phase FIR filter, the phase
The characteristic is required to be θ (ω) = − αω (6) as a function of the angular frequency ω. Where α is called the phase lag
Is a constant. In addition, it has a linear phase characteristic as described above.
The necessary and sufficient conditions for the FIR filter are as shown in the following equation (8).
The impulse response has symmetry, and is expressed by the following equation (7).
The phase delay α depends on the duration (filter order) N.
Is uniquely specified. α = (N−1) / 2 (7) h (n) = h (N−1−n) (8) where 0 ≦ n ≦ N−1 (c) Symmetry of filter coefficient (8) The impulse response has symmetry as in the formula
This means that the filter coefficients h (0) to h (N-1)
It means having symmetry. That is, the filter coefficient
Is set with symmetrical characteristics, the linear phase characteristics
Can be realized. To illustrate an example of the symmetry of the impulse response, the order N
When N is an odd number, it is as shown in FIG. 6, and when N is an even number,
It is as shown in FIG. As is clear from the figure, n = (N
-1) Shows symmetrical characteristics centered at / 2. When N is an odd number
Is the (N-1) / 2 order, and the impulse on both sides
The response is symmetrical. When N is an even number, (N-2) / 2
The center between the next and N / 2 is centered, and the impulse response
The answer is symmetric. Orders at symmetric positions are filter
Since the numbers are the same, all the filter coefficients of order N
There is no need to prepare, only half of it. For details, N is
In the case of an odd number, ｛(N−) from order 0 to (N−1) / 2 order
1) / 2｝ +1 filter coefficients may be prepared,
{(N-1) / 2} filter order from the + 1st to N-1th order
The number is symmetrical from the 0th order to {(N-1) / 2} -1st order
A certain filter coefficient may be used. That is, 0th order and N
The same filter coefficient is used for the -1st order, and the first order and the N-2
Use the same filter coefficients as N is an even number
In the case of, N / 2 number of filters from 0th order to (N-2) / 2nd order
What is necessary is just to prepare the filter coefficient, and from the N / 2 order to the N-1 order
Filter coefficient is symmetrical position from 0th order to (N-2) / 2th order
May be used. (D) Frequency response of linear phase FIR filter Impulse response shows symmetry as shown in Fig. 6 and Fig. 7
Frequency response H of linear phase FIR filter ^* (E ^jω )of
The characteristics are illustrated in FIGS. 8 and 9. N is odd
In the case of a number, ω = π (where π is a sampler) as shown in FIG.
(Corresponding to 1/2 of the ring frequency fs))
It is not fixed to 0 and can be set arbitrarily. If N is even
As shown in FIG. 9, the level when ω = π is always 0.
As is clear from this, when the order N is odd, the filter is
Realizes high-pass filter characteristics by setting the filter coefficient
However, if N is an even number,
It is possible to realize the noise characteristics. But N is even
The number of filters is easier to design, and low-pass filters and
It is suitable for the design of bandpass filters. Therefore, depending on the filter characteristics to be realized,
It is preferable to switch the order of the luta
The adaptive digital filter device of this embodiment
In 21 and 22, such even-odd switching of order N is performed.
It is designed so that you can do it. Ie band
Filter characteristics of pass filter and low pass filter
In order to perform high-pass filtering, set the order N to an even number
To filter the data characteristics, set the order N to an odd number.
Set. (E) Other features of the FIR filter Other features of the FIR filter include feedback.
Because there is no croup, it is characterized by good stability. That is, a feedback loop like an IIR filter.
If there is a problem, the problem such as oscillation will occur, but with the FIR filter
Does not cause problems such as oscillation and is easy to design. Also, when changing the filter characteristics with time
However, FIR filters are advantageous. In this case, usually
The filter function corresponding to each of the different filter characteristics
You have to prepare each pair of numbers,
To reduce the time variation of the filter characteristics, many filter
A set of numbers is required. To solve this problem,
Prepare two sets of filter coefficients that are separated to some extent in time,
By interpolating between the two sets of filter coefficients,
Densely generate a set of filter coefficients with the passage of time,
Thus the filter coefficient generated by interpolation
It is possible to set a filter characteristic that fluctuates between
You. In this way, interpolation of filter coefficients is performed in real time.
To realize time-varying filter characteristics from
As for the one with good stability,
This is very advantageous because it is not necessary to devise the data coefficient. Also, the word length of the signal in the digital filter is finite.
Therefore, the signal data inevitably falls within the limited word length.
Must be rounded. Such rounding becomes noise
However, in the FIR filter, the feedback loop
There is no accumulation of rounding errors
This is advantageous for noise suppression. Regarding the characteristics of the FIR filter as described above
For example, the book "Theory and Application of Digital
Signal Processing "(Book: Lawrence, R. Rabiner; Berna
rd, Gold, Publisher: Prentice-Hall Inc)
Have been. Next, the adaptive digital filter in this embodiment is
For some features of filter devices 21 and 22,
This will be briefly described. (F) How to calculate filter coefficients The filter coefficients are obtained by analyzing actual musical sounds.
Can be An example of the procedure for obtaining the filter coefficient
Explaining with reference to the figure, first, two types showing different tones
Sample sound waveforms (original music sound waveforms) from natural instrument sounds
Prepare by doing For example, Haraku tone 1
The waveform of the piano sound played with a strong key touch.
Sound waveform 2 is the waveform of the piano sound played with a weak key touch
is there. Next, a high-speed Frayer conversion is performed, and the original musical sound waveform 1,
Analysis of 2 free components, based on which both waveforms 1 and 2
Is determined. Next, the waveforms 1 and 2
Calculate the difference in torque characteristics. Next, the spectral properties of the difference are quantified.
The child processing is performed and the filter coefficient is calculated based on this.
U. Finally, the obtained filter coefficient is stored in the memory. The filter coefficient that realizes the time variation of the filter characteristics is
Described in the dynamic control parameter memory 26 (Fig. 2)
Realize a steady filter characteristic that does not change over time
The filter coefficient to be set is set in ADF22 and 22 (Fig. 2).
Data memory. In addition, based on the spectral characteristics of the difference between the two waveforms,
The reason for obtaining the filter coefficient is that the tone generator 18 (No.
Fig. 2 shows one of the original sound waves (for example, a strong key touch is supported)
Tone signal corresponding to the waveform
By applying filtering according to the spectral characteristics of
The other harmonic sound waveform (for example, a wave corresponding to a weak touch)
This is to obtain a musical tone signal corresponding to (shape).
When filtering according to key touch, all keys
Prepare a set of filter coefficients according to the level of touch strength
Side-by-side set of filter coefficients corresponding to several stages
Just prepare and key strength not prepared
The corresponding filter coefficients are determined by interpolation as described above.
You may make it. Of course, not only the filter coefficient corresponding to the key touch,
Pitch (or range) or tone type or other
The filter coefficient corresponding to the factor of
Prepare by. (G) Filter operation synchronized with pitch For each sampling point in ADF21 and ADF22 (Fig. 2)
The calculation timing of is based on the pitch synchronization signals PS1 and PS2
Is set. This means that the unit time
Delay (z in Fig. 5) ^-1 ) Is generated by the pitch synchronization signals PS1 and PS2.
Means to be set. That is, the filter operation
Sampling frequency fs in pitch synchronization PS1, PS2
Therefore, it is set. Specifically, it corresponds to each note name G to F #
The frequencies of the pitch synchronization signals PS1 and PS2 are shown in Table 1 above.
Since it is the same as fe on the effective sampling frequency
Sampling frequency f of filter operation in F21 and F22
s is shown in the table according to the note name of the input tone signal.
Will be different. Sampler in filter operation
The ringing frequency fs is the frequency as shown in FIG. 8 and FIG.
This corresponds to ω = 2π in the response characteristics. Clear from here
In this way, the sampling frequency fs changes according to the note name.
Then, the frequency corresponding to ω = 2π in the frequency response characteristic
The number will change accordingly and the resulting fill
The data characteristic is a moving formant characteristic. Such a move
Formant characteristics are very suitable for tone color control of musical tone signals
Things. On the other hand, the sampling frequency in the filter operation
If the number is constant regardless of the pitch of the input signal, then
The filter characteristics used are fixed formants. (H) Pitch synchronization / asynchronous switching As described above, the moving formant filter produces a musical sound.
It is suitable for color control, but it depends on the timbre or effect to be obtained.
When a fixed formant filter is preferred
There is. Also, operate the pitch vent operator 13 (Fig. 2).
Fixed even if the pitch of the generated sound slides greatly
Formant filters are preferred. for that reason,
In the ADFs 21 and 22 of this embodiment, the filter operation
It is possible to switch between synchronous and asynchronous.
It is like. Also, such pitch synchronous / asynchronous
Switching is not uniform for all channels, but for each channel
It is possible to independently specify pitch synchronization or asynchronous
It has become so. By the way, a fixed formant is used for the pitch vent operator.
The reason why the filter is more preferable is as follows. Pick
Pitch control by the Tivent operator 13
Not only control, but also a large pitch slide
It is also possible to control the pitch, in which case the note names shown in Table 1 above.
Pitch control is applied across the octave boundary of G to F #.
May be done. At that time, the fill synchronized with the pitch
The sampling frequency fs changes suddenly during
And the cutoff frequency also fluctuates rapidly.
(Because it is a moving formant)
Bring. For example, the pitch vent operation
If the tone slides from F # 5 to G5,
Pulling frequency fluctuates rapidly from 47.359kHz to 25.088kHz
(See Table 1 above)
The cut frequency also fluctuates rapidly by the same amount as the difference. This
To prevent such inconveniences, move the mobile phone during pitch vent operation.
Instead of using a Lumant (filter operation synchronized with pitch),
Fixed formant (filter operation asynchronous to pitch)
Good to do. AD for pitch-asynchronous filter operation
Sampling frequency of filter operation in F21 and F22
Is 50 kHz in the example of FIG. (I) Dynamic / static filter
Switching the number As described above, in the dynamic mode,
In real time, under the control of microcomputer 14
Dynamic control parameter memory 26 (Fig. 2)
Read the parameter data for mic control and send it to ADF2
Must be forwarded inside 1,22. Therefore, the
Data transfer time is limited and the filter coefficient has many orders
And filter coefficient parameters of all orders within a limited time
Data may not be transferred. Therefore, Dyna
Filter order in mic mode is real-time data transfer.
Must have a limited order commensurate with the transit time
No. On the other hand, in static mode, filter
Since there is no need to change the coefficient, there is no such problem.
No. Also, the larger the filter order, the finer the filter characteristics
Is preferred because Therefore, the status
The filter order should be large enough in quick mode
Like that. For the above reasons, the specification of this embodiment
Filter depending on whether it is in Mic mode or Static mode
The order is switched. For example, static
In the mode, the filter order is 32nd order (however, this is an even order
If the characteristic is an odd-order characteristic, the order is 31)
The filter order in dynamic mode is half that
It is 16th order (15th order in the case of odd-order characteristics). (J) Weight control of filter coefficient The binary digital data format of one filter coefficient is 12
Bit filter coefficient data part and 3-bit weight
It consists of a data section. The 3-bit weight data part is
6 types of 0, +1, +2, +3, +4, and +5 bits
Of the shift amount of the shift.
The filter coefficient data part is shifted according to the
Weighting is performed. 12-bit filter coefficient data
To perform weight control that can shift up to 5 bits
Therefore, the dynamic range of the filter coefficient is substantially 17
Expanded to a bit. With such weight control,
Memory while securing a sufficient dynamic range
The number of bits of the filter coefficient to be stored is small
It helps to save the capacity of the filter coefficient memory. <Overview of Adaptive Digital Filter> FIG. 11 shows adaptive digital filters corresponding to the first to eighth channels.
The internal configuration example of the digital filter device (ADF) 21 is omitted.
This is the same block diagram as the other ADF22.
Can be configured. The input interface 38 is the tone generator 18 (second
2), and receives the pitch synchronization signal PS1 from each channel.
Pitch synchronization signal PS1 to the ADF21 internal calculation timing
It is shaped into an adapted state.
Shown in Figure 12. The timing signal generation circuit 39 controls various operations inside the ADF 21.
Generates a timing signal to control the
Pitch of each channel given from interface 38
Necessary for filter operation based on the signal corresponding to the synchronization signal.
It generates various necessary operation timing signals,
The details are shown in FIG. As described below,
Since the channel filter operation is performed in a time-sharing manner,
The timing signal generation circuit 39 provides appropriate timing
Timing signal for filter operation control of each channel
No. is given. State memories 40, 42 and multipliers and accumulators
The units 41 and 43 perform data processing for executing filter operation of the FIR filter.
It is a digital filter circuit. Multiply with state memory 40
Digital filter consisting of a compensator and accumulator unit 41
Circuit (this is called A-series digital filter circuit)
Is the filter operation for the first to fourth channels (Ch1 to Ch4)
The state memory 42, the multiplier and the accumulator
A digital filter circuit composed of the
Column digital filter circuits) are the fifth to eighth channels.
Performs channel (Ch5 to Ch8) filter operation.
You. In the digital filter circuit of each series A and B, 4
Filter calculations for channels are now performed in a time-sharing manner.
ing. Two filter operations for the first to eighth channels
The reason for dividing into columns A and B is as follows.
It depends. State memories 40 and 42 are tone generators
Digital tone signal sump given from 18 (Fig. 2)
Captures the value data TDX in synchronization with the pitch synchronization signal PS1,
The pitch synchronization signal is output by the number of stages corresponding to a predetermined filter order.
Signal PS1 at the timing corresponding to
The unit delay element z in the basic circuit of the FIR filter in FIG. ^-1 of
Corresponds to the set. Multiplier and accumulator unit 41, 43
Is the digital tone delayed by the state memories 40 and 42
Corresponds to the delay order for signal sample value data
Multiply the filter coefficients of the order and accumulate the result of multiplication of each order
This is the sum of the values.
Corresponding to the multiplication element and the addition element. A series of stations
Group example of the port memory 40, the multiplier and the accumulator unit 41
Is shown in FIG. 14, and the B-series
Can be configured. The microcomputer interface 44 is the microcomputer 14
Via the data and address bus 28 under the control of FIG.
Various data given by ADF21
Is to be supplied to Via this interface 44
The types of data that can be accepted are as follows. Key code KC: indicates a key assigned to each channel. Key-on pulse KONP: Key on pulse assigned to each channel
The signal becomes "1" only once at the start of pressing. Touch code TCH: Press key assigned to each channel
Indicates the strength of the touch at the time. Voice code VN: For the key assigned to each channel
Indicates the selected tone color (voice). The above KC, KONP, TCH, and VN are predetermined time division timings.
Time division multiplexed for each channel according to
Output from the interface 44 and the parameter processing
Unit (sometimes called PPU) 45
You. Pitch synchronous / asynchronous designation signal PASY: Data in this ADF21
Digital filter is executed synchronously or asynchronously.
This signal is used to specify whether This signal PASY is also
Can be provided in a time-sharing manner for each
Pitch synchronous / asynchronous control of filter operation for each channel
Can be done independently. This signal PASY is selected
Tone type or pitch vent operator 13 (Fig. 2)
Operation details, or operation status of dedicated or appropriate controls
Generated according to the status, etc., and
Given to S.44. Output from interface 44
Pitch synchronous / asynchronous designation signal PASY is an input interface
Generated according to pitch sync signal / PS1 given to 38
Control whether the input interface 38 should perform
Used to do. Dynamic filter parameter DPR: Microcomputer
Parameter control for dynamic control under the control of computer 14.
Filter parameters read from memory 26 (Fig. 2)
(Filter coefficient). As mentioned earlier, this dynamic
Mode filter parameter DPR content is sounding
It changes over time. This dynamic mode
The data format of the filter parameter DPR is
Bit filter coefficient data and 3-bit weighted data
Data that further identifies order odd / odd.
including. Also, as described above, this dynamic mode
The order of the filter parameter DPR is 16th (or 15th).
Next). Furthermore, as is clear from the above, the linear phase
Actual preparation due to the symmetry of the filter coefficients in the characteristics
Set of dynamic mode filter parameters DP
R only needs 8th order. Dynamic / static selection signal DS: Dynamic
/ According to the operation of the static selection switch 27 (Fig. 2)
Generated by the above-mentioned dyna
Quick mode or static mode
Show. The above DPR and DS are sent to the interface
Given to Kuta 46. Parameter memory 47 is for static mode
It stores the filter parameters (filter coefficients)
is there. The parameter processing unit 45
Filter parameters for static mode from
Functions to read data. That is, the key-on pulse
When KONP is given, tone code VN, touch code TC
H, the parameters to be read based on the contents of the key code KC
Calculates the address of the data memory 47 and stores it in this address.
The read filter parameters are read from the memory 47.
You. The readout static mode filter parameters
The data SPR is provided to the parameter selector 46. This
Data type of filter parameter SPR for antistatic mode
The formula is also similar to the DPR described above. Also, as mentioned above,
A set of orders for the filter parameter SPR for the tick mode
Is the 32nd order (or 31st order). Moreover, it's clear from the above
As described above, due to the symmetry of the filter coefficient in the linear phase characteristic,
A set of static mode filters
The parameter SPR need only be for the 16th order. The parameter selector 46 is a dynamic / static
For dynamic mode or according to the contents of the
Filter parameters for static mode DPR, SPR
Select one. The selected parameters are the parameters of A-series and B-series.
Input to the data supply circuits 48 and 49. Parameter supply of A series
In the supply circuit 48, the filter parameters of the first to fourth channels are
Accept DPR or SPR, store it, and filter
In synchronization with the timing, the state memory 40 and the multiplier and
It is supplied to the accumulator unit 41. Parameter B
In the supply circuit 49, the filter parameters of the fifth to eighth channels are set.
Do the same for data. Filter parameter SPR for static mode is
The key is read from the parameter memory 47 once at the beginning.
After that, it is stored in the parameter supply circuits 48 and 49. Obedience
Therefore, in static mode, during the sounding period
The filter coefficient does not change and a constant filter characteristic is maintained.
On the other hand, the filter parameter DPR for the dynamic mode
Is the new parameter of the microcomputer interface
In the parameter supply circuits 48, 49 until given through 44
It is stored, and the stored contents are the contents of the parameter DPR
It is rewritten every time it changes. Filters output from parameter supply circuits 48 and 49
Even / odd identification data EO that identifies even-odd of order
A1 to EOA4 and EOB1 to EOB4 are given to the state memories 40 and 42.
The filter coefficient data parts COEA, COEB and weighting data
WEIA and WEIB are multipliers and accumulators 41 and 43
Given to. In addition, in the code in the figure, the suffix A or
B represents the distinction between the A series and the B series. Data EOA1 to EOA
4, EOB1 to EOB4 are given in parallel for each channel.
Data COEA, COEB, WEIA, WEIB
Are given in a time-sharing manner. Parameter processing unit 45, parameter selection
, A parameter memory 47, a parameter supply circuit 48,
A detailed example of 49 is shown in FIG. The pitch synchronization output circuit 50 includes a multiplier and an accumulator.
Filtered for each channel output from sections 41 and 43
Input the tone signal sample value data, and
Circuit that resamples at the timing synchronized with the switch
is there. Here, the signal used for sampling control is
Interface 38. Pitch sync signal PS1D
Yes, this specifies the pitch synchronization signal PS1 for each channel.
It is a time delay. Resampler in sync with the pitch
Of using the delayed pitch synchronization signal PS1D for
The reason is that each channel in the digital filter operation in the previous stage is
This is for adjusting to the time delay of the tone signal of the channel. This
The pitch of the digital filter output signal is
The process of resampling in anticipation
Harmony with the musical tone pitch, so
Resolve. Digital filter calculation synchronized with pitch
If so, the digital filter output signal is equal to the pitch.
Pitch synchronous output circuit
Pitch synchronization can be achieved even if 50 is not provided.
Digital filter operation asynchronous to pitch.
In order to achieve pitch synchronization when performing
The output circuit 5 is required. Details of pitch synchronization output circuit 50
A specific example is shown in FIG. Next, each part of the adaptive digital filter device 21
A detailed example will be described. In each figure, “1D”, “8D”, etc.
Circuits with numbers and the letter D are delay circuits or serial circuits.
It is a shift register and the previous number is the delay stage or stage.
Indicates the number of pages. Also, this delay circuit or shift register
Delay control clock pulse or shift in block
It is not shown that the control clock pulse is input.
In this case, the master clock pulse φ (see FIG. 3)
Therefore, delay or shift control is performed. <Input interface 38: FIG. 12> In FIG. 12, the pitch synchronization signal PS1 is OR circuits 51 and 5.
The data is input to the shift register 53 through the line 2. Shown in FIG.
This pitch sync signal PS1 has 8 time slots
Eight channels are time-division multiplexed as one cycle
Sync with the pitch of the key assigned to a channel
1 time slot corresponding to the channel in the cycle
A signal "1" is generated at. The output of the shift register 53 is AND
Returned to the input side via the circuit 54 and the OR circuit 52,
8 stage shift register PS1
It is circulated and held in the star 53. 8 corresponding to each channel
Latch circuits 55 are provided in parallel,
The pitch synchronization signal output from the
Force D is input in parallel. Latch system for each latch circuit 55
Latch timing corresponding to each channel for input L
Signals φFS1 (25), φFS2 (29),… φFS8 (56) respectively
Input is gone. The number next to φFS is the channel number
And the number in parentheses next to it indicates one operation cycle (the
Time slot number in 64 time slots shown in Fig. 3)
Indicates the time slot number corresponding to that time slot number.
The latch timing signal becomes signal "1"
You. For example, the signal φFS1 (25) is transmitted in time slot 25.
The number "1" corresponds to the first channel.
As can be seen in FIG. 3, time slot 25
The time-sharing switch of the first channel in the pitch synchronization signal PS1
It supports imming. Therefore, this signal φFS1 (2
5) The part of the latch circuit 55 that is latch controlled by
Contents of pitch synchronization signal PS1 of channel 1 (same as pitch
The expected timing is signal "1", other timing
In this case, the signal “0”) is latched. Other channels 2-8
Similarly, the pitch synchronization signal of each channel is
It is latched in parallel by the latch circuit 55 at the timing.
You. The latch timing signal corresponding to each channel
φFS1 (25) to φFS8 (56) are from the decoder 56 shown in FIG.
Generated. Decoder 56 decodes the output of counter 57
To generate various types of timing signals. counter
57 is a modulo 64 that counts the master clock pulse φ
And the system sync pulse SYNC (third
It is reset periodically by (Fig.). Each channel 1
~ 8 latch timing signal φFS1 (25) to φF
Which time slot S8 (56) occurs is shown in Fig. 13.
It will be clear from the display. Returning to FIG. 12, each timing signal φFS1 (25) to φFS8
(56) is multiplexed and inverted by NOR circuit 58. Noah
The output of the circuit 58 is input to the AND circuit 54. This
To the channel that was captured by the latch circuit 55.
The memory of the related shift register 53 is cleared. On the other hand, the channel for which the pitch synchronization signal PS1 becomes "1"
The signal “1” latched by the latch circuit 55 corresponding to
Latch timing signal φFS corresponding to the cycle
It is held until 1 (25) to φFS8 (56) occur. like this
Then, the pitch synchronizing signal PS1 becomes “1” in the latch circuit 55.
Time corresponding to 64 time slots corresponding to the channel
Only the signal "1" is held. The channel corresponding to each channel
The output of the switch circuit 55 is a filter operation request signal φF1 to φF8.
Then, it is given to the timing signal generating circuit 39 in FIG.
As will be described later, this filter calculation request signal φF1 to φF8
When “1” is set, the filter operation for one sample point is executed.
Is performed. Only when the pitch sync signal PS1 is generated
Since the filter operation request signals φF1 to F8 become “1”,
Digit synchronized with the pitch of the tone signal to be filtered
The filter calculation will be performed. For example, as shown in FIG.
If the pitch synchronization signal PS1 becomes “1”
In this case, this signal “1” is the pitch synchronization signal of channel 1.
This is cyclically held by the shift register 53, and the time
When the timing signal φFS1 (25) occurs in slot 25
Latch circuit 55, corresponding to channel 1.
The filter operation request signal φF1 is
And rises to “1”. This signal φF1 is
Up to 24 time slots for a total of 64 time slots
Keep signal “1”. <Timing signal generating circuit 39: FIG. 13> In FIG.
The input interface shown in FIG.
Filter calculation required for each channel given from
A tie for controlling filter operation depending on the request signals φF1 to F8.
Operation timing generation circuits 391 to 398 for generating a timing signal
Is provided for each channel (Ch1 to Ch8). In the figure
Although only the circuit 39 of channel 1 is shown in detail, other channels are not shown.
The circuits 392 to 398 of the modules 2 to 8 have the same configuration, and input
Relation of time signals T (33), T (49), ...
Only differ. The timing signals T (33), T (49),.
Generated from decoder 56. As before, timing
In the code indicating the signal, the number in parentheses is one operation
Time slot in the kuru (64 time slots shown in Fig. 3)
Indicates the slot number and the time corresponding to the time slot number.
The timing signal becomes “1” in the time slot.
And Other timing signals generated by decoder 56
The same applies to numbers, and refer to the numbers in parentheses.
The timing signal is assigned to which time slot.
It is easy to see if the error occurs (whether it becomes "1"). example
For example, timing signal T (33) is
Signal "1" in the memory slot 33.
T (3-18) is a signal from time slot 3 to 18
It becomes "1". Channel 1 computation timing signal generation circuit 391
To explain, the filter operation request signal φF1 and the timing
The signal T (33) is supplied to the AND circuit 59. Therefore,
If it is required to perform a filter operation,
The output of the AND circuit 59 is output at the timing of time slot 33.
It becomes “1”. The output signal of this AND circuit 59 and this signal
Is delayed by one time slot in the delay circuit 60.
Given to circuit 61. The output of this OR circuit 61 is a filter
Digital as data sampling clock signal RLA1
Used to control the unit delay in the filter circuit
It is. This signal RLA1 is time-slotted as shown in FIG.
It becomes "1" at the time of the points 33 and 34. The output of the AND circuit 59 and the channel 1 are included in the AND circuit 62.
Even / odd identification data EOA1 (this is the parameter
Is output from the circuit 48) by the inverter 63.
The inverted signal is given. Let's realize this data EOA1
When the order of the filter characteristics is even, the signal is “1”.
The signal is "0" at the odd order. Output of AND circuit 62
The force is delayed by two time slots in the delay circuit 64, and the
Output as the input signal INHA1. Odd filter order
The output signal of the AND circuit 62 is
"1", the time slot after 2 time slots
At the time of 35, INHA1 becomes "1" (see FIG. 17). filter
If the order is even, the signal INHA1 is always "0". this
The in-bit signal INHA1 is a digital filter circuit
In arithmetic operation, the operation of the highest order of the even order (32nd order) is prohibited
To realize odd-order filter characteristics
used. Timing signals T (3-18) and T (35-50) are OR times
The output of the AND circuit 59 is input to the
Are input to the OR circuit 66. The output of the OR circuit 66 is slow
Delayed by one time slot in the extension circuit 67, the first shift clock
The clock signal φFFA1 is output (see FIG. 17). Ma
The output of the OR circuit 66 and the output of the delay circuit 64 are
The signal inverted at 68 is added to the AND circuit 69.
The signal whose output is delayed by one time slot by the delay circuit 70 is
Output as 2 shift clock signal φFLA1 (Fig. 17
reference). The signal φFLA1 is a tie signal if the filter order is even.
It is “1” at the time of slot 36, but is “0” if it is odd.
You. These shift clock signals φFFA1 and φFLA1 are
When calculating operation for each order in the digital filter circuit
In order to perform divisionally, in the state memory 40 (Fig. 11)
Sample the tone signal sample value data corresponding to each delay stage
Used to shift. Time slot according to the timing signal T (35-50)
Multiplication timing signal PDOA1 that becomes “1” between 35 and 50
(Refer to Fig. 17) is easy for digital filter circuits.
Multiplies sound signal sample value data by filter coefficients
It dictates the time period that should be used. Operation corresponding to other channels 2 to 4 in A sequence
The timer used in the timing signal generation circuits 392 to 294
The timing signals T (49), T (19−34), T (51-2),.
Channel 1 timing signals T (33), T (3-18), T
16 time slots in order from the timing of (35-50)
It is out of alignment. Therefore, the circuit 391 of channel 1
Signals RLA2 to PDO similar to the signals RLA1 to PDOA1 output from
A2, ... RLA4 ~ PDOA4 is the circuit 392 ~ 3 of other channels 2 ~ 4
Timing shifted by 16 time slots from 94 each
Generated by Based on this,
In the filter circuit (especially the multiplier and accumulator unit 41)
1 operation cycle = 16 times during 64 time slots
Four channels 1 to 4
To be able to perform filter operation in a time-sharing manner
Has become. Operation timing corresponding to each channel 5 to 8 of B series
16 between each channel also in the
Timing at a predetermined timing shifted by time slot
Signal T (49), T (19−34), T (51-2),.
RLB1 to PDOB1,... RLB4 to PDOB4
Is generated. Operation timing signal generation circuits 391 to 3 corresponding to A series
The signals RLA1 to PDOA4 generated in 94 are the states of the A series.
Circuits 395 to 398 provided to the memory 40 and corresponding to the B series
The generated signals RLB1 to PDOB4 are B-state memos.
It is given to Li 42 (Fig. 11). <State memory 40: FIG. 14> In FIG.
State memories 401-4 corresponding to the respective channels 1-4
It is equipped with 04 in parallel. Channel 1 state memo
Only the details of the channel 401 are shown.
Tate memories 402 to 404 have the same configuration, and input
The signals are different. For each of the above channels 1 to 4
The corresponding operation timing signal generation circuits 391 to 394 (the thirteenth
Signals generated from RLA1 to PDOA1, ... RLA4 to PDOA4
Are the state memories 401 to 4 corresponding to the own channel.
Entered in 04 respectively. State memory 40, multiplier and accumulator shown in FIG.
Before describing the details of the oscillator section 41,
Figure 18 shows the basic operation of a digital filter circuit.
And the schematic diagram shown in FIG. <Basic operation of even-order filter operation: FIG. 18> FIG.
FIR for realizing filter characteristics consisting of the following (32th order)
5 is a schematic diagram for explaining a basic operation of a type filter operation.
(A) is a block diagram, and (b) is at each operation timing.
(A) each stage Q0 of the shift registers SR1 and SR2
This shows the state of the tone signal sample values in Q15, Q16-Q31. The first shift register SR1 has 16 stages,
Digital tone signal sample value data to be filtered
x _n Is input via the selector SEL1. Selector SEL1
Via new sample value data x _n Signal for capturing
The filter data sampling clock signal
No. RLA (RLA1 for channel 1) is used and shift
The shift clock pulse of the register SR1 is
First shift clock signal φFFA (for channel 1
φFFA1) is used. Each of the first shift registers SR1
16 stages from sample points n to n-15 on stages Q0 to Q15
Sample data x _n ~ X _n-15 Is held. This
The output of the final stage of the shift register SR1 is the selector SEL1.
When there is no sampling clock signal RLA via
Returned to the stage. This shift register SR1 moves to the right
Only shifted. The second shift register SR2 also has 16 stages,
The output of the shift register SR1 is input via the selector SEL2.
Is forced. SR1 output is taken to SR2 via selector SEL2.
The filter data sampler
Shift clock of the SR2 using the clock clock signal RLA.
As the pulse, the second shift clock signal φFLA
(ΦFLA1 for channel 1) is used. This second
Each stage Q16 to Q31 of the second shift register SR2 has a sun
16 sample value data x from pull point n to n-31
_n-16 ~ X _n-31 Is held. The final status of the shift register SR2
Tage Q31 is sampling clocked via selector SEL2.
When there is no clock signal RLA, it is connected to the first stage Q16. This
Shift register SR2 is a bidirectional shift type
Right shift mode when the ring clock signal RLA is “1”,
When it is “0”, it is in left shift mode. The outputs of shift register SR1 and SR2 stages Q15 and Q16
It is added by the adder ADD and the addition result is given to the multiplier MUL.
And multiplied by the filter coefficient COEA. The result of the multiplication is
The multiplication result for all orders given to the accumulator ACC.
The fruits are accumulated there. Thus, accumulate
The filter operation result for one sample point is output from the ACC
Is output. Adds sample value data for two sample points with adder ADD.
And multiply it by the common filter coefficient COEA with the multiplier MUL.
The reason for the calculation is based on the above-mentioned “symmetry of filter coefficient”.
You. That is, two sample value data in a symmetric relationship
Are multiplied by the same value of filter coefficient,
Instead of multiplying separately, add and then multiply by one
By multiplying the sample value data by coefficient at the same time
I have. In FIG. 18 (b), the vertical axis calculation timing is
Progress every time slot according to master clock
You. The numbers shown there indicate the order of convenience,
Time slot number in arithmetic cycle (64 time slots)
It does not indicate the number. In the example shown, the calculation type
Each stage of shift registers SR1 and SR2 when ming 1
X from Q2 to q31 _n To x _n-31 Up to 32 sample points
Contains data. In the example shown in FIG.
The lock signal RLA is supposed to be "1". This
Shift shift signal according to the shift clock signals φFFA and φFLA.
The transistors SR1 and SR2 are shifted to the right by one stage.
The state shown in FIG. At this time
In the case of channel 1, the soft clock signals φFFA and φFFA are
As shown in the columns of φFFA1 and φFLA1 in Fig. 17, the time slot
Occurs at the point 34. As is clear from the figure,
The next one time slot is shift clock signal φFFA, φF
LA does not occur, so the calculation timing 3 in Fig. 18 (b)
Then, the state of each stage Q0 to Q31 does not change. But,
The 16 time slot widths from operation timing 3 to 18 are:
Speaking of channel 1, multiplication timing signal PDOA1 (17th
It corresponds to the time slot 35 to 50)
Multiplication and accumulation are performed during this time. That is, at operation timing 3, the stages Q15 and Q16
X in _n-14 And x _n-15 Sample value data is the adder AD
D is added and this is multiplied by the 16th order filter coefficient
The result is stored in the accumulator ACC. Between operation timings 4 and 18, one time slot
The first shift register SR1 shifts right,
The shift register SR2 is shifted to the left, and each stage Q0 to Q31
Changes sequentially as shown. Therefore, the operation type
X in mining 4 _n-13 And x _n-16 Is added to the 15th order
The filter coefficients are multiplied and the result is accumulator AC
Classified as C. At the next operation timing 5, x _n-12 And x
_n-17 A similar operation is performed for the asymmetric position
Filter coefficients for the two sample value data in
Calculations are performed sequentially in a time-sharing manner.
X at the symmetric position of _{n + 1} And x _n-30 A similar operation is performed for
This completes the filter operation of all orders. Next performance
At calculation timing 19, the shift is performed once again, as shown in the figure.
As shown in Fig.
Pull value data x _{n + 1} ~ X _n-30 Are lined up. <Odd-order filter operation basic operation: Fig. 19> Fig. 19 shows the filter characteristics of odd-order (31st-order).
Explain the basic operation of FIR type filter operation when it appears
Is a block diagram, (a) is a block diagram, (b) is each performance
(A) shift registers SR1 and SR2 at the calculation timing
Of the tone signal sample values of each stage Q0-Q15, Q16-Q30
Indicates the status. Each block in (a) is shown in Fig. 18 (a).
The difference is that the output of stage Q16 is
Is provided to the adder ADD via the gate GT. Get
The GT is an inhibit signal INHA (IN channel 1
HA1) became controlled by the inverted signal
And when the signal INHA is “1”, the output signal of the stage Q16
Is not provided to the adder ADD. Also, the second
The 16th stage Q31 of the shift register SR2 of
15 stage Q30 and first stage Q16 via selector SEL2
Connected. In (b), the state change of the first shift register SR1
Is the same as FIG. 18 (b). Second shift register SR2
Are slightly different from those in FIG. 18 (for the even-numbered order).
Shift clock signal φFLA of second shift register SR2
Is "1" in the even-order mode at the operation timing 4.
However, it is “0” in the odd-order mode (channel 1
In this case, refer to the time slot 36 in the column of φFLA1 in FIG. 17). Obedience
Therefore, in the odd-order mode, as shown in FIG.
The content of the second shift register SR2 is calculated at operation timing 4
Is not shifted, and it is sequentially between operation timings 5 to 19.
Left shifted. At the operation timing 3, each of the shift registers SR1 and SR2
Stages Q0 to Q30 have musical tones corresponding to the 31st delay stages
Signal sample value x _{n + 1} ~ X _n-29 Are in order,
Sample value x of center order in page Q15 _n-14 Contains.
As shown in FIG. 6, in the symmetry of the odd-order mode
In the central position, the unique fill
Data coefficients are assigned. Therefore, at operation timing 3,
Is the output of stage Q16 by the inhibit signal INHA
And the output signal of stage Q15 corresponding to the central order
Add only to the adder ADD and in the multiplier MUL
Is multiplied by a unique filter coefficient corresponding to. At operation timing 4, the first shift register SR1
Is shifted right, and the second shift register SR2 is shifted
Not done. Therefore, stage Q15 has x _n-13 Entered, Q16
X _n-15 Contains. In addition, the inhibit signal INHA
Becomes "0" and the gate GT is opened. Thus, the central next
Sample value x corresponding to the order on both sides of the number _n-13 , x _n-15 Add
The data are added to the adder ADD and added.
Are multiplied by a common filter coefficient. At operation timings 5 to 18, SR1 shifts sequentially to the right and SR2 shifts
The sump is shifted left sequentially, and is symmetrical as shown
Values enter stages Q15 and Q16, and both are added and shared
Are calculated. <Digital filter circuit: FIG. 14> Referring to FIG.
The moly 401 will be described. About 16-state memory 401
Will be explained. The 16-stage unidirectional shift register 71
Corresponding to the first shift register SR1 in Fig. 18 and Fig. 19.
And the first shift clock corresponding to channel 1
The shift is controlled by the lock signal FFA1. Tornjeere
Digital sound signal signal supplied from the data 18 (Fig. 2)
Sample value data TDX or latch circuit 73
According to the timing signal XLDA1.
The value data is taken into the latch circuit 73. Music signal
Time division tie of each channel in sample value data TDX
1 to 8 for each channel (see FIG. 3).
Latch timing XLDA1 to XLDA4, XLDB1 to XLDB corresponding to
4 is generated from decoder 56 (FIG. 13). I mentioned earlier
The numbers in parentheses at the end of each signal display in Fig. 13 are
Indicates the time slot number in which the signal of. Each Chan
In the state memory corresponding to the
Latch circuits are provided.
The timing signals XLDA1 to XLDA4 and XLDB1 to XLDB4.
The tone signal sample value data TDX of each channel 1-8 is
Latched separately and thus demultiplexed. Tone signal of channel 1 latched by latch circuit 73
Sample value data is given to A input of selector 74
You. The selector 74 is the operation timing signal generation circuit shown in FIG.
Filter data sampling clock provided from 391
A input is selected when the lock signal RLA1 is "1",
The 16th stage of shift register 71 added to the B input
Select the output signal. As described above, this signal RLA1 is a musical tone
The pitch is synchronized with the pitch of the
Select new sample value data (A input) with
This is given to the shift register 71. It is clear from FIG.
Thus, in the time slot 34 where the signal RLA1 becomes “1”,
Since the shift clock signal φFFA1 is “1”, the shift register
Star 71 is the new sample value data provided by selector 74.
Data to the first stage (Q0). Next time slot
At time 35, the shift operation is paused and the following time slot
The right shift from 36 to 51 is performed as described above. The bidirectional shift register 72 is the second shift register shown in FIGS.
It corresponds to the shift register SR2. This bidirectional system
Each stage Q16-Q31 of the shift register 72 is set as shown.
Lectors SL to SL16 and latch circuits LC1 to LC16
And are connected so that bidirectional shift is possible. sand
That is, the A input of the selector SL1 of the first stage Q16 is
Output signal of the last stage (Q15) of 1 shift register 71
Signal is input to the selector SL2 of each of the other stages Q17 to Q31.
To the A input of SL16, the latch circuit LC1 of the previous stage
~ The output of LC15 is input. Also, the selector for each stage
The B inputs of SL1 to SL16 have latch circuits LC2 to LC2 of the next stage.
The outputs of LC16 and LC1 are input. This allows each selector
When the A input of SL1 to SL16 is selected,
When the B input is selected, a left shift mode is set.
The sampling clock is used as a selection signal for each of the selectors SL1 to SL16.
Lock signal RLA1 is used, and when this signal is "1", A input selection
That is, the right shift mode is selected. However, odd mode
To disable stage Q31 when stage Q30
Selector SL15 is somewhat different from the others. In other words, this
The selector SL15 has a C input,
The output signal of the stage Q16 is added. Regarding channel 1
When the even-odd identification data EOA1 is “1” (that is, even-order mode)
When the signal RLA1 is “0”, the AND circuit 751 is enabled.
The output of the AND circuit 751 becomes the signal "1", which causes the security
Lector SL15 selects the B input and the output of stage Q31 is switched
Provided to tage Q30 (shifted left). EOA1 is
When "1" (in odd-order mode), AND circuit 761 is enabled
When the signal RLA1 is "0", the selector SL15
And the output of stage Q16 is given to stage Q30.
(Shift left over Q31). With the above configuration, the first and second shift registers 7
The change state of the contents of 1,72 is between the even-order mode and the odd-order mode.
According to FIG. 18 (b) and FIG. 19 (b),
It will be exactly the same. The output signal of the first stage Q16 of the second shift register 72
The signal is provided to gate 76 via gate 75. Gate 75
Controlled by a signal that is the inverse of the inhibit signal INHA1
Which corresponds to the gate GT in FIG.
You. The gate 76 outputs the output signal of the first shift register 71.
(Output signal of stage Q15) and given through gate 75
Output signal of the second shift register 72 which is
Opened by calculation timing signal PDOA1 (see Figure 17)
It is. The output of gate 76 is applied to the multiplier and accumulator 41.
It is given to the calculator 77, where two tone signal sample values de
Data is added. This adder 77 is added to FIGS. 18 and 19.
This corresponds to the arithmetic unit ADD. Output of adder 77 is delayed
It is time slot delayed in circuit 78 and input to multiplier 79.
You. Multiplier 79 is a tone signal given via delay circuit 78
A filter applied to the sampled value data via the delay circuit 80
It is for multiplying the filter coefficient data COEA. Multiplier 79
The output is delayed by the delay circuit 8 for 48 time slots and then shifted.
Given to 82. 5 ties for shift control input of shifter 82
A delay circuit 83 that sets the delay of the
Receiving data WEIA. This multiplier 79 and shifter 82
Corresponds to the multiplier MUL in FIGS. 18 and 19.
You. That is, as described above, the filter coefficient data COEA is
This is the effective bit data of the filter coefficient, and
The effective bit of this filter coefficient and the tone signal sample
Multiplication with the default value data is performed. And this multiplication result
In shifter 82 according to the value of weighting data WEIA.
Real number of filter coefficients by shifting
And the tone signal sample value data are multiplied. The output of shifter 82 is applied to accumulator 84 and
The multiplication result corresponding to each order of the channel is accumulated
Is The output of accumulator 84 enters latch circuit 85.
Latched according to the computation end timing signal FENDA
Is done. This signal FEND is generated by the decoder 56 in FIG.
It is. As shown in the figure, this signal FENDA
Becomes "1" in the time slots 8, 24, 40 and 56. Thailand
In slot 56, the calculation result of channel 1 is latched,
8 latches the calculation result of channel 2, and 24 latches the result.
The operation result of channel 3 is latched.
Latch the operation result. B-series operation from decoder 56
The end timing signal FENDA is also generated at the same time. The multiplier and accumulation unit 41 has four channels
Is shared by time sharing. That is, the adder 77
Channel 1 state memory 401 gate 76 output
Not only the state memories 402-404 of channels 2-4
Output signal of a gate with similar function provided in
Are multiplexed. Output of each state memory 401-404
Force gate 76 has 16 timeslot width multiplication timing
Signals PDOA1 to PDOA4 differ by 16 time slots
Each is input at the timing. Therefore, each adder 77
Channels 1-4 signals are time-divided every 16 time slots
Multiple inputs. Filter coefficient data COEA and weight
WEIA data for 4 channels are the same as above.
It is time-division multiplexed every 16 time slots at the same timing.
To 16 time slots per channel
In this case, the data from 1st to 16th is time-division multiplexed.
ing. B-series state memory 42, multiplier and accumulator
The control section 43 has the same configuration as that of FIG.
The timing is appropriately different. Digit of A-sequence and B-sequence as shown in FIG.
Filter circuit (ie multiplication with state memories 40, 42)
Channels in the instrument and accumulator 41,43)
FIG. 20 shows the timing of the filter operation for 1 to 8.
You. In Fig. 20, the column of shift 1 indicates the first shift record.
Shift timing of the register (71 for channel 1)
The second shift register (cha
In the case of channel 1, the shift timing of 72) is shown.
You. The direction of the arrow is the shift direction (right shift or left shift)
Is shown. Calculation of shift timing of each channel
Generated from timing signal generation circuits 391 to 398 (Fig. 13).
First and second shift clock signals φFFA1 to φFFB
4. It corresponds to the generation timing of φFLA1 to FLB4. Shi
Shift operation and shift operation for filter operation and memory
There is a dummy shift operation for data refresh.
You. For example, in the case of channel 1, time slots 4 to 19
Is a dummy shift. In shift 2
The left (←) symbol shifts left in the even-order mode,
Indicates that no shift is performed in odd mode. In FIG. 20, the column of INH shows the inhibit signals INHA1 to INHA1.
The timing of INHB4 generation is shown. Odd mode
In some cases, the inhibit signal is used in the time slot marked with a circle.
INHA1 to INHB4 become “1”. The PDO column is for each channel
State memory 40, 42 from multiplier and accumulator
The tone signal sample value data is input to the parts 41 and 43.
Ming. This is the multiplication timing for each channel
Corresponding to the timing of the generation signals PDOA1 to PDOB4.
You. The SUM column shows the output timing of the accumulator 84.
doing. 6 time slots between PDO and SUM timing
There is a delay of 5 times due to delay circuits 78 and 81.
Lot delay and 1 time slot due to accumulation 84
Due to the delay of Accumulator 84 output timing
In the last time slot, calculation end timing signal FEND
A is generated and the output of the accumulator 84 is sent to the latch circuit 85.
take in. <Parameter memory 47: FIG. 21> FIG. 21 shows an example of the storage format of the parameter memory 47.
Examples are shown, key group table, touch group
Table, parameter address table and parameters
Made up of banks. The actual filter parameters are
Parameter address stored in parameter bank
The table shows the parameters to be read from the parameter bank.
Data address data is stored. Key group
The table is the information that groups each key for each key
I remember. As an example, 88 keys and 44 groups
And the key group table
Address relative to the key group to which the key belongs.
Stores dress data (called key group address)
ing. Therefore, the key group table
Addressed by De KC. This key group table
Is stored at a predetermined absolute address (offset) in the parameter memory 47.
Address OADS)
ing. The touch group table shows the key touch intensity for each tone.
Information that groups the touch intensity for each stage
I remember. As an example, the number of tones is 32.
Switch group table supports tone code VN values 0 to 31
Includes 32 tone-specific areas and touch code
The steps of touch strength that can be expressed by TCH are 6 as an example.
4 and each tone color area corresponds to touch 0 to 63 6
It has four address locations. For each touch intensity
Address where the touch intensity belongs
Relative address data related to the loop (touch group
Dress). Touching as an example
The number of loops is 16. Therefore, the touch group table
Is addressed by tone code VN and touch code TCH
It is. This touch group table has parameter memory
47 predetermined absolute addresses (this is the offset address OA
It occupies a storage area starting from D1). This
Absolute address data for reading the switch group table.
Data is 5 bits above the 6-bit touch code TCH
11-bit relative address data
Data (address with offset address OAD1 set to 0)
And add this to the offset address OAD1
Created by Parameter address table is set for each key group.
For each tone, and for each tone
Relative address of the address that stores the router parameter
Stores data (called parameter address).
This parameter address table is used for each key group.
Includes 44 key group areas corresponding to 0-43
This key group area is
Address by the key group address read from the
Be relieved. Each key group area corresponds to tones 0 to 31
Each of the 32 timbre-specific areas
The area is addressed by the timbre code VN. Each tone
Another area is 16 adverts corresponding to touch groups 0 to 15.
Each address position has the above-mentioned touch
Touch group address read from group table
Address. In addition, 2
A memory location for bytes is allocated, and the above-mentioned pad is stored there.
The parameter address data is stored in 12 bits.
This parameter address table is stored in the parameter memory 47.
A predetermined absolute address (this is the offset address OAD2
). This para
Absolute address to read the meter address table
For data, set the least significant bit to “0” or “1”.
(This means that one address position is two bytes, that is, two absolute addresses.
4 bits touch glue on top.
Address data, and the upper 5 bits
Locate the tone code VN, and the upper 6-bit key
Position the group code and add a total of 16 bits of relative address.
Address (offset address OAD2 is 0)
) And add this to the offset address OAD2
It is created by The parameter bank is an example of 2620 types of filter
Parameters from 0 to 26
Includes 2620 parameter storage areas corresponding to 19
You. One parameter storage area is a storage location of 32 bytes
Including (32 absolute address positions),
Parameters corresponding to one set of filter coefficients are stored.
You. The first-order filter coefficients are stored in 2-byte storage locations.
This is broken down into 12-bit files, as described above.
Filter coefficient data (COE) and 3-bit weighting data
(WEI) and 1-bit even / odd identification data (EO).
However, weighting data (WEI) and even / odd identification data (EO)
Is common among the orders in one set of parameters
Therefore, the data is stored only in the first-order storage location, and storage locations of other orders
Do not remember. However, the weighting data (WEI)
It is also possible to store each order independently.
This parameter bank contains the parameter address
The parameter address read from the
Be relieved. The parameter bank of the parameter memory 47
A predetermined absolute address (this is the offset address OAD3
The memory area starting from This parame
The absolute address data for reading the data bank is 12
17-bit relative address
Address data (address with offset address OAD3 set to 0)
Address) in the upper 12 bits of the
Address data OAD3
It is created by adding to. This absolute address
The lower 5 bits of data in 32 steps
The parameter specified by the parameter address
A set of filters consisting of 16 orders in the meter storage area
The parameters are read out sequentially. Hierarchical parameter memory as shown in Fig. 21
The structure is advantageous because it can save memory capacity
is there. Rather than doing this, 44 key groups, 32 tones, 16
Supports all combinations of touch groups (22528 patterns)
If you store the filter parameters individually,
A storage capacity of 528 × 32 bytes is required, but as shown in Fig. 21
In this case, the parameter address table 1408 (= 44 ×
32) x 32 bytes and 2620 x 32 bytes of the parameter bank
Only a combined storage capacity of 4028 x 32 bytes is required.
In other words, a combination of key groups, tones, and touch groups
Filter parameters are common even if
There are 22528 ways in the example of Fig. 21 as they may be used.
Structure that shares 2620 kinds of parameters for the combination of
In this way, the memory capacity is saved. <Parameters are processing unit 45, parameter
Lector 46, parameter memory 47, parameter supply circuit 4
8, 49: Fig. 15> The parameter processing unit 45 is
Parameter note as described above for
It controls the reading of the memory 47. Program memo
The parameter memory 47 as described above is read into the re-451.
A program for executing control is stored. Blog
The ram counter 452 reads the program memory 451
8 steps of program step signal PC
Page shift register 86 and addition notation 87, gates 88 and 89,
It includes a command detection circuit 90 and counts the number of channels.
The operation is performed in a time-sharing manner. Key-on pulse KONP is Inver
It is inverted by the switch 91 and added to the control input of the gate 88. This key
-On-pulse KONP becomes signal “1” at the beginning of key press.
Therefore, the one corresponding to each channel is time-division multiplexed.
ing. Addition 87 is a gain for the output of shift register 86.
Adds "1" given from port 89, and adds
The result is provided to shift register 86 through gate 88.
You. The end detection circuit 90 detects that the output value of the shift register 86 is
Detects whether the last step of the program has been reached
Therefore, if the final step is not reached, output signal "0"
The signal “1” is input to the control of the gate 89 through the inverter 92.
Signal "1" is added to force and count up 1
As given in Note 87, but reached the final step
Output the signal "1" and output the signal via the inverter 92.
Give “0” to gate 89, close gate 89, and count
Don't do it. With the above configuration, the contents of the program counter 452
The key-on pulse KONP occurred in the round step signal PC.
When it is reset to "0", the shift register 86 makes one cycle.
Every time you do it (every 8 time slots), you get 1 count up
The count stops when the final step is reached.
It is. As an example, the number of program steps is 37,
The step signal PC output from the counter 452 starts from "0".
It changes sequentially up to "36" (final step). Step signal
PC is the output of the shift register 86,
Things are time-division multiplexed. The program memory 451 stores the input step signal PC
Read the selection control signals SELC1 to SELC4 according to the step
And to read the offset address memory 453.
Is read. Offset address memo
453 uses the value 3 of the offset address OADS to OAD3 described above.
I remember. Read from offset address memory 453
Any of the issued address data ADOF (OADS to OAD3)
Is input to the adder 454. Adder 454 is selector 455
Relative address data RADD and offset add given by
Address data ADOF and the output is added as address data
It is added to the address input of the parameter memory 47 as PRAD.
You. Key group address register 456, touch group
Address register 457, Parameter address register 458
Each consists of an 8-stage shift register,
Group address data KEYG, touch group address data
Data TCHG, parameter address data PAD for each channel
It is stored for each time division. Each register 456-4
Selectors 93 to 95 are provided on the input side of 58,
The data read from the data memory 47 is stored in each selector.
Join the other input. The other input of each selector 93-95
The output of each register 456-458 is added. Selector 93-95
Select control signals SELC2 to SELC4 from program memory 451
To be given to the steps of the program
Accordingly, the 7 read output data of the parameter memory 47
Populate registers 456-458 or register 456
Controls whether to retain the data once captured in ~ 458
I do. Obviously, from the parameter memory 47,
When the key group address data of is read
To the key group address register 456,
When the touch group address data of
Take this into the touch group address register 457,
When the above parameter address data is read
Take this into the parameter address register 458
Selection control signals SELC2 to SELC4 are generated. Address data KE stored in each register 456 to 458
YG, TCGH, and PAD are input to the selector 455. Sector 455
Has key code KC, tone code VN and touch code TCH
Steps output from the program counter 452
Least significant bit PCLSB of signal PC and whether this step signal PC
Also input data PC-4 minus “4” (binary “100”)
Have been. In the selector 455, from the program memory 451
The input data is stored according to the applied selection control signal SELC1.
Relative address selected in a fixed combination and the selected data
In the bit position corresponding to the predetermined weight in the data RADD
Position and thus create the relative address data RADD.
Power. In this parameter processing unit 45
The processing contents of the 37 steps performed are as follows. When PC = 0: Key group table read processing Selects key code KC by selection control signal SELC1, and
Keyset table as fuset address data ADOF
Read offset address OADS. Also, the selection system
Output data of parameter memory 47 by control signal SELC2
Take in the key group address register 456. to this
From the key group table in parameter memory 47
Reads the key group address corresponding to the key code KC
And this is stored in register 456. PC = 1: Touch group table read processing Selects tone code VN and touch code TCH by signal SELC1
TCH in the least significant bit and VN in the higher bit.
Then, the relative address data RADD is created. Offset
Off touch group table as dress data ADOF
Read the set address OAD1. Also, the signal SELC3
Output data from the parameter memory 47 by touch group
Take it into the dress register 457. This allows the parameter
Tone code VN from the touch group table of data memory 47
And touch group address corresponding to touch code TCH.
Read out and stored in register 457. When PC = 2 or 3: Parameter address table read processing
The key group address data KEYG,
Voice code VN, touch group address data TCHG, switch
The least significant bit PCLSB of the step signal PC is selected, and the least significant bit PCLSB is selected.
Relative to PCLSB, TCHG, VN, KEYG
Create address data RADD. Data as para as para
Read the offset address OAD2 of the meter address table
Protrude. In addition, the signal SELC4 causes the parameter memory 47
Capture output data to parameter address register 458
No. As a result, the parameter address of the parameter memory 47 is
The appropriate parameter address is read from the table.
Which is stored in register 458. As mentioned above,
One parameter address data consists of 12 bits,
It is stored in a 2-byte storage location (see FIG. 21).
When bit PCLSB is “0” (PC = 2 step), the lower
8-bit parameter address data is read out and PC
When the LSB is “1” (PC = 3 step), the upper 4
Parameter address data of the network. Sele
This parameter address data is 12 bits
Register the bit positions so that they are parallelized to the data.
Store at Star 458. When PC = 4 to 35: Parameter bank read processing Reduces parameter address data PAD by 4 by signal SELC1.
Select the calculated step signal PC-4 and start from the least significant bit
Relative address data RADD by positioning in the order of PC-4 and PAD
Create Also, the parameter bank as data ADOF
Read the offset address OAD3 of. Signal PC-4 is
In 32 steps of PC = 4 to 35, the value is from "0"
It changes to "31". Therefore, depending on the parameter address
A set of filter parameters consisting of 32 bytes specified by
Data (see Fig. 21) is the parameter in parameter memory 47
The data is sequentially read from the bank one byte at a time. When PC = 36: Stop program counter 452
Complete the filter parameter read sequence.
You. The filter parameters read from the parameter memory 47
The data is input to the timing synchronization circuit 459. This time
Path 459 generates program step signal PC and timing signal
The timing given from the decoder 56 of the raw circuit 39 (FIG. 13)
Signal group TS1 and accepts each signal based on these signals.
Synchronize a number of filter parameters in time
Output. The output of this synchronization circuit 459 is static
Parameter set as filter parameter SPR for mode
It is applied to the A input of the rector 46. Parameter selector 46
Is the microcomputer interface 44 (Fig. 11) for the B input of?
Output filter parameters for dynamic mode
DPR is given. The selection control input SB of the selector 46
Dynamic output from the microcomputer interface 44
/ Static selection signal DS
In the loading mode, select the B input parameter DPR and
In input mode, the A input parameter SPR is selected. The output of the selector 46 is a parameter supply circuit 4 for each of the A and B systems.
Entered at 8,49. A detailed example is shown only for the A series circuit 48.
However, the B-series circuit 49 has the same configuration. Parameter supply
In circuit 49, distribution circuit 485 is
Out of the parameter data given to
Import data on channels 1 to 4
In addition to parallelizing channels, filter coefficient data (channels)
In channel 1, COEA1), weighted data (channel
1, WEIA1), even / odd identification data (EOA for channel 1)
1) Parallelized separately and correspond to each channel
It is distributed to the memory circuits 481 to 484. Such distribution control
The appropriate timing signal TS2 to generate the timing signal
The distribution circuit generated by the decoder 56 of the circuit 39 (FIG. 13)
Given to 485. Memory circuits 481 to 484 show detailed examples for channel 1.
However, the same applies to other channels. 12 bits
The filter coefficient data COEA1 of
It is input to the shift register 97 of the stage. This filter
Coefficient data COEA1 for 16 orders in 16 time slots
Data is time-division multiplexed.
The data is taken into each stage of the shift register 97.
The contents of the shift register 97 are cyclically held via the selector 96
Is done. The 3-bit weight data WEIA1 is stored in the latch circuit 9.
Entered in 8. The 1-bit even / odd identification data EOA1 is
Input to the switch circuit 99. A selector 96 and a latch circuit 98,
The control of 99 is performed by an appropriate control signal (not shown).
It is done at the timing. Ie static mode
When the key is pressed, the parameter memory 47
The 16th-order parameter data read from the
Via the synchronization circuit 459, selector 46 and distribution circuit 485
Then, in synchronization with the timing input to the memory circuit 481,
Selector 96 selects 16th-order filter coefficient data COEA1
Latch 97 and the latch circuits 98 and 99 are weighted.
WEIA1 and even / odd identification data EOA1 are latched. Less than
Later, a new press key is assigned to that channel.
Memory of the shift register 97 and the latch circuits 98 and 99 until
Will be retained. On the other hand, in dynamic mode,
Selector 46, distribution from con interface 44 (Fig. 11)
Dynamic control parameter for the 8th order via circuit 485
In synchronization with the timing when the meter data DPR is given,
Eighth order filter coefficient of the parameter data DPR
Import data COEA1 into shift register 97 and weight
The data WEIA1 is latched by the latch circuit 98 and the even / odd identification data is
Latch circuit EOA1 in the latch circuit 99. After that, a new die
Until the dynamic control parameter data DPR is given.
The memory of the shift register 97 and the latch circuits 98 and 99 is retained
Is done. In the dynamic mode, shift
Corresponding to 9th to 16th of 16 stages of register 97
8 stages of dynamic control parameters for 8 stages
And store the filter coefficient data of the
The contents of the corresponding eight stages are set to 0. It is output from the shift register 97 of each memory circuit 481 to 484.
The filter coefficient data to be supplied to the selector 486,
In accordance with the timing signal TS3,
Selected and time division multiplexed. Thus, the channel
Filter coefficient data for 1 to 4 are time-division multiplexed.
And the power of the A-series as the A-series filter series data COEA
It is supplied to the calculator and accumulator section 41 (Fig. 14). The weight output from the latch circuit 98 of each memory circuit 481 to 484 is
The found data is given to the selector 487, where it is timed.
Signal of each channel is selected sequentially according to the
And time-division multiplexed. Time multiplexed in this way
Weighted data WEIA of channels 1-4 is multiplied by A sequence
It is supplied to the instrument accumulator section 41 (FIG. 14). Each latched in the latch circuit 99 of each memory circuit 481 to 484
The even / odd identification data EOA1 to EOA4 of channels 1 to 4 correspond to
Channel state memories 401-404 (Fig. 14)
Given in columns. <Pitch synchronization output circuit 50: FIG. 16> In FIG.
From the multiplier and accumulator unit 41 (FIGS. 11 and 14)
The output filtered tone signal of channels 1 to 4
The sample value data SMA is given in time division multiplex. 14th
In the illustrated latch circuit 85, the fill of each channel 1 to 4
The timing at which the output that has been
Column is the last accumulated time slot (shaded area).
This allows filtered samples of each channel 1 to 4
FIG. 17 shows the channel timing of the value data SMA.
Become like The B input multiplier is used for the C input of the selector 501.
And the channel output from the accumulator 43 (FIG. 11).
Filtered tone signal sample value data for channels 5 to 8
SMB is given in time division multiplex. This data SMB
The channel terminating is as shown in FIG. 8-stage shift register for A input of selector 501
The output of the selector 502 is provided, and the output of the selector 501 is
Input to the register 502. Shift with this selector 501
Register 502 is the filtered support for each channel 1-8.
The sample value data is converted to the PS1 channel timing shown in Fig. 3.
High-speed time-division tie per time slot as shown in
This is for time-division multiplexing according to the timing. No.
From the decoder 56 in FIG. 13 to time slots 57, 13, 26, 46
Signal 1REGLDA and time slot
Timing signal that becomes "1" in units 11, 31, 44 and 64
1REGLDB is generated, and this is the B selection of the selector 501 in FIG.
Selection control input SB and C selection control input SC. to this
Of the data SMA given to the B input
The data of rule 1 is time slot 57 (this is shown in Fig. 3).
Channel 1 timing of PS1 channel timing
Data corresponding to channel 2)
Is the time slot 13 (PS1 channel 2
), And the data of channel 3
Slot 26 (timing of channel 3 of PS1 in FIG. 3)
), And the data of channel 4 is
To 46 (timing of channel 4 of SP1 in Figure 3)
Selected. In addition, the data SMB
That is, the data of channel 5 is stored in time slot 11 (FIG. 3).
Timing of PS5 channel 5)
The data of channel 6 is stored in time slot 31 (PS1 in FIG. 3).
Channel 6 timing), channel 7
The data of time slot 44 (channel of PS1 in Figure 3
Data at channel 8
Is the time slot 64 (PS1 channel 8
Imming) is selected. The timing signals 1REGLDA and 1REGLDB are
The inverted signal is given to the A selection control input SA of the selector 501.
It is. Therefore, at each timing described above, the shift register 50
Filtered sample for each channel captured in 2
The value data is stored in the shift register at other times.
502 is circulated and held. The output of the shift register 502 is applied to the A input of the selector 504.
available. The output of the selector 504 is the shift stage of 8 stages.
It is input to Dista 505. The output of shift register 505 is
The signal is returned to the input side via the B input of the collector 504. SEREC
And the shift register 505
Playback sampling of output music signal in synchronization with its pitch
It is for doing. A selection control input S of selector 504
A is provided from input interface 38 (FIG. 12)
The delayed pitch synchronization signal PS1D is delayed by 8 time slots.
It is input via the delay circuit 506. In FIG. 12, the pitch synchronizing signal PS1 is the OR circuit 51.
It is input to the 64-stage shift register 100 via.
24 time slots delayed in this shift register 100
The pitch synchronization signal is input to the AND circuit 101, and 40 times
The slot delayed signal is input to the AND circuit 102, and 4
The signal delayed by 8 time slots is input to AND circuit 103
And the circuit 10 delayed by 64 timeslots
Entered in 4. To the other inputs of each AND circuit 101-104
Is the timing signal generated by the decoder 56 of FIG.
PSS1 to PSS4 are input respectively. Of each AND circuit 101-104
Output is given to OR circuit 105 and delayed pitch synchronization
The signal PSID is obtained. Generation timing of each signal PSS1 to PSS4
Are as shown in parentheses in FIG. There
In, for example, the display "1y8" is 8 time slots
The signal "1" may occur in the first time slot of the cycle.
And Therefore, in the case of the timing signal PSS1, "1y8,
3y8 ”, the first and third in eight time slot odors
A signal "1" is generated in each of the second time slots. Thirteenth
The indication in parentheses of each signal PSS1 to PSS4 in the figure and the PS in FIG.
Seen with channel timing 1 and
In addition, the signal PSS1 is the timing of channels 1 and 3 in PS1.
And PSS2 is connected to channel 2 in PS1.
It becomes “1” at the timing of 6, and PSS3 is the channel in PS1.
It becomes “1” at the timing of channels 3 and 7, and PSS4 becomes PS1
It becomes “1” at the timing of channels 4 and 8 in the channel. From the above, the pitch synchronization signal PS1 of channels 1 and 5
24 time slots, 2 and 6 PS1 40 time slots
PS3 of 3 and 7 is 48 time slots, PS1 of 4 and 8 is 64
Time slot, delayed pitch for each delayed
Synchronous signal PS1D. Thus delayed by the channel
The reason for the different delay times is the adaptive digital fill.
Channels 1 to 4, 5 to 5 in the data device 21 (FIG. 11).
This is because the calculation timing of FIG. Referring back to FIG. 16, the delayed pitch synchronization signal PS1D is delayed.
The circuit 506 further delays by 8 time slots, and the selector 504
Given to the input SA of. Selector 504 is a channel
When the signal PS1D of is “1”, the channel is filtered
Sample value data is fetched from the shift register 502,
Input to the shift register 505. At other times,
Shift register 505 via the B input of selector 504B
Is kept in circulation. Thus, the selector 504 and shift
Filter of each channel in the circuit of register 505
The sampled value data that should be generated on that channel.
Resampled in sync with the pitch of the sound. <Pitch Synchronous / Asynchronous Switching of Filter Operation> From the microcomputer interface 44 (FIG. 11) to the
A Pitch synchronous / asynchronous designation signal PASY given to the circuit 51
Is always "0" when performing filter operation with pitch synchronization.
Input interface 38 responds to pitch synchronization signal PS1.
Filter request signals φF1 to φF8 and the delayed
Generate a sync signal PS1D. Therefore, the pitch sync signal
When PS1 occurs, that is, the musical sound to be filtered
The sampling period synchronized with the signal pitch
Filter calculation is performed. This will give you
Ruta characteristics are moving formants. When performing the filter operation without synchronizing to the pitch,
The pitch synchronous / asynchronous designation signal PASY is always set to “1”. Obedience
Therefore, the output of the OR circuit 51 in FIG.
Is always "1" regardless of the presence or absence of. Therefore, the input
The interface 38 is used for each filter operation cycle (64 time
Filter calculation request signals φF1 to φ at fixed intervals for each lot)
Generate F8 and signal PS1D. Therefore, the digital fill
Sampling frequency in data calculation is independent of pitch
Constant (for example, 50kHz) and the resulting filter characteristics
It becomes a fixed formant. <Modification> The pitch synchronization output circuit 50 shown in FIG.
Pitch synchronization processing by channel time division using 502 and 505
However, it is not limited to this, but it is parallel for each channel.
A memory circuit is installed to perform pitch synchronization processing in parallel.
You may do it. In the above embodiment, the digital filter has a pair of coefficients.
Although an FIR filter showing the nomenclature was used,
A FIR filter having a so-called coefficient may be used. Also Phil
The model is not limited to FIR, but IIR (infinite impulse response)
Other types may be used. Storage format of parameter memory shown in Fig. 21
Is not limited to this, and various modifications are possible. Also, the method of addressing the parameter memory is as described above.
Not limited to the procedure shown in the example, various modifications are possible. An example
For example, in the embodiment, the key group table is accessed first.
And then access the touch group table
However, this may be reversed. Fig. 15 shows the progress
A micro-processor that stores the readout procedure in the RAM memory 451 in advance
Programming method, which allows the
The data is read from the memory 47.
Complete hardware, regardless of the
Ear circuit or complete software program
The read control may be performed in such a manner. In the above embodiment, the determinant of the parameter is pitch /
The range, key touch, and timbre types
Not limited to For example, time lapse is included in the parameter determinant.
Filter that changes with the passage of time following the tone generation
The parameters may be read. In that case, the fifteenth
The parameter processing unit 45 shown in the figure
It shall be designed appropriately so that it can operate. Also, yellowtail
Depending on the amount of operation of appropriate manual controls such as lance controls
The output may be used as a parameter determinant. Further, in the above embodiment, this is applied to a multi-tone electronic musical instrument.
Although the invention is applied, it is also applicable to single-tone electronic musical instruments.
Of course, it can be used. Also, dedicated electronic
Not only musical instruments but also devices with musical signal generation or processing functions
In general, the present invention can be applied. In the above embodiment, the tone generator
Digital music signal input to digital filter device
Signal sample value data itself
It is assumed that it is in a ring state, but this
Not limited to For example, pitch asynchronous fixed sampling
Digital tone signal sampled at
Pitch synchronization signal even when input to the
Sample this input digital tone signal
Perform filter operation synchronized with pitch while correcting
You can do it. In the above embodiment, the pitch synchronizing signal generation circuit
Included in the
Switch to the adaptive digital filter device.
But it is not limited to this. For example,
Digital Music Sound with Sampling Period Synchronized with Switch
When inputting the signal to the digital filter,
Change in the sampled tone data signal
Generates a pitch synchronizing signal.
Control the filter operation by the switch synchronization signal.
It may be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an outline of the present invention, FIG. 2 is a block diagram showing an overall configuration of an electronic musical instrument according to an embodiment of the present invention, and FIG. A timing chart showing timings of main signals, FIG. 4 is a block diagram showing an example of a pitch synchronization signal generating circuit included in the tone generator shown in FIG. 2, and FIG. 5 is a block diagram showing a basic configuration of an FIR filter. 6 and 7 are graphs showing examples of the symmetry of the impulse response in the linear phase FIR filter when the order N is odd and even, respectively, and FIGS. 8 and 9 are the frequencies in the linear phase FIR filter. FIG. 10 is a graph showing an example of response characteristics when the order N is odd and even, respectively. FIG. 10 is a flowchart showing an example of a procedure for obtaining the filter coefficient, and FIG. 2 is a block diagram showing an example of the adaptive digital filter device in FIG. 2, FIG. 12 is a block diagram showing an example of the input interface in FIG. 11, and FIG. 13 is a block diagram showing an example of the timing signal generating circuit in FIG. FIG. 14 is a block diagram showing an example of the state memory, the multiplier, and the accumulator section (that is, an example of the FIR type digital filter circuit) in FIG. 11, and FIG. 15 is an example of the parameter processing unit and the parameter supply circuit in FIG. 16 is a block diagram showing an example of the pitch synchronization output circuit in FIG. 11, FIG. 17 is a timing chart showing an example of generation of various signals for controlling the filter calculation timing, and FIG. Realizes filter characteristics of even-order (32nd-order) in the digital filter circuit shown in the figure. Fig. 19 is a schematic diagram for explaining the basic operation of the FIR type filter operation in the case of the following, Fig. 19 shows the basic operation of the FIR type filter operation when realizing the filter characteristics consisting of odd orders (31st order) in the same digital filter circuit. FIG. 20 is a diagram showing the filter operation timing for eight channels in the A, B2 series digital filter circuit as shown in FIG. 14, and FIG. 21 is shown in FIG. 11 and FIG. It is a figure which shows an example of the storage format in the parameter memory shown. 110 ... parameter storage means, 111 ... parameter address storage means, 112 ... readout means, 10 ... keyboard, 11 ...
Key touch detector, 18 ... Tone generator, 19 ... Pitch synchronization signal generation circuit, 21, 22 ... Adaptive digital filter device, 40, 42 ... State memory, 41, 43
... Multiplier and accumulator unit, 45 ... Parameter processing unit, 47 ... Parameter memory, 50 ...
Pitch synchronization output circuit.

Continuation of front page    (56) References JP-A-59-49595 (JP, A)                 JP 58-40593 (JP, A)                 JP-A-56-117291 (JP, A)                 JP 61-264397 (JP, A)                 JP-A-61-264396 (JP, A)                 JP-A-61-45298 (JP, A)                 JP-A-59-197096 (JP, A)

Claims (1)

(57) [Claims] Parameter storage means for storing a plurality of sets of filter parameters, and address data for instructing addresses in the parameter storage means of filter parameters to be read from the parameter storage means in correspondence with a combination of a plurality of parameter determinants The parameter address storage means is characterized in that among the stored respective address data, the same address in the parameter storage means is designated for different combinations of the parameter determinants, In response to an input specifying a combination of determinants, specific address data corresponding to the combination of parameter determinants specified by the input is read from the parameter address storage means, and the parameter is read according to the read address data. Filter parameter supply device with a reading means for reading a set of filter parameters from 憶 means.