JPS62127899A - Musical sound signal processor using digital filter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a musical tone signal processing device using a digital filter, and is used in electronic musical instruments and other devices having a musical tone generation function.

[Conventional technology]

The use of a digital filter in the timbre circuit of an electronic musical instrument is disclosed, for example, in Japanese Patent Application Laid-Open No. 59-44096. Conventional digital filters execute filter operations at regular sampling periods determined by the system, and the resulting filter characteristics are fixed formants.

[Problem that the invention seeks to solve]

In conventional tone color circuits using digital filters as described above, in order to achieve filter characteristics of moving formants, it is necessary to change the filter coefficients depending on the pitch of the input musical tone signal, which requires a large number of filter coefficients. Therefore, the capacity of the filter coefficient storage means becomes large, resulting in a complicated and large-sized device configuration.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a musical tone signal processing device using a digital filter that can realize moving formant filter characteristics with an extremely simple configuration.

[Means for solving problems]

FIG. 1 shows an outline of the present invention, and the musical tone signal processing device according to the present invention includes pitch synchronization signal generating means 110 that generates a signal PS synchronized with the pitch of a digital musical tone signal, and and a digital filter circuit 111 that executes a filter operation at a sampling period synchronized with the pitch synchronization signal PS generated from the pitch synchronization signal generating means 110.

In FIG. 1, the basic configuration of an FIR filter is schematically shown as an example in a block of a digital filter circuit 111, and filter operation synchronized with the pitch is performed by using the pitch synchronization signal PS as a sampling clock signal with a unit delay. will be held.

Further, according to the present invention, means is further provided for generating a pitch synchronization/asynchronous designation signal for designating whether the filter calculation should be performed in synchronization with the pitch of the musical tone or asynchronously,
In the digital filter circuit 111, this pitch synchronization/
Depending on the asynchronous designation signal, the filter operation may be performed in either the pitch-synchronized sampling period or a predetermined common sampling period.

[Action and effect of the invention]

The sampling period at which the filter calculation is performed in the digital filter circuit 111 is not a fixed period, but a period synchronized with the pitch of the input digital musical tone signal. The position of the formant in the digital filter is determined based on the sampling frequency. Therefore, if the sampling period of the filter calculation changes in synchronization with the pitch, the resulting filter characteristic will be a moving formant in which the formant position changes in synchronization with the pitch.

In addition, by switching the calculation period of the filter to a pitch-synchronized period or a predetermined common period using a pitch synchronous/asynchronous designation signal, a moving formant is used during pitch-synchronous operation, and a fixed formant is used during pitch-asynchronous operation. Realized. Therefore, the moving formant and the fixed formant can be easily selected according to the characteristics (for example, timbre) of the musical sound to be realized. Pitch synchronization/
The means for generating the asynchronous designation signal may be any suitable means such as a tone selection switch, effect selection switch, dedicated switch, or externally provided performance information data, and is linked to the selection operation of the tone or effect, etc. The filter calculation operation can be switched between pitch synchronization and asynchronous operation based on a dedicated switch operation, or in response to information input from the outside.

Therefore, according to the present invention, a moving formant can be realized with an extremely simple configuration in which filter calculation is executed at a sampling period synchronized with the pitch, and the excellent effects of simplicity and low cost are achieved.

In addition, since it is possible to easily switch between pitch synchronization and asynchronous filter operation, it is possible to easily switch between moving formant and fixed formant according to the characteristics of the timbre to be achieved by the digital filter or the characteristics of the effect imparted to the musical tone. This provides an excellent effect in that switching can be performed freely.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Description of overall configuration of one embodiment> In FIG. 2, a keyboard 10 is provided with a plurality of keys for specifying the pitch of musical tones to be generated.

The key touch detector 11 detects a touch applied to a pressed key on the keyboard 10, and may detect either an initial touch or an aftertouch. The timbre selection device 12 consists of a group of operators for selecting the timbre of the musical tone to be generated. The pitch bend operator 13 is for continuously modulating the pitch of the musical tone to be generated according to the amount of operation thereof, and is composed of, for example, a dial type operator. The microcomputer 14 includes a CPU (Central Processing Unit) 15, a ROM (Read Only Memory) 16 that stores programs and other data, and a RAM (RAM) for working and data storage.
Random access memory) 17, which sends and receives data to and from each circuit in the electronic musical instrument via a data and address bus 28, performs key press detection processing on the keyboard 10, and determines pressed keys for multiple sound generation channels. It executes a sound generation assignment process, a process of detecting a tone selection operation in the tone color selection device 12, a process of detecting an operation amount of the pitch bend operator 13, and various other processes.

The tone generator 18 is capable of independently generating digital musical tone signals in a plurality of sound generation channels, and has a key code K indicating the key assigned to each channel.
C, a key-on signal KON indicating whether the key is on or off, and other necessary data are sent from the microcomputer 14 to the bus 2.
Tone generator 18
contains a pitch synchronization signal generation circuit 19,
A pitch synchronization signal synchronized with the pitch of the musical tone signal generated in each channel is generated for each channel.

In the specifications of this embodiment, the tone generator 18
generates digital musical tone signals in a time-divisional manner using the first to sixteenth channels (Chi to Ch16), a total of 16 channels. The digital musical sound waveform sample value data output from the tone generator 18 in a time-division multiplexed manner is
Indicated by The master clock pulse φ generated by the master clock generator 20 controls the basic operating time of the tone generator 18. One cycle of time division multiplexing of digital musical waveform sample value data TDK is 64 cycles of the master clock pulse φ, and each cycle in this 64 cycles is divided into one time slot.
The numbers 64 to 64 are shown in FIG. 3. The figure also shows the specifications of channel timings 1 to 16 of the multiplexed digital musical tone waveform sample value data TDK. For example, the data TDX of the first channel is assigned to four time slots 33-36.

In the specifications of this embodiment, the musical sound waveform sample value data TDX is commonly multiplexed and output as data for 16 channels as described above, but the pitch synchronization signals Psi and PS2 of each channel are divided into two systems. The signals are time-division multiplexed and output every eight channels. One pitch synchronization signal PS1 is obtained by time division multiplexing the first to eighth (Chi to chs) pitch synchronization signals, and its channel timing is as shown in FIG. The other pitch synchronization signal P
S2 is obtained by time division multiplexing the ninth to sixteenth (Ch9 to Ch16) pitch synchronization signals, and its channel timing is as shown in FIG.

As is clear from the figure, the pitch synchronization signals Psi and PS2 of each channel are generated with a width of one time slot, and one cycle of time division multiplexing is eight time slots.

Two series adaptive digital filter device (hereinafter referred to as A
21 and 22 (sometimes abbreviated as DF) are digital filter devices configured to be suitable for filtering musical tone signals, and according to the specifications of this embodiment, it is possible to filter musical tone signals for 8 channels each. , one ADF 21 filters the musical tone signals of the 1st to 8th channels, and the other ADF 21 filters the musical tone signals of the 9th to 16th channels.
Filters the musical tone signal of the channel.

Inside the ADF21.22, there is a digital filter circuit of a predetermined type, a filter parameter memory, various circuits that control the supply of filter parameters, and a control that performs filter calculation operation in synchronization with the pitch of the musical tone signal to be filtered. It includes circuits for various functions, such as a pitch synchronization output circuit that outputs a filtered musical tone signal in synchronization with its pitch, and has a configuration suitable for filtering musical tone signals.

The digital musical tone waveform sample value data TDX output from the tone generator 18 is input to the ADFs 21 and 22. Furthermore, the pitch synchronization signals PS1 of the first to eighth channels are input to the ADF 21, and the pitch synchronization signals PS2 of the ninth to sixteenth channels are input to the ADF 22. In ADF21 and 22, pitch synchronization signals PS1 and P
The data TDX of the channel corresponding to the time slot in which S2 has occurred (the signal becomes "1") is taken in, and a filter operation is performed on the one sample value data of that channel. Therefore, in one ADF21,
The filter calculation for the musical tone signals of the first to eighth channels is performed in accordance with the pitch synchronization signal PS1, and the other ADF 22 performs the filter calculation of the musical tone signals of the ninth to sixteenth channels in accordance with the pitch synchronization signal PS2. In this way, ADF
The unit time of the filter calculation in 21 and 22 (signal delay time synchronized with the sampling period) is synchronized with the pitch of the musical tone signal to be filtered, and the moving formant characteristics are changed by changing the filter calculation unit time according to the pitch. filtering is realized. In addition, in order to control the basic operation timing of the circuit, the master clock pulse φ and the system synchronization pulse 5YNC are used.
is given to the ADFs 21 and 22. As shown in FIG. 3, the system synchronization pulse 5YNC is a pulse generated at a period of 64 time slots, and is synchronized with one cycle of time division multiplexing of the digital musical tone signal. Also, A.D.
Various data for controlling the filter operation is sent to F21 and F22 via the bus 28 to the microcomputer 1.
It is given under the control of 4.

In addition, in these ADFs 21 and 22, the actual filter calculation operation is not only performed in synchronization with the pitch of the musical tone signal to be filtered, but also resamples the filtered musical waveform sample value data in synchronization with the pitch. , the output is completely synchronized in pitch. Pitch synchronization signals PS1 and PS2 are also used to resample this filtered data in synchronization with the pitch.
is used.

The digital tone waveform sample value data of each channel outputted from the ADFs 21 and 22 is summed by an accumulator 23, and tone waveform sample value data is obtained by summing the sample value data of 16 channels. Accumulator 2
3 is converted into an analog musical tone signal by a digital/analog converter 24, and generated through a sound system 25.

In this embodiment specification, the supply of filter coefficients is controlled in two modes. One is "static mode"
This is a mode in which the filter coefficients are not changed during the tone generation period. The other is the "dynamic mode", which is a mode in which the filter coefficients are changed over time during the period in which musical tones are produced, and the timbre changes over time due to filtering. Filter coefficients for static mode are stored in filter parameter memories inside ADFs 21 and 22.

The filter coefficients for the dynamic mode are stored in a dynamic control parameter memory 26, which is read out while being switched over time under the control of the microcomputer 14, and sent to the ADF 21 and 2 via the bus 28.
given to 2. The dynamic/static selection switch 27 is a switch for selecting in which mode the supply of filter coefficients is controlled.

As an example of the clock frequency, the master clock pulse φ is approximately 3.2 MHz, the repetition frequency of one time division cycle (8 time slots) of the pitch synchronization signals Psi and PS2 is 400 kHz, and the digital musical sound waveform One time division cycle of sample value data TDK (
The repetition frequency of one operation cycle (64 time slots) in the filter is 50kHz.

Next, detailed examples of each circuit in FIG. 2 will be explained.

Regarding Generation of Pitch Synchronization Signal> FIG. 4 shows an example of the pitch synchronization signal generation circuit 19, which generates the pitch synchronization signal PS1 for one system a (channels 1 to 8). The other pitch synchronization signal PS2 is also generated by the same configuration as in FIG.

The pitch synchronization signal PS1 is generated based on time-divisionally counting the P number read out from the P number memory 29 by a counter 30 for each channel. The P number is a number indicating the number of sample points in one cycle of a musical sound waveform having a frequency corresponding to each pitch name C-B in the reference octave.

When the pitch synchronization signal PS1 is generated in an 8-channel time division manner as shown in FIG.
resolution) is 1/8 the frequency of the master clock pulse φ (for example, 400 kHz), which is common to all pitch names. On the other hand, since the basic sampling frequency is common, the P number of each note name shows a different value depending on the note name frequency. Let fn be the frequency of the pitch name in the reference octave, and fc be the above-mentioned common sampling frequency (400kHz), then the P number corresponding to the pitch name is determined as follows.

P number = fc÷fn - (1) where,
Common sampling frequency fc = 400kHz
, if the frequency fn of pitch name A is fn=440Hz (that is, A4 note), then the P number of pitch name A is calculated from the above formula.

P number of pitch name A = 400000÷440 = 90
It becomes 9.

On the other hand, if the number of sample points of different sample point amplitude values per cycle of musical waveform that can be generated within the tone generator 18 is 64, the effective sampling frequency fe of the frequency fn is fe = fnX 64 - (2), If fn=440Hz.

fe=440X64=, 28160Hz.

Similarly, the P number and effective sampling frequency fe of each pitch name in the reference octave can be determined as shown in the table below. In this case, the standard octave is G4
It is one octave from note to F#5.

In the counter 30 of Table 1 and FIG. 4, the pitch synchronization signal PS1
is obtained by dividing the common sampling frequency fc established based on the master clock pulse φ according to the P number. As is clear from the above, the P number is the number of cycles of the common sampling frequency fc in one cycle waveform, that is, the number of sample points.
The effective number of sample points per period of musical sound waveform that can be generated with 8 is 64 as described above. Therefore, if the frequency division number for dividing the common sampling frequency fc is equal to P number ÷ 64 (3), then 64 pulses can be obtained per musical tone period as the frequency division output, This allows all 64 effective sample points to be established. When the common sampling frequency fc is divided by the frequency division number determined in this way, from formulas (1), (2), and (3), fc ÷ frequency division number = (fn X P number) ÷ (P number ÷ 64) = fnX 64 = fe - (4), and by changing the sampling point address using this frequency-divided output, the effective sampling frequency fe can be established. The effective sampling frequency fe established in this way is in harmony with the pitch name frequency fn,
Pitch synchronization is achieved.

The pitch synchronization signal PS1 of each channel generated from the counter 30 is a frequency-divided output signal, that is, a signal having an effective sampling frequency fe as shown in the above equation (4) corresponding to the note name of the key assigned to that channel. It is.

By the way, the frequency division number determined by the above equation (3) is not necessarily an integer, but often includes a decimal number. For example, in the case of pitch name A, the frequency division number=909÷64414.20. Therefore, the frequency dividing operation in the counter 30 is to appropriately divide the frequency by two integers close to the frequency division number determined by equation (3) as described later, and the average result is the frequency division number determined by equation (3). The same result as dividing by is obtained.

In FIG. 4, the P number memory 29 stores in advance the P number of each pitch name in the standard octave as shown in Table 1 above. The key code KC of the key assigned to each channel is sent to the tone generator 1 via the bus 28.
8, and within the tone generator 18, the key code KC of the first to eighth channels is set to P in FIG.
Time-division multiplexing is performed at the timing shown in the channel timing of Sl, and key coats KC of the 9th to 16th channels are time-division multiplexed at the timing shown in the channel timing of PS2 in FIG. Key codes KC of the 1st to 8th channels time-division multiplexed in this way
is input into the P number memory 29. P number memory 2
9 is the input key code KC of the 1st to 8th channels
The P number is read out in a time-division manner in correspondence with the note name.

The counter 30 includes an adder 31 that inputs the P number read out from the P number memory 29, a selector 32 that inputs the output of this adder 31 to the rOJ input, and an 8-stage circuit that inputs the output of this selector 32. shift register 3
3, and a gate 3 which gates the lower bits (decimal part) of the output of the shift register 33 and supplies it to the other input of the adder 31.
4 and an adder 35 which inputs the upper bits (integer part) of the output of the shift register 33 and adds up all rr I I + times signals consisting of 7 bits in which all bits are 1''.The P number itself is a 12-bit binary coded signal, but the output of the adder 31 consists of a 13-bit signal including one extra bit as a carry signal bit.

The inverted key-on pulse KONP and the signal output from the carrier output co of the adder 35 are input to an AND circuit 36, and the output of this AND circuit 36 is input to the selector 32.
Adds to selection control input.

When the output signal of the AND circuit 36 is “0”, the adder 3
1, the signal applied to the rOJ input of the selector 32 is selected, and when it is 1'', the signal applied to the "1" input is selected. The "1" input of the selector 32 is connected to the lower bit (decimal part) of the output of the shift register 33 and the adder 35.
A 13-bit signal consisting of the output bits (integer part) of The key-on pulse KONP is a signal that becomes 111 IT only once at the beginning of the key press, and
Those corresponding to channels are time-division multiplexed.

Inverted key-on pulse KONP is this key-on pulse KO
This is a signal obtained by inverting NP.

The selector 32, shift register 33, and adder 35 establish a frequency division number as shown in equation (3) above according to the P number, and adjust the common sampling frequency fc according to the integer part of this frequency division number. This is a circuit for frequency division. Adder 3
1 is for adjusting the value of the integer part according to the decimal part of the frequency division number.

Since the divisor 64 in the above equation (3) is 2G, no special division is required to obtain the frequency division number.

By simply treating the lower 6 bits of the P number as a decimal part, the frequency division number corresponding to the P number can be established. Therefore, of the 13 bits of the output signals from the adder 31, selector 32 and shift register 33, the lower 6 bits are the weight of the decimal part, and the upper 7 bits are the weight of the integer part.

Adding all II I II times signals in the adder 35 is equivalent to subtracting 1. Therefore, adder 35
In effect, 1 is subtracted from the integer value of the output of the shift register 33. The result of the subtraction from the adder 35 is returned to the "1" input of the selector 32 together with the 6-bit data of the decimal part that has not been operated, and is again input to the adder 35 via the shift register 33. shift register 33
is shift-controlled by the master clock pulse φ, so the period at which the same channel signal is output from the shift register 33 is eight times the master clock pulse φ, that is, the period of the common sampling frequency fc.

At the beginning of pressing a key, the inverted key-on pulse KONP becomes '0''i only once at the channel timing to which the key is assigned, and at this time, the P number of the key is selected via the rOJ input of the selector 32. The integer part of the P number is given from the shift register 33 to the adder 35,
1 is repeatedly subtracted from the integer part at a cycle of the common sampling frequency fc. When the subtraction result of the integer part is a value of 1 or more, a carry signal “1” is constantly output from the carry signal output CO of the adder 35, and the AND circuit 36
Since the condition is satisfied, the selector 32 continues to select the "1" input. When the output of the adder 35 eventually becomes "OII" by repeating the subtraction, that is, when the same number of fc cycles as the number of integer parts of the P number have elapsed, the carry signal of the adder 35 is not output, and the AND circuit 36 The condition does not hold. At that time, the selector 32 selects the "0" input, and the lower 6 of the P number and the output of the shift register 33
The output of the adder 31, which is the sum of the bits (decimal part data), is selected. In this way, the P number whose value has been changed somewhat by the addition of the decimal part is given to the shift register 33, and the process of subtracting 1 from the changed integer value of the P number is repeated. In addition.

The gate 34 is disabled only at the beginning of key depression by the inverted key-on pulse KONP, and otherwise always supplies fractional part data to the adder 31. P in adder 31
By adding the decimal part data to the number, the integer value of the frequency division number actually used for frequency division may become one larger than the integer value of the frequency division number determined from the P number. For example, the P number of pitch name A is 909, and its frequency division number is 14.20.
However, at first, the branching is performed according to the integer value 14, but then it becomes 14.20+0.20=14.40, and eventually becomes 15.00, and the branching is performed according to the integer value 15. In this way, the common sampling frequency fc is divided according to the integer value of the frequency division number determined by the P number or one larger than that, and the average result is frequency division according to the frequency division number determined by the P number. Action is accomplished. The signal of the carryout output CO of the adder 35 corresponds to the frequency-divided output, and the signal inverted by the inverter 37 is output as the pitch synchronization signal PS1.

For better understanding, let's take pitch name A as an example and use selector 32.
An example of the change in output is shown below. The change timing is the cycle of the common sampling frequency fc.

The first is the frequency division number 14.20 corresponding to the P number 909, then the integer value is decreased by 1 to 13.20, and the following are 12.20.11.20.10.20, . . . 2 .2
0.1.20 and its integer value decreases by 1 one by one. fc
In the 14th period, the value added to the "1" input of the selector 32 becomes 0°20, and at this time the carry signal becomes 11.
01t, the pitch synchronization signal PS1 becomes 1", and the selector 32 selects the "0" input. The rOJ input of the selector 32 has a frequency division number 14.corresponding to the P number 909.
Decimal value 0.2 given from shift register 33 to 20
A value of 14.40 is given by adding 0. Therefore,
14.40 is output from the selector 32. After that, the output of selector 32 is 13.40.12.40.11.40
, . . 2.40.1.40, and the numerical value added to the "1" input of the selector 32 becomes 0.40 in the 14th cycle of fc, and the carry signal of the adder 35 decreases by 1. becomes '''OI+, and pitch synchronization signal PS1
is generated. At this time, the output of adder 31 is 14.20
+0.40 = 14.60, which is applied to the shift register 33 via the rOJ input of the selector 32. In this way, in the case of pitch name A, frequency division is performed using 14 or 15 as the frequency division number, and the common sampling frequency fc (
For example, the pitch synchronization signal PS1 becomes "1" every 14 or 15 cycles (400 kHz).

The pitch synchronization signal PS2 corresponding to the other 9th to 16th channels is also generated in the same manner as described above.

<Description of Tone Generator> The tone generator 18 uses the pitch synchronization signals PS1 and PS2 of each channel generated as described above to generate a musical tone signal according to a sampling timing synchronized with the pitch of the musical tone to be generated. You can do it like this. Of course, the present invention is not limited to this, and it is also possible to generate musical tone signals according to sampling timing that is not synchronized with pitch.

Address data specifying the sample point address (instantaneous phase angle) of the musical tone to be generated can be generated by independently counting the pitch synchronization signals PS1 and PS2 of each channel for each channel. However, the pitch synchronization signals PS1 and PS2 are in the aforementioned reference octave (0
4 to F#5 notes), so when generating the above address data, the count rate when counting the pitch synchronization signals PS1 and PS2 should be adjusted according to the octave range of the musical tone to be generated. Need to switch.

For example, when generating musical tones in the octave of 03 to F#4, each time pitch synchronization signals PS1 and PS2 are generated,
．． 5, and when generating musical tones in the octave from 04 to F#5, count by 1 every time the pitch synchronization signals PS1 and PS2 are generated, and when generating musical tones in the octave from G5 to F#6. , pitch synchronization signals PS1, PS2
Count 2 each time this occurs. In this way, address data that changes in synchronization with the pitch and octave of the musical tone to be generated is generated for each channel, and a digital musical tone signal is generated based on this address data.

Any musical tone signal generation method may be used in the tone generator 18. For example, a method of sequentially reading out the musical waveform sample value data stored in the waveform memory according to the above address data (memory read method), or a method of performing a predetermined frequency modulation calculation using the above address data as phase angle parameter data to sample the musical waveform. Any known method may be used, such as a method for obtaining value data (FM method), or a method for obtaining musical waveform sample value data by executing a predetermined amplitude modulation calculation using the address data as phase angle parameter data (AM method). May be used. Further, when the memory read method is adopted, the musical sound waveform stored in the waveform memory may be only a one-cycle waveform, but it is preferable to use a multi-cycle waveform because this improves the sound quality.

There are two methods of storing a multi-period waveform in a waveform memory and reading it out: For example, there is a method of storing the entire waveform from the start to the end of sound generation and reading it out once, as shown in Japanese Patent Laid-Open No. 52-121313, or a method of reading it out once. As shown in Japanese Patent Publication No. 58-142396, a method in which a multi-cycle waveform of an attack part and one or more cycle waveforms of a sustaining part is stored, and after reading the waveform of the attack part once, the waveform of the sustaining part is repeatedly read out; Alternatively, as shown in Japanese Patent Application Laid-open No. 147793/1983, there are various methods such as storing a plurality of discretely sampled waveforms, sequentially switching over and specifying the waveforms to be read out, and repeatedly reading out the specified waveforms. The following methods are known, and these methods may be adopted as appropriate.

(Preliminary Explanation of Adaptive Digital Filter) The calculation types of digital filters are basically finite impulse response (FIR) filters and infinite impulse response (IIR) filters, but the adaptive digital filter of this embodiment FIR filters are employed in devices 21,22. First, a general explanation related to FIR filters will be given.

(a) Basic circuit configuration of FIR filter Figure 5 is a diagram of the basic circuit configuration of an FIR filter.
n) is digital musical waveform sample value data at an arbitrary n-th sample point, and is an input signal of the FIR filter. z-1 is a unit time delay element, which sets a time delay of one sampling period. Therefore, x
(n-1) is the digital musical sound waveform sample value data of the n-1th sample point, and x(n-N+1) is the n
This is digital musical tone waveform sample value data at the -N+1st sample point. N is the duration of the impulse response and corresponds to the order of the FIR filter. h(o)～h
(N-1) is an Nth-order filter coefficient. The triangular block into which this filter coefficient is input is a multiplication element,
The data of each sample point delayed by the delay element z(n) ~
x(n-N+1) is multiplied by the corresponding filter coefficients h(0) to h(N-1), respectively. A block with a plus sign to which the multiplication output is input is an addition element, which adds and sums each multiplication output to obtain an output signal y(n).

The impulse response of such a FIR filter (h(n)
), that is, the transfer function is =h(0)+h(1)
It is expressed as z-1+-h(N-1)z-(N-"...(5).

(b) Linear phase characteristic of FIR filter One feature of such an FIR filter is that one phase characteristic can be made into a linear phase.

When a linear phase is used, the phases of the input and output waveforms of the filter completely correspond to each other with linear characteristics, and no distortion occurs in the output waveform. Therefore, it is suitable for filtering signals such as musical tones, voices, audio, etc. In a linear phase FIR filter, the phase characteristic is required to be θ(ω)=−αω (6) as a function of the angular frequency ω. Here, α is a constant called phase lag. In addition, FI with linear phase characteristics as described above
What are the necessary and sufficient conditions for the R filter?

The impulse response has symmetry as shown in equation (8) below, and the phase delay α is uniquely defined by the duration (filter order) N as shown in equation (7) below.

α= (N-1)/2 ... (7)
h (n) = h (N -1-n)
-(8) However, O≦n≦N-1 (c) Symmetry of filter coefficients The fact that the impulse response has symmetry as in equation (8) above means that the filter coefficients h(0) to h(N- 1) means that it has symmetry. That is, by setting the filter coefficients with symmetrical characteristics, the above-mentioned linear phase characteristics can be realized.

An example of the symmetry of the impulse response is shown in FIG. 6 when the order N is an odd number, and as shown in FIG. 7 when the order N is an even number. As is clear from the figure, n=(N−
1) If N is an odd number, the (N-1)/2nd order will be the center, and the impulse responses on both sides will be symmetrical. If N is an even number, (N-2)
The center is between the /2nd order and N/2, and the impulse responses on both sides are symmetrical.The filter coefficients of orders at 6 symmetrical positions have the same value, so it is necessary to prepare filter coefficients for all orders N. No, half of that is fine. Specifically, if N is an odd number, you only need to prepare ((N-1)/2)+1 filter coefficients from 0th order to (N-1)/2nd order, and ((N-1)/ 2) For the filter coefficients from the +1st order to the N-1st order, filter coefficients located at symmetrical positions from the 0th order to the ((N-1)/2)-1st order may be used. In other words, the same filter coefficient is used for 0th order and N-1st order, and 1
The same filter coefficients are used for the order and the N-2 order. Also, if N is an even number, just prepare N/2 filter coefficients from 0th order to (N-2)/2nd order, and filter coefficients from N/2nd order to N-1st order. From 0th order (N-2)/
It is sufficient to use filter coefficients located at symmetrical positions up to the second order.

(d) Frequency response of linear phase FIR filter Linear phase F whose impulse response shows symmetry as shown in Figures 6 and 7
Examples of the characteristics of the frequency response H'' (eJω) of the IR filter are shown in Figures 8 and 9. When N is an odd number, ω = π (here, π is the sampling frequency fs) as shown in Figure 8. (corresponding to 1/2 of As is clear from this, when the first order N is an odd number, it is possible to achieve bypass filter characteristics by setting the filter coefficients, but when N is an even number, bypass filter characteristics cannot be achieved. However, it is easier to design a filter when N is an even number, and it is suitable for designing a low-pass filter or a band-pass filter.

Therefore, it is preferable to switch the order N of the filter between even and odd depending on the filter characteristics to be achieved.
1.22 has a specification that allows such even-odd switching of the order N. That is, when filtering the characteristics of a band pass filter or a low pass filter, the order N is set to an even number, and when filtering the characteristics of a bypass filter, the order N is set to an odd number.

(e) Other features of the FIR filter Another feature of the FIR filter is that it has good stability because it has no feedback loop.

That is, when there is a feedback loop like an IIR filter, problems such as oscillation occur, but with an FIR filter, problems such as oscillation do not occur and the design is easy.

The FIR filter is also advantageous when the filter characteristics are changed over time. In this case, it is usually necessary to prepare separate sets of filter coefficients corresponding to each filter characteristic that differs over time, but in this case, a large number of sets of filter coefficients are required to refine the temporal fluctuations of the filter characteristics. It is said that In order to solve this problem,
Prepare two sets of filter coefficients that are a certain amount ahead of time,
By performing interpolation between the two sets of filter coefficients, sets of filter coefficients are generated densely as time passes between them, and filter characteristics that vary over time are set by the filter coefficients generated by the interpolation. is possible. In this way, when interpolating filter coefficients in real time to achieve time-varying filter characteristics, there is no need to take instability into consideration when designing filter coefficients for a highly stable FIR filter. Very advantageous.

Furthermore, since the word length of the signal in the digital filter is finite, the signal data must necessarily be rounded within the limited word length. Such rounding causes noise, but since the FIR filter does not have a feedback loop, errors due to rounding do not accumulate, which is advantageous in terms of noise countermeasures.

The various characteristics of the FIR filter as described above can be found in, for example, the book rTheory and Applic.
ation of Digital Signal P
rocessingJ (Author: Lawrence,
R, Rabiner; Bernard, Gol
d1 Publisher: Prentice-Hall Inc)
is described in detail.

Next, some features of the adaptive digital filter devices 21 and 22 in this embodiment will be briefly explained in advance.

(f) How to find filter coefficients Filter coefficients are found by analyzing actual musical tones. An example of the procedure for determining filter coefficients is shown in the 10th example.
To explain with reference to the figure, first, two types of musical sound waveforms (original musical sound waveforms) representing different tones are prepared by sampling natural musical instrument sounds. For example, original music sound waveform 1 is a waveform of a piano sound played with a strong key touch, and original music sound waveform 2 is a waveform of a piano sound played with a weak key touch. Next, fast Fourier transform is performed to obtain the original sound waveform 1.
Analyze the Fourier components of 2, and based on this, both waveforms 1 and 2
Find the spectral characteristics of. Next, the difference in the spectral characteristics of waveforms 1 and 2 is determined. Next, the spectral characteristics of the difference are quantized, and the filter coefficients are determined based on the quantized characteristics.The finally determined filter coefficients are stored in the memory.

Filter coefficients that realize time-varying filter characteristics are stored in the dynamic control parameter memory 26 (Figure 2), and filter coefficients that realize steady filter characteristics that do not change over time are stored in the ADFs 22 and 22 (Figure 2). ) is stored in the parameter memory.

The reason for determining the filter coefficients based on the spectral characteristics of the difference between the two waveforms is that the tone generator 18 (Fig. 2) generates a musical tone signal corresponding to one of the original musical waveforms (for example, a waveform corresponding to a strong key touch). This is to obtain a musical tone signal corresponding to the other original musical sound waveform (for example, a waveform corresponding to a weak touch) by applying filtering according to the spectral characteristics of the difference.

When performing filtering according to key touches, instead of preparing sets of filter coefficients corresponding to all stages of key touch strength, only sets of filter coefficients corresponding to some stages are prepared. The filter coefficient corresponding to the key touch strength for which no preparation has been made may be obtained by interpolation similar to that described above.

Of course, not only filter coefficients corresponding to key touches but also filter coefficients corresponding to pitches (or ranges), timbre types, and other various factors are prepared using the same method as described above.

(g) Filter calculation in synchronization with pitch The filter calculation timing for each sample point in ADFs 21 and 22 (FIG. 2) is set by pitch synchronization signals PS1 and PS2. This means that the unit time delay (2-1 in FIG. 5) in the filter calculation is set by the pitch synchronization signals Psi and PS2. That is, the sampling frequency fs in the filter calculation is set by the pitch synchronization signals Psi and PS2.

Specifically, the pitch synchronization signal P corresponding to each pitch name G-F#
Since the frequencies of si and PS2 are the same as the effective sampling frequency fe shown in Table 1 above, the sampling frequency fs of the filter calculation in ADF21 and 22 is determined according to the pitch name of the input musical tone signal. The difference will be as shown in . The sampling frequency fs in the filter operation changes as the sampling frequency fs changes depending on the note name, as is clear from the ω = 2π in the frequency response characteristics shown in Figures 8 and 9. The frequency corresponding to ω=2π in the response characteristic also changes accordingly, and the obtained filter characteristic becomes a moving formant characteristic. Such moving formant characteristics are very suitable for controlling the timbre of musical tone signals.

On the other hand, if the sampling frequency in filter calculation is constant regardless of the pitch of the input signal, the obtained filter characteristic will be a fixed formant.

(h) Pitch synchronous/asynchronous switching As mentioned above, a moving formant filter is suitable for controlling the timbre of musical sounds, but a fixed formant filter may be more desirable depending on the timbre or effect to be obtained. Furthermore, a fixed formant filter is also preferable when the pitch vent operator 13 (FIG. 2) is operated to largely slide the pitch of the generated sound. for that,
The ADFs 21 and 22 of this embodiment are designed to allow switching between pitch-synchronous and asynchronous filter calculations. Also, such pitch synchronization/
The asynchronous switching is not uniform for all channels, and pitch synchronization or asynchronous switching can be independently specified for each channel.

Incidentally, the reason why a fixed formant filter is preferable during pitch bend operation is as follows. Pitch control by the pitch vent operator 13 is capable of not only slight pitch deviation control but also large pitch slide control over several pitches.

In that case, pitch control may be applied across the octave boundary of pitch name G-F# shown in Table 1 above. At this time, if filter calculations are performed in synchronization with the pitch, the sampling frequency fs will change rapidly, and the cutoff frequency will also change rapidly (because the formant is a moving formant), resulting in an unnatural timbre change. For example, the pitch bend operation changes the sound being produced from F#5 to 0.
If you slide to 5 notes, the sampling frequency will be 4.
In the case of a moving formant that fluctuates rapidly from 7.359 kHz to 25.088 kHz (see Table 1 above),
The cut frequency also changes rapidly by the same amount as the difference. To prevent such inconvenience, it is preferable to use a fixed formant (filter calculation asynchronous to pitch) instead of a moving formant (filter calculation synchronized with pitch) during pitch bend operation. In the case of pitch asynchronous filter calculation, the sampling frequency of the filter calculation in ADFs 21 and 22 is 50 kHz in the example of FIG. 3.

(i) Switching the filter order according to dynamic/static mode As mentioned above, in the dynamic mode, dynamic control is performed from the dynamic control parameter memory 26 (FIG. 2) under the control of the microcomputer 14 in real time at the time of sound generation. The parameter data must be read out and transferred to the inside of the ADF21.22. Therefore, if there is a limit on data transfer time and there are many orders of filter coefficients, there is a possibility that filter coefficient parameter data of all orders cannot be transferred within the limited time.

Therefore, the filter order in the dynamic mode must be a limited order commensurate with the real-time data transfer time.

On the other hand, in the static mode, there is no need to change the filter coefficients during sound generation, so there is no such problem.

Moreover, it is preferable to have a larger filter order because it is possible to realize finer filter characteristics. Therefore, in the static mode, the filter order is made sufficiently large.

For the above reasons, the specifications of this embodiment are such that the filter order is switched depending on whether the mode is dynamic mode or static mode. For example, the filter order in static mode is 32nd (however, this applies to even-order characteristics; it is 31st in case of odd-order characteristics), and the filter order in dynamic mode is half that, 16th ( (15th order in the case of odd-order characteristics).

(j) Weighting control of filter coefficients The binary digital data format of one filter coefficient is 1
It consists of a 2-bit filter coefficient data section and a 3-bit weighting data section. The 3-bit weighting data section indicates one of six shift amounts: 0, +1, +2, +3, +4, and +5 bits, and the filter coefficient data section is set according to this shift amount. are shifted and their weights are determined. By performing weighting control that can shift the 12-bit filter coefficient data portion by up to 5 bits, the dynamic range of the filter coefficients is substantially expanded to 17 bits. This type of weighting control ensures a sufficient dynamic range while
Since the number of bits of the filter coefficient to be stored in the memory is small, it helps to save the capacity of the filter coefficient memory.

Overall explanation of adaptive digital filter〉Part 11
The figure is a block diagram schematically showing an example of the internal configuration of an adaptive digital filter device (ADF) 21 corresponding to the first to eighth channels, and the other ADF 22 can be configured in exactly the same manner.

The input interface 38 is connected to the tone generator 18 (
It accepts the pitch synchronization signal PS1 from FIG.
A detailed example thereof is shown in FIG.

The timing signal generation circuit 39 generates timing signals that control various operations inside the ADF 21, and also performs various calculations necessary for filter calculation operations based on the signal corresponding to the pitch synchronization signal of each channel provided from the input interface 38. It generates a timing signal, a detailed example of which is shown in FIG. As will be described later, since the filter calculation for each channel is performed in a time-division manner, the timing signal generation circuit 39 provides a timing signal for controlling the filter calculation operation for each channel at an appropriate timing. .

State memory 40.42 and multiplier and accumulator section 41.43 are digital filter circuits that perform filter operations of the FIR filter. A digital filter circuit (referred to as an A-series digital filter circuit) consisting of a state memory 40, a multiplier and an accumulator section 41 is connected to the first to fourth channels (Chi to Ch).
4) The digital filter circuit (this is referred to as a B-series digital filter circuit) consisting of the state memory 42, multiplier, and accumulator section 43 performs the filter calculation of the fifth to eighth channels (Ch5 to chs). This is what we do. The digital filter circuits of each series A and B are configured to time-divisionally perform filter calculations for four channels. The reason why the filter calculations for the first to eighth channels are divided into two series A and B is due to circuit design reasons. State memories 40 and 42 store digital musical tone signal sample value data TD given from tone generator 18 (FIG. 2).
K in synchronization with the pitch synchronization signal PS1, and the pitch synchronization signal PS1 is taken in by the number of stages corresponding to a predetermined filter order.
6 multiplier and accumulator sections 41.4 corresponding to the set of unit delay elements z-1 in the FIR filter basic circuit shown in FIG.
3 multiplies the digital musical tone signal sample value data delayed by the state memories 40 and 42 by the filter coefficient of the order corresponding to the delay order, and accumulates and totals the multiplication results of each order. This corresponds to the multiplication element and addition element in the FIR filter basic circuit shown in FIG. A detailed example of the A-series state memory 40 and multiplier/accumulator section 41 is shown in FIG. 14, and the B-series state memory 40 can be configured in the same manner.

The microcomputer interface 44 is connected to my computer 1.
4 (FIG. 2) under the control of the data and address bus 28.
It accepts various data given through the ADF 21 and supplies it to each circuit within the ADF 21. This interface 4
The types of data accepted via 4 are as follows:

Key code KC: Indicates the key assigned to each channel.

Key-on pulse KONP: The signal RI I+ is generated only once at the beginning of pressing the key assigned to each channel.

Touch code TCH: Indicates the strength of the touch when suppressing the key assigned to each channel.

Tone color code vN: Indicates the tone type (voice) selected for the key assigned to each channel.

The above-mentioned KC, KONP, TCH, and VN are output from the interface 44 in a time-division multiplexed state according to predetermined time-division timing, and are output from the parameter processing unit (sometimes referred to as PPU) 4.
given to 5.

Pitch synchronous/asynchronous designation signal PASY: This AD
This signal specifies whether the digital filter operation in F21 is performed in pitch synchronization or asynchronous manner. This signal PASY can also be given to each channel in a time-division manner, and pitch synchronization/asynchronous control of filter calculation can be performed independently for each channel. This signal PASY is generated depending on the selected tone type, the operation content of the pitch bend operator 13 (FIG. 2), or the operation state of a dedicated or appropriate operator, etc., and is transmitted to the interface via the bus 28. 44. The pitch synchronization/asynchronous designation signal PASY output from the interface 44 is given to the input interface 38, and is used to control whether or not the input interface 38 should generate a signal according to the pitch synchronization signal PS1. Ru.

Dynamic filter parameter DPR: A filter parameter (filter coefficient) read out from the dynamic control parameter memory 26 (FIG. 2) under the control of the microcomputer 14. As described above, the contents of this dynamic mode filter parameter DPR change with the passage of time during sound generation. The data format of this dynamic mode filter parameter DPR also consists of a 12-bit filter coefficient data section and a 3-bit weighting data section, as described above.

Contains data that identifies whether the order is even or odd. In addition, as mentioned above, this dynamic mode filter parameter DPR
One set of orders is 16th (or 15th). Furthermore, as is clear from the above, due to the symmetry of the filter coefficients in the linear phase characteristic, the set of dynamic mode filter parameters DPR to be actually prepared only needs to be for the 8th order.

Dynamic/static selection signal DS=a signal generated in response to the operation of the dynamic/static selection switch 27 (FIG. 2).

Indicates whether the filter calculation is to be performed in the above-mentioned dynamic mode or static mode.

The above DPR and DS are given to the parameter selector 46 from the interface 44.

The parameter storage 47 stores filter parameters (filter coefficients) for the static mode.

The parameter processing unit 45 serves to read filter parameters for static mode from the parameter memory 47. That is, when the key-on pulse KONP is given, the address of the parameter memory 47 to be read is calculated based on the contents of the tone code VN, touch code TCH, and morning code KC, and the filter parameter stored at this address is read out from the memory. Read from 47. The read static mode filter parameter SPR is given to the parameter selector 46. The data format of this static mode filter parameter SPR is also the same as that of the above-mentioned DPR.

Furthermore, as described above, the order of the set of static mode filter parameters SPR is 32nd (or 31st). Furthermore, as is clear from the above, due to the symmetry of the filter coefficients in the linear phase characteristic, the actually prepared set of static mode filter parameters SPR is 1.
Only the 6th order is enough.

The parameter selector 46 selects a filter parameter DPR for dynamic mode or static mode according to the content of the dynamic/static selection signal DS.
Select one of the SPHs.

The selected parameters are input to A-series and B-series parameter supply circuits 48 and 49. The A-series parameter supply circuit 48 receives the filter parameters DPR or SPR of the first to fourth channels, stores them, and supplies them to the state memory 40 and the multiplier and accumulator section 41 in synchronization with the filter operation timing. . The B-series parameter supply circuit 49 performs similar operations for the filter parameters of the fifth to eighth channels.

The filter parameter SPR for static mode is
It is read out from the parameter memory 47 only once at the beginning of the key press, and thereafter stored in the parameter supply circuits 48 and 49. Therefore, in the static mode, the filter coefficients do not change during the sound generation period, and constant filter characteristics are maintained. On the other hand, the filter parameters DPR for the dynamic mode are stored in the parameter supply circuits 48 and 49 until new parameters are given via the microcomputer interface 44, and the stored contents are updated every time the contents of the parameters DPR change over time. be rewritten as .

Odd/even identification data EOAI to EOA4. which identifies whether the order is even or odd among the filter parameters output from the parameter supply circuits 48, 49. EOBI to EOB4 are given to the state memory 40.42, and filter coefficient data section C0
EA, C0EB and weighting data sections WEIA, WEI
B is provided to a multiplier and accumulator section 41.43. Note that the suffix A or B in the symbols in Figure 1 indicates the distinction between the A series and the B series. Data EOAI~E○A4
．． EOBI to EOB4 are given in parallel for each channel, but data C0EA, C0EB, WEIA,
WEIB is provided for each channel in a time-division manner.

Parameter processing unit 45. A detailed example of the parameter selector 46, parameter memory 47, and parameter supply circuits 48 and 49 is shown in FIG.

The pitch synchronization output circuit 50 is a circuit that inputs the filtered musical tone signal sample value data of each channel output from the multiplier and accumulator sections 41 and 43, and resamples them at a timing synchronized with each pitch. . The signal used for sampling control here is given from the input interface 38. This is the pitch synchronization signal PSID, which is the pitch synchronization signal PS1 of each channel delayed by a predetermined time. For pitch-synchronized resampling, a delayed pitch synchronization signal P
The reason for using SID is to match the time delay of the musical tone signal of each channel in the digital filter calculation at the previous stage. This process of resampling the digital filter output signal in synchronization with its pitch harmonizes the sampling frequency with the pitch of the musical tone, thereby solving the problem of aliasing noise. When performing digital filter calculations in synchronization with the pitch, the digital filter output signal has a sampling period synchronized with the pitch, so pitch synchronization can be achieved even if the pitch synchronization output circuit 50 is not particularly provided. When digital filter calculations are performed asynchronously with each other, a pitch synchronization output circuit 50 is required to achieve pitch synchronization. A detailed example of the pitch synchronization output circuit 50 is shown in FIG.

Next, detailed examples of each part of the adaptive digital filter device 21 will be explained.

In each figure, circuits with numbers and letters such as rlDJ-"8D" in the blocks are delay circuits or shift registers, and the preceding number indicates the number of delay stages or stages. In addition, in the delay circuit or shift register block, if it is not shown that the delay control clock pulse or shift control clock pulse is inputted, the delay or shift control is performed by the master clock pulse φ (see Fig. 3). Ru.

Input Interface 38: FIG. 12 In FIG. 12, pitch synchronization signal PS1 is input to shift register 53 via OR circuits 51 and 52. As shown in Figure 3, this pitch synchronization signal PS1 is time-division multiplexed for 8 channels, with 8 time slots as one cycle, and corresponds to each channel at a period synchronized with the pitch of the key assigned to that channel. The output of the shift register 53 is returned to the input side via the AND circuit 54 and the OR circuit 52, and the pitch synchronization signal PS1 for 8 channels is generated in the 8-stage shift register 53. Eight latch circuits 55 corresponding to each channel are provided in parallel, and the pitch synchronization signal output from the shift register 53 is input in parallel to the data input. The latch control of the latch circuit 55 is performed by a latch timing signal φFSI (25) corresponding to each channel.

φFS2 (29), . . . φFS8 (56) appear as inputs, respectively. The number written next to φFS indicates the channel number, and the number in parentheses after that indicates one calculation cycle (
The latch timing signal indicates the time slot number in the 64 time slots shown in FIG.
”. For example, the signal φFSL (25) becomes a signal “1” in time slot 25, which corresponds to the first channel. As is clear from FIG. 3, time slot 25 is a pitch synchronization signal. 1st in PS1
It supports time division timing of channels. Therefore, the latch circuit 55 that is latch-controlled by this signal φFSI (25) has the content of the pitch synchronization signal PS1 of channel 1 (signal "1" at the timing synchronized with the pitch, signal "0" at other timings). ) is latched.

The same goes for the other channels 2 to 8, and the pitch synchronization signals of each channel are latched in parallel in the latch circuits 55 at predetermined timings.

Note that the latch timing signal φ corresponding to each channel
FS1 (25) to φFS8 (56) are generated from the decoder 56 of FIG. The decoder 56 is the counter 5
7 to generate various types of timing signals. Counter 57 is a modulo 64 counter that counts master clock pulses φ, and is periodically reset by system synchronization pulse 5YNC (FIG. 3). It will be clear from the display in FIG. 13 in which time slots the latch timing signals φFSL (25) to φFS8 (56) corresponding to channels 1 to 8 are generated.

Returning to FIG. 12, each timing signal φFSL(25)~
φFS8 (56) is multiplexed and inverted by a NOR circuit 58. The output of the NOR circuit 58 is input to the AND circuit 54. As a result, the memory in the shift register 53 regarding the channel that has been loaded into the latch circuit 55 is cleared.

On the other hand, the signal "1" is latched by the latch circuit 55 corresponding to the channel in which the pitch synchronization signal PS1 is "1".
are held until the corresponding latch timing signals φFSI (25) to φFS8 (56) are generated in the next cycle. In this way, the latch circuit 55 receives 64 signals corresponding to the channels for which the pitch synchronization signal PS1 is 1''.
The signal it 1 tp is held for a time corresponding to the time slot.

The output of the latch circuit 55 corresponding to each channel is applied to the timing signal generation circuit 39 of FIG. 13 as filter operation request signals φF1 to φF8.

As described later, these filter operation request signals φF1 to φ
When F8 becomes 1", the filter operation for one sample point is executed. Only when the pitch synchronization signal PS1 is generated, the filter operation request signals φF1 to φF8 become 11117, so that the musical tone signal to be filtered is Digital filter calculations are performed in synchronization with the pitch of .

For example, as shown in FIG. 17, if the pitch synchronization signal PS1 becomes "1" at time slot 9 (
In this case, this signal 1 (1jl is the pitch synchronization signal of channel 1) is cyclically held in the shift register 53, and in the time slot 25, the timing signal φFSL
When (25) occurs, it is latched by the latch circuit 55,
Filter operation request signal φF1 corresponding to channel 1 rises to "1" in time slot 25. This signal φF1 is applied to the time slot 24 of the next cycle.Timing signal generation circuit 39: FIG. 13 In FIG.
In addition to the counter 57, an arithmetic timing generation circuit 39 generates a timing signal for controlling the filter arithmetic operation in response to the filter arithmetic request signals φF1 to φF8 of each channel applied from the input interface 38 in FIG.
1 to 398 for each channel (Chi to chs). In the figure, only the circuit 391 of channel 1 is shown in detail, but the circuits 392 to 398 of other channels 2 to 8 have the same configuration, and the timing signal T input thereto is
(33), T (49).

The only difference is the time relationship between... Timing signal T (3
3), T(49), . . . are generated from the decoder 56. Similarly to the above, the number in parentheses in the code indicating the timing signal corresponds to one operation cycle (64 cycles shown in Figure 3).
This indicates the time slot number in the time slot (time slot), and indicates that the timing signal becomes ``1'' in the time slot corresponding to the time slot number. The same applies to other timing signals generated from the decoder 56, and by referring to the numbers in parentheses, it can be easily determined in which time slot the timing signal is generated (in which case it is 1"). For example, The timing signal T(33) is a signal "1" in the time slot 33 as shown in FIG.
-18) is the signal “
1”.

To explain the calculation timing signal generation circuit 391 of channel 1, the filter calculation request signal φF1 and the timing signal T(33) are applied to the AND circuit 59. Therefore, if it is required to perform a filter calculation operation, the AND circuit 5
The output of 9 becomes "1". The output signal of this AND circuit 59 and a signal obtained by delaying this signal by one time slot in a delay circuit 60 are applied to an OR circuit 61. The output of this OR circuit 61 is used as a filter data sampling clock signal RLAI to control the unit delay in the digital filter circuit.

This signal RLA3 becomes "1" in time slots 33 and 34 as shown in FIG.

The AND circuit 62 is supplied with a signal obtained by inverting the output of the AND circuit 59 and the even/odd identification data EOAI of channel 1 (which is output from the parameter supply circuit 48 in FIG. 11) by an inverter 63. This data E
OAI is a signal "1" when the order of the filter characteristic to be achieved is an even number, and a signal "1" when the order is an odd number.
#l. The output of the AND circuit 62 is delayed by two time slots in the delay circuit 64, and the input signal INHA1 is delayed by two time slots.
is output as When the filter order is an odd number, the output signal of the AND circuit 62 is rr I I in the time slot 33
F, and time slot 3 after 2 time slots
5, the signal INHA1 becomes 1'' (see Figure 17).
. If the filter order is even, the signal INHA1 is always “
0''. This input signal INHA1 is used to realize odd-order filter characteristics by prohibiting the highest even-order (32nd order) calculation in the calculation operation of the digital filter circuit.

Timing signals T(3-18) and T(35-50) are input to an OR circuit 65, and the output thereof and the output of the AND circuit 59 are input to an OR circuit 66. The output of the OR circuit 66 is delayed by one time slot in the delay circuit 67 and output as the first shift clock signal φFFAl (see FIG. 17). Also.

A signal obtained by inverting the output of the OR circuit 66 and the output of the delay circuit 64 by an inverter 68 is applied to an AND circuit 69.
A signal obtained by delaying the output by one time slot in delay circuit 7o is output as second shift clock signal φFLAI (see FIG. 17).

The signal φFLAI is 111 I+ at time slot 36 if the filter order is even, but r
e On. These shift clock signals φFFA
l, φFLAI is for sequentially shifting musical tone signal sample value data corresponding to each delay stage in the state memory 40 (FIG. 11) in order to time-divisionally perform arithmetic operations for each order in the digital filter circuit. used for.

The multiplication timing signal PDOAI (see FIG. 17), which becomes "1" between time slots 35 and 50 in accordance with the timing signal T (35-50), is used to combine the musical tone signal sample value data and the filter coefficient in the digital filter circuit. This indicates the period during which multiplication should be performed.

Timing signals T (49), T (19-34) used in the calculation timing signal generation circuits 392 to 394 corresponding to other channels 2 to 4 in the A series
, T (51-2), ... are the channel 1 timing signals T (33), T (3-18), T (35-
50) are sequentially shifted by 16 time slots. Therefore, signals RLA2 to PDOA2 . . . . RLA4 to PDOA4 are generated sequentially at timings shifted by 16 time slots from the circuits 392 to 394 of other channels 2 to 4, respectively. Based on this, the A-series digital filter circuit (
In particular, in the multiplier and accumulator section 41), filter calculation operations for four channels 1 to 4 can be performed in a time-sharing manner in a time interval of every 16 time slots during one calculation cycle = 64 time slots. It has become.

In the calculation timing signal generation circuits 395 to 398 corresponding to each channel 5 to 8 of the B series, the timing signal T (49) is also generated at a predetermined timing shifted by 16 time slots between each channel.

T (19-34), T (51-2), . . . are used, and various signals RLB 1 to PDOB 1° . . . RLB 4 to PDOB 4 similar to those described above are generated.

Operation timing signal generation circuit 391 corresponding to A series
Each signal RLAI-PDOA4 generated in circuit 394 is given to the state memory 40 of the A series, and each signal RLB1-P generated in circuits 395-398 corresponding to the B series
DOB4 is applied to the B-series state memory 42 (FIG. 11).

State memory 40: Fig. 14 In Fig. 14, the state memory 40 of the A series is the state memory 40 corresponding to each channel 1 to 4 of the A series.
1 to 404 in parallel.

Although the details of only the state memory 401 of channel 1 are shown, the state memories 402 to 4 of other channels 2 to 4 are shown in detail.
04 also has the same configuration, but the signals input thereto are different. Each of the signals RLAI to PDOA1 . ...RLA4
~PDOA4 are input to state memories 401 to 404 corresponding to their own channels, respectively.

Before explaining the details of the state memory 40 and the multiplier and accumulator section 41 shown in the figure, the basic operation of the digital filter circuit consisting of these circuits will be explained in the 18th section.
This will be explained with reference to the diagram shown in FIG.

Basic operation of even-order filter operation: Fig. 18〉 Fig. 18 shows the even-order (32nd
This is a schematic diagram for explaining the basic operation of FIR type filter operation when realizing the filter characteristics consisting of (
(a) is a block diagram, (b) is each stage Q of shift registers SRI and SR2 in (a) at each calculation timing.
The state of the musical tone signal sample values in O to Q15 and Q16 to Q31 is shown.

The first shift register SRI has 16 stages, and digital musical tone signal sample value data Xn to be filtered is inputted via a selector 5ELL. The above-mentioned filter data sampling clock signal RLA (RLAI in the case of channel 1) is used as the signal for taking in new sample value data 1 shift clock signal φFFA (for channel 1, φFFA
1) is used. Each stage QO-Q15 of the first shift register SRI holds 16 sample value data XnNXn-zs from sample points n to n-15. The output of the final stage of this shift register SRI is returned to the first stage via selector 5ELL when there is no sampling clock signal RLA. This shift register SRI is shifted only in the right direction.

The second shift register SR2 also has 16 stages, and the output of the first shift register SRI is inputted via the selector 5EL2. The aforementioned filter data sampling clock signal RLA is used as a signal for taking in the output of SRI into SR2 via selector 5EL2,
The shift clock pulse of SR2 is the second shift clock signal φFLA (for channel 1, φ
FLAI) is used. This second shift register S
Each stage Q16 to Q31 of R2 holds 16 sample value data Xn-□, ~xi-, □ from sample point n-16 to n-31.

The final stage Q31 of the shift register SR2 is connected to the first stage Q16 via the selector 5EL2 when there is no sampling clock signal RLA. This shift register SR2 is of a bidirectional shift type, and when the sampling clock signal RLA is it II I+, it is in the right shift mode, and when it is in the right shift mode u Q PI, it is in the left shift mode.

Stages Q15 and Q of shift registers SRI and SR・2
The outputs of 16 are added by an adder ADD, and the addition result is given to a multiplier MUL, where it is multiplied by a filter coefficient C0EA. The multiplication results are given to an accumulator ACC, where the multiplication results for all orders are accumulated. In this way, the filter calculation result for one sample point is output from the accumulator ACC.

Adder ADD adds sample value data for two sample points, and a common filter coefficient C0EA is added to multiplier MU.
The reason for multiplying by L is the above-mentioned "symmetry of filter coefficients"
by. In other words, since two symmetrical sample value data are multiplied by the same filter coefficient, instead of multiplying them separately, they are added together and then multiplied once to multiply both sample value data by the coefficient. I try to do them at the same time.

In FIG. 18(b), the calculation timing of the vertical axis advances every time slot according to the master clock. The numbers shown therein indicate the order for convenience and do not absolutely indicate the time slot number within one operation cycle (64 time slots). In the illustrated example, at calculation timing 1, χ is applied to each stage QO to Q31 of shift registers SRI and SR2. It contains sample value data for 32 sample points from Xn-3x.

In the illustrated example, it is assumed that the sampling clock signal RLA becomes "1" at calculation timing 2. As a result, shift registers SR1 and SR2 are shifted to the right by one stage in response to shift clock signals φFFA and φFLA, and at calculation timing 2, the state as shown in the figure is achieved. In the case of channel 1, the shift clock signals φFFA and φFLA at this time are φFFAl and φFLA in FIG.
As shown in column 1, this occurs in time slot 34. As is clear from the figure, the shift clock signals φFFA and φFLA are not generated in the first time slot, and therefore the state of each stage QO-031 does not change at calculation timing 3 in FIG. 18(b). However, the 16 time slot width from calculation timing 3 to 18 is the multiplication timing signal PDOAI (
FIG. 17) corresponds to time slots 35 to 50 in which multiplication and accumulation occur.

In other words, at calculation timing 3, stages Q15 and Q1
The sample value data of
is maintained.

From calculation timing 4 to 18, the first shift register SRI shifts to the right, and the second shift register SRI shifts to the right every time slot.
The shift register SR2 of is shifted to the left, and each stage Q
The state of O-Q31 changes sequentially as shown. Therefore, at calculation timing 4, Xn-0a and Xfi-t are added, and this is multiplied by the 15th filter coefficient,
The result is accumulated in accumulator ACC. At the next calculation timing 5, similar calculations are performed for X n-tz and Xi-□, and similar filter coefficient calculations are performed sequentially and time-divisionally for the two sample value data at symmetrical positions, and at calculation timing 18, Similar calculations are performed for Xn and Xn-30 at the last symmetrical position, and the filter calculations for all orders are completed. At the next calculation timing 19, the shift is performed once again, and as shown in the figure, the sample value data x net to X n-3° are arranged in the order of time delayed by each stage QO-Q31.

Basic operation of odd-order filter operation: Figure 19 Figure 19 is a schematic diagram for explaining the basic operation of FIR-type filter operation when realizing odd-order (31st order) filter characteristics. (a) is a block diagram, (b) is the shift register SR1, SR of (a) at each calculation timing
2 each stage QO~Q15. The state of the musical tone signal sample values of Q16 to Q3'O is shown.

Each block in (a) is the same as that shown in FIG. 18(a), except that the output of stage Q16 is applied to adder ADD via gate GT. The gate GT is controlled by a signal obtained by inverting the inhibit signal INHA (INHAl in the first channel), and when the signal INHA is "1", the output signal of the stage Q16 is applied to the adder A'DD. prohibited. In addition, the second shift register SR
2, the 16th stage Q31 is not used, and the 15th stage Q30 and the first stage Q16 are connected via the selector 5EL2.

In (b), the state change of the first shift register SRI is the same as in FIG. 18(b). 2nd shift register S
The state change of R2 is slightly different from that shown in FIG. 18 (even order case). The shift clock signal ψFLA of the second shift register SR2 is "1" in the even-order mode at calculation timing 4, but becomes "0" in the odd-order mode (in the case of channel 1, the shift clock signal ψFLA of φFLAI in FIG. 17 is (See time slot 36 in column). Therefore, in odd-order mode, the first
As shown in FIG. 9(b), the second shift register SR2
The contents of are not shifted at calculation timing 4, but are sequentially shifted to the left between calculation timings 5 and 19.

At calculation timing 3, shift register SRI.

Each stage QO to Q30 of SR2 contains musical tone signal sample values Xn+i to xy1. corresponding to each of the 31st delay stages. s
are entered in order, and the sample value xyl-2 of the center order is entered in stage Q15. As shown in FIG. 6, unique filter coefficients are assigned to the orders located at the center of the symmetry of the odd-order modes. Therefore, at calculation timing 3, the output of stage Q16 is inhibited by the inhibit signal INHA,
Only the output signal of the stage Q15 corresponding to the central order is applied to the adder ADD, and multiplied by a unique filter coefficient corresponding to the central order in the multiplier MUL.

At operation timing 4, only the first shift register SRI is shifted to the right, and the second shift register SR2 is not shifted. Therefore, stage Q15 contains xn-, , and stage Q16 contains xi-, s. In addition, the inhibit signal INHA becomes LL O71, and the gate G
T is opened. In this way, the sample values Xn-xa+xyl-,, corresponding to the orders on both sides of the central order, are sent to the adder AD.
D and are added together, and both are multiplied by a common filter coefficient in multiplier MUL.

At calculation timings 5 to 18, SR1 is sequentially shifted to the right, and S
R2 is sequentially shifted to the left, and the sample values at symmetrical positions as shown are transferred to stage Q15. Enter Q16, where both are added and multiplied by a common filter coefficient.

Digital Filter Circuit: Fig. 14> The state memory 401 corresponding to channel 1 will be explained with reference to Fig. 14. 16-stage single-sided shift register 7
1 is the first shift register SRI in FIGS. 18 and 19.
, and is shifted and controlled by the first shift clock signal φFFAl corresponding to channel 1. The digital tone signal sample value data TDX supplied from the tone generator 18 (FIG. 2) is input to the latch circuit 73, and the sample value data of channel 1 is taken into the latch circuit 73 in accordance with the latch timing signal XLDAI.

The latch timing signal XLDA corresponding to each channel 1 to 8 corresponds to the time division timing of each channel in the musical tone signal sample value data TDX (see FIG. 3).
I~XLDA4. XLDBI-XLDB4 are generated from decoder 56 (FIG. 13). As mentioned above, the first
The number in parentheses at the end of each signal display in FIG. 3 indicates the time slot number in which that signal occurs. A latch circuit similar to latch circuit 73 is provided in the state memory corresponding to each channel, and latch timing signals XLDAI to XLDA4 . XLDBl~XL
The musical tone signal sample value data TDX of each channel 1 to 8 are separately latched by the DB 4 and demultiplexed.

The musical tone signal sample value data of channel 1 latched by the latch circuit 73 is applied to the A input of the selector 74. The selector 74 selects six inputs when the filter data sampling clock signal RLA1 given from the calculation timing signal generation circuit 391 of FIG. 13 is "1",
Otherwise, the output signal of the 16th stage of the shift register 71 which is added to the B input is selected. As mentioned above, this signal RLAI is synchronized with the pitch of the musical tone,
New sample value data (A input) is selected by the selector 74 in synchronization with the pitch, and is provided to the shift register 71. As is clear from FIG. 17, the signal RLAI is a
In the time slot 34 that becomes l u, the shift clock signal φFFAl becomes It I It, so the shift register 71 takes in new sample value data given from the selector 74 into the first stage (QO). As described above, the shift operation is temporarily suspended in the next time slot 35, and the shift operation is sequentially shifted to the right in the following time slots 36 to 51.

The bidirectional shift register 72 is the second one in FIGS. 18 and 19.
This corresponds to shift register SR2. Each stage Q16 to Q31 of this bidirectional shift register 72 has selectors SL1 to 5L16 and a latch circuit L as shown in the figure.
It consists of CI to LC16, which are connected to enable bidirectional shifting. That is, the first stage Q1
The output signal of the final stage (Q15) of the first shift register 71 is input to the A input of the selector SLI No. 6,
Selectors SL2 to 5L for each of the other stages Q17 to Q31
Each of the 16 eight power units has a latch circuit LCI in the previous stage.
~The output of LC15 is input.

In addition, the B inputs of the selectors SLI to 5L16 of each stage are connected to the latch circuits LC2 to LC16, LC of the next stage.
The output of I is input. This allows each selector SLI
When the A input of ~5L16 is selected, the mode becomes the right shift mode, and when the B input is selected, the mode becomes the left shift mode.

A sampling clock signal RLAI is used as a selection signal for each selector SLI to 5L16, and when this is 1'', the A input is selected, that is, the right shift mode is selected.However,
In order to disable stage Q31 when in odd-order mode, selector 5L15 of stage Q30 is somewhat different from the others. In other words, the selector 5L15 is provided with a C input, to which the output signal of the stage Q16 is applied. Odd-even identification data EOAI for channel 1
is “1” (that is, even-order mode), AND circuit 7
51 is enabled and the signal RLA1 is 1'0", the output of the AND circuit 751 becomes the signal "1", which causes the selector 5L15 to select the B input, and the output of the stage Q31 is given to the stage Q30 ( shifted left)
. When EOAI is "0" (odd order mode), AND circuit 761 is enabled, and when signal RLAI is "0", selector 5L15 selects the C input, and the output of stage Q16 is given to stage Q30 (Q31 shifted to the left).

With the above configuration, the first and second shift registers 71
．． The changing state of the contents of 72 is exactly the same as that shown in FIGS. 18(b) and 19(b) depending on whether the mode is an even number mode or an odd number mode.

The output signal of the first stage Q16 of the second shift register 72 is applied to the gate 76 via the gate 75. Gate 75 is controlled by a signal obtained by inverting inhibit signal INHAI, and corresponds to gate GT in FIG. 19. Gate 76 inputs the output signal of first shift register 71 (output signal of stage Q15) and the output signal of second shift register 72 (output signal of stage Q16) given via gate 75, and determines the multiplication timing. It is released by the signal PDOAI (see FIG. 17).

The output of the gate 76 is applied to an adder 77 of the multiplier and accumulator section 41, where the two musical tone signal sample value data are added. This adder 77 corresponds to the adder ADD in FIGS. 18 and 19. Adder 7
The output of 7 is delayed by one time slot in a delay circuit 78 and input to a multiplier 79. The 0 multiplier 79 applies a filter coefficient to the musical tone signal sample value data provided via the delay circuit 78 via a delay circuit 80. This is to multiply data C0EA. The output of the multiplier 79 is sent to the delay circuit 81
The signal is delayed by four time slots and applied to the shifter 82. Weighting data W is input to the shift control input of the shifter 82 via a delay circuit 83 that sets a delay of 5 time slots.
EIA will be given. This multiplier 79 and shifter 82 are
This corresponds to the multiplier MUL in FIGS. 18 and 19.

That is, as mentioned above, the filter coefficient data C0EA is the data of the effective bits of the filter coefficient, and the multiplier 79
In the step, the valid bits of this filter coefficient are multiplied by the musical tone signal sample value data. Then, by shifting this multiplication result by the number of bits corresponding to the value of the weighting data WEIA in the shifter 82, the multiplication of the real number of the filter coefficient and the musical tone signal sample value data is completed.

The output of shifter 82 is given to accumulator 84, and 1
Multiplication results corresponding to each order of the channel are accumulated. The output of the accumulator 84 is the latch circuit 8
5 and is latched in accordance with the operation end timing signal FENDA.

This signal FENDA is generated from decoder 56 of FIG. As shown in the figure, this signal FE
NDA becomes "1" at time slot 8, 24° 40.56. At time slot 56, the operation result of channel 1 is latched, at time slot 8, the operation result of channel 2 is latched, at time slot 24, the operation result of channel 3 is latched, and at time slot 40, the operation result of channel 4 is latched. B-series calculation end timing signal FEN
DB is generated similarly.

The multiplier and accumulate unit 41 is time-divisionally shared by four channels. That is, the adder 77 receives not only the output of the gate 76 of the state memory 401 of channel 1, but also the output of the state memory 401 of channels 2 to 4.
Output signals of gates having similar functions provided in 02 to 404 are multiplexed input. Multiplication timing signals PDOAI-PDOA4 having a width of 16 time slots are input to the output gates 76 of each state memory 401-404 at different timings shifted by 16 time slots. Therefore, the adder 77 has each channel 1 to 1.
4 signals are input in a time division multiplexed manner every 16 time slots. The filter coefficient data C0EA and weighting data WEIA are time-division multiplexed for each 16 time slots at the same timing as described above for the four channels, and from the 1st to the 16th order in the 16 time slots for one channel. data is time-division multiplexed.

The B-series state memory 42 and multiplier/accumulator section 43 also have the same configuration as in FIG. 14, however, the timings of various signals are changed as appropriate.

FIG. 20 shows the timing of filter operation for each channel 1 to 8 in the A-series and B-series digital filter circuits (i.e., state memory 40.42 and multiplier and accumulator section 41.43) as shown in FIG. Shown below. In FIG. 20, the shift 1 column shows the shift timing of the first shift register (71 in the case of channel 1), and the shift 2 column shows the shift timing of the second shift register (72 in the case of channel 1). Indicates shift timing. The direction of the arrow indicates the shift direction (right shift or left shift). The shift timing of each channel is calculated by the calculation timing signal generation circuits 391 to 39.
8 (FIG. 13), the first and second shift clock signals φFFAl to φFFB4, φFLA1 to φF
It corresponds to the timing of occurrence of LB4. Shift operations include shift operations for filter operations and dummy shift operations for refreshing stored data.

For example, in the case of channel 1, shifts in time slots 4 to 19 are dummy shifts. The symbol (←) in the shift 2 column indicates that a left shift is performed in the even-order mode, and that no shift is performed in the odd-order mode.

In FIG. 20, the INH column is the inhibit signal IN.
It shows the timing of occurrence of HA1 to INHB4. In the odd-order mode, the inhibit signals INHA1 to INHB4 become "1" in the time slot marked O.
The PDO column shows the state memory 40.4 of each channel.
2 shows the timing at which musical tone signal sample value data is input to the multiplier and accumulator sections 41 and 43. This is the multiplication timing signal PDOA of each channel.
It corresponds to the generation timing of 1 to PDOB4. SU
The column M shows the output timing of the accumulator 84. The delay of 6 time slots between PDO and SUM timing is due to delay circuit 78.81.
Due to the time slot delay and the 1 time slot delay due to the 7 cumulate rate 84. In the last time slot of the output timing of the accumulator 84, an operation end timing signal FENDA is generated, and the output of the accumulator 84 is taken into the latch circuit 85.

<Parameter memory 47: FIG. 21> FIG. 21 shows an example of the storage format of the parameter memory 47, which consists of a key group table, touch group table, parameter address table, and parameter bank.

Actual filter parameters are stored in a parameter bank, and address data of parameters to be read from the parameter bank is stored in a parameter address table. The key group table stores information for grouping keys in correspondence with each key. - As an example, the number of keys is 88° and the number of groups is 44, and in the key group table, relative address data (referred to as key group address) regarding the key group to which the key belongs is stored in the address position corresponding to each key. Therefore, the key group table is addressed by the key code KC. This key group table is stored at a predetermined absolute address (offset address 0AD) in the parameter memory 47.
The touch group table 6, which occupies the storage area starting from ``S'', stores information for grouping touch intensities corresponding to each level of key touch intensities for each timbre. - As an example, the number of tones is 32, and this touch group table includes 32 timbre-specific areas corresponding to the values 0 to 31 of the timbre code VN, and the stages of touch intensity that can be expressed by the touch code TCH are just one example. 64, and each tone area can be touched from 0 to 6.
It has 64 address locations corresponding to 3.

At the address position corresponding to each touch intensity, relative address data (referred to as touch group address) regarding the touch group to which the touch intensity belongs is stored.

- As an example, the number of touch groups is 16. Therefore, the touch group table is addressed by tone code VN and touch code TCH. This touch group table is stored at a predetermined absolute address (
This occupies a storage area starting from offset address 0AD1). The absolute address data for reading this touch group table is created by combining the upper half of the 6-bit touch code TCH with the 5-bit tone code VN to create 11-bit relative address data (address where offset address OAD 1 is O). death,
It is created by adding this to offset address 0ADI.

The parameter address table is for each key group.
In addition, for each tone color, relative address data (referred to as parameter address) of an address storing a filter parameter corresponding to each touch group is stored. This parameter address table is for each key group 0 to 4.
This key group area includes 44 key group areas corresponding to 3, and this key group area is determined by the key group address read from the above-mentioned key group table.

addressed. Each key group area has tones 0 to 31
The timbre area includes 32 timbre-specific areas corresponding to the timbre code VN. Each timbre area has 16 address positions corresponding to touch groups 0 to 15, and each address position is addressed by a touch group address read from the touch group table described above. Note that a 2-byte storage location is allocated to one address location, and the parameter address data is stored there in 12 bits. This parameter address table occupies a storage area of the parameter memory 47 starting from a predetermined absolute address (this is referred to as an offset address AD2). The absolute address data for reading this parameter address table sets the lowest 1 bit to "'O" or "1" (this is because 1 address position occupies 2 bytes, or 2 absolute addresses), and the upper A 4-bit touch group address data is located, a 5-bit tone code VN is located above it, a 6-bit key group code is located above that, and a total of 16 bits of relative address data (offset address 0AoQ) is created. Create an address (with O as O),
It is created by adding this to offset address 0AD2.

The parameter bank stores, for example, 2620 types of filter parameters, and includes 2620 parameter storage areas corresponding to parameter addresses O to 2619. One parameter storage area includes 32 byte storage locations (32 absolute address locations) and stores parameters corresponding to one set of filter coefficients for 16 orders. The filter coefficients for the first order are stored in a 2-byte storage location, and as mentioned above, the contents include 12-bit filter coefficient data (COE), 3-bit weighting data (WEI), and 1-bit even/odd data. Consists of identification data (EO). However, weighted data (WE
I) and odd-odd discrimination data (E O) are common among each order in one set of parameters, so they are stored only in the first order storage location and not in the storage locations of other orders. However, it is also possible to store the weighting data (WEI) independently for each order. This parameter bank is addressed by the parameter address read from the parameter address table described above. The parameter bank occupies a storage area of the parameter memory 47 starting from a predetermined absolute address (referred to as offset address 0AD3). Absolute address data for reading this parameter bank is created by placing 12-bit parameter address data in the upper 12 bits of 17-bit relative address data (address with offset address 0AD3 as 0). and set this to offset address 0AD
It is created by adding to 3. By sequentially changing the lower 5 bits of this absolute address data in 32 steps.

A set of filter parameters consisting of 16 orders within one parameter storage area specified by the parameter address is sequentially read out.

A hierarchical parameter memory structure as shown in FIG. 21 is advantageous because it saves memory capacity. If we were to individually store filter parameters for all (22,528) combinations of 44 key groups, 32 tones, and 16 touch groups without doing this, a storage capacity of 22,528 x 32 bytes would be required. If you do as shown in Figure 21, you will get 402 bytes, which is the sum of 1408 (=44x32) x 32 bytes of the parameter address table and 2620 x 32 bytes of the parameter bank.
Only 8x32 bytes of storage capacity is required. In other words,
Even if the combinations of key groups, tones, and touch groups are different, the same filter parameters can be used in some cases, so the example in Figure 21 has a structure in which 2,620 types of parameters are shared for 22,528 combinations. This is intended to save memory capacity.

Parameter processing unit 45, parameter selector 46, parameter memory 47, parameter supply circuit 48, 49: FIG. 15 The parameter processing unit 45 controls reading of the parameter memory 47 as described above for the static mode described above. It is something to do. The program memory 451 stores a program that executes read control of the parameter memory 47 as described above. The program counter 452 generates a program step signal PC for reading the program memory 451, and includes an 8-stage shift register 86, an adder 87, a gate 88, 89, and an end detection circuit 9°, and has 8 channels. The counting operation is performed in a time-division manner. The key-on pulse KONP is inverted by an inverter 91 and is added to the gate 88 control circuit. This key-on pulse KONP becomes a signal at 1 y+ at the beginning of a key press, and the pulses corresponding to each channel are time-division multiplexed. Adder 87 receives 1 from gate 89 for the output of shift register 86.
11 jj, and the addition result is sent to gate 8.
8 to a shift register 86. The end detection circuit 9o detects whether the output value of the shift register 86 has reached the final step of the program. If the output value has not reached the final step, it outputs a signal (lO#I) and outputs the signal (lO#I) through the inverter 92. A signal ``1'' is applied to the control input of the gate 89 to instruct the count up by 1.
″′ is provided to adder 87.

When the final step is reached, the signal It I 11 is output, and the signal II O# is applied to the gate 89 via the inverter 92 to close the gate 89 and prevent counting from occurring.

With the above configuration, the contents of the program counter 452, that is, the step signal PC, is reset to "0" when the key-on pulse KONP is generated, and thereafter is incremented by 1 every time the shift register 86 goes around (every 8 time slots). , when the final step is reached, the count is stopped.

- As an example, the number of program steps is 37, and the step signal PC output from the counter 452 changes sequentially from "0" to r36J (last step). The step signal PC is the output of the shift register 86, and eight channels are time-division multiplexed.

The program memory 451 stores the input step signal PC.
Select control signals 5ELC1 to 5ELC according to the steps of
4 and read out the address data for reading the offset address memory 453. The offset address memory 453 has the aforementioned offset address 0A.
It stores values from DS to 0AD3. Offset address data ADOF (one of OADS-OAD3) read from offset address memory 453 is input to adder 454. Adder 454 is selector 45
The relative address data RADD given from 5 and the offset address data ADOF are added, and the output is added to the address input of the parameter memory 47 as address data PRAD.

Key group address register 456, touch group address register 457. The parameter address registers 458 each consist of eight stages of shift registers, and each has key group address data KEYG, touch group address data TCHG, and parameter address data PA.
D is stored in a time-division manner for each channel.

Selectors 93 to 9 are provided on the input side of each register 456 to 458.
5 are provided, and data read from the parameter memory 47 is applied to one input of each selector. The other input of each selector 93-95 has each register 456-95.
458 outputs are added. The selection control signals 5ELC2 to 5ELC4 of the selectors 93 to 95 are stored in the program memory 451.
It controls whether the read output data of the parameter memory 47 is taken into the registers 456 to 458, or whether the data once taken into the registers 456 to 458 is cyclically held. conduct. As is clear, when the aforementioned key group address data is read out from the parameter memory 47, it is stored in the key group address register 45.
6, when the touch group address data mentioned above is read out, it is taken into the touch group address register 457, and when the above-mentioned parameter address data is read out, it is taken into the parameter address register 458. 5ELC2~5E
LC4 is generated.

Address data KEYG, TCHG, and PAD stored in each register 456 to 458 are input to selector 455. The sector 455 contains the key code KC1, the tone code VN, the touch code TCH, the least significant bit PCLSB of the step signal PC output from the program counter 452, and r4 from this step signal PC.
Data PC-4 obtained by subtracting the decimal "1o o"> is also input. Selector 455 selects program memory 4.
Input data is selected in a predetermined combination according to a selection control signal 5ELCI given from 51, and the selected data is positioned at a bit position corresponding to a predetermined weight in relative address data RADD, thus creating relative address data RADD. Output.

The contents of the 37 steps executed in this parameter processing unit 45 are as follows.

When pc=o: Select key code KC by key group table read processing selection control signal 5ELCI, and read offset address 0ADS of the key group table as offset address data ADOF. In addition, the output data of the parameter memory 47 is transferred to the key group address register 4 by the selection control signal 5ELC2.
56.

As a result, the key group address corresponding to the key code KC is read from the key group table of the parameter memory 47 and stored in the register 456.

When PC=1: Tone code VN and touch code T are read by touch group table read processing signal 5ELCI.
Select CH and TCH in the least significant bit.

VN is positioned above it and relative address data RA
Create DD. Offset address 0A of touch group table as offset address data ADOF
Read D1. Further, the output data of the parameter memory 47 is taken into the touch group address register 457 by the signal 5ELC3. As a result, the touch group address corresponding to the tone code VN and touch code TCH is read from the touch group table in the parameter memory 47 and stored in the register 457.

When PC=2.3: Key group address data KE is read by parameter address table read processing signal 5ELCI.
YG, tone code VN, touch group address data TCHG, least significant bit of step signal PC PCLSB
PCLSB, TCHG, V from the least significant bit.
Position the relative address data RA in the order of N and KEYG.
Create DD. Read offset address 0AD2 of the parameter address table as data ADOF.

Further, the output data of the parameter memory 47 is taken into the parameter address register 458 by the signal 5ELC4. As a result, an appropriate parameter address is read from the parameter address table in the parameter memory 47 and stored in the register 458. As mentioned above, one parameter address data consists of 12 bits and is stored in a 2-byte storage location (see FIG. 21). When bit PCLSB is “0” (step pc=2), the lower 8 bits of parameter address data are read, and when PCLSB is “1” (step PC=3), the higher 4 bits of the parameter address data are read. Data is read. The selector 95 allocates bit positions so that this parameter address data is parallelized into 12-bit data and stores it in the register 458.

When PC=4 to 35: Parameter address data PAD by parameter bank read processing signal 5ELCI
The step signal PC-4 subtracted by 4 is selected and positioned in the order of PC-4 and PAD from the least significant bit to create relative address data RADD. Also, the offset address 0AD3 of the parameter bank is read out as data ADOF. The value of the signal PC-4 changes from rOJ to "31" in 32 steps from PC=4 to 35.

Therefore, a set of filter parameters (see FIG. 21) consisting of 32 bytes specified by the parameter address is stored in one set from the parameter bank of the parameter memory 47.
Each byte is read out sequentially.

When PC=36, the nib program counter 452 is stopped and the filter parameter reading sequence is completed.

The filter parameters read from parameter memory 47 are input to timing synchronization circuit 459. This circuit 459 receives the program step signal PC and the timing signal group TSI given from the decoder 56 (FIG. 13) of the timing signal generation circuit 39, and synchronizes the filter parameters of each order to a predetermined timing based on these signals. and output it. The output of this synchronization circuit 459 is the filter parameter SPR for static mode.
is given to six inputs of the parameter selector 46.

The B input of the parameter selector 46 is given the dynamic mode filter parameter DPR output from the microcomputer interface 44 (FIG. 11). The dynamic/static selection signal DS output from the microcomputer interface 44 is applied to the selection control input SB of the selector 4G, and the parameter DPR of the B input is selected in the dynamic mode, and the parameter A is selected in the static mode.
Select the input parameter SPR.

The output of the selector 46 is input to parameter supply circuits 48 and 49 for each of the A and B series. Although a detailed example of only the A-series circuit 48 has been shown, the B-series circuit 49 also has the same configuration. In the parameter supply circuit 49, the distribution circuit 485 takes in the data regarding channels 1 to 4 of the A series from among the parameter data serially applied from the selector 46, parallelizes this for each channel, and also outputs the filter coefficient data C channel 1. Then C0EAI).

The weighting data (WEIAI for channel 1) and the even/odd identification data (EOAI for channel 1) are parallelized separately and stored in storage circuits 481 to 481 corresponding to each channel.
484. For such distribution control, an appropriate timing signal TS2 is sent to the timing signal generation circuit 39.
is generated from the decoder 56 (FIG. 13) of the distribution circuit 4.
85.

A detailed example of the storage circuits 481 to 484 is shown for channel 1, but the same applies to the other channels. 12
The bit filter coefficient data C○EAI is the selector 96.
The signal is inputted to a 16-stage shift register 97 via a 16-stage shift register 97. This filter coefficient data C0EAI is time-division multiplexed with 16 orders of data in 16 time slots, and the 16 orders of data are sent to the shift register 97.
are taken into each stage of The contents of shift register 97 are cyclically held via selector 96.

The 3-bit weighting data WEIAI is sent to the latch circuit 98.
is input. The 1-bit even-odd identification data EOAI is input to the latch circuit 99. The selector 96 and the latch circuits 98 and 99 are controlled at appropriate timing by appropriate control signals (not shown). That is, in the static mode, parameter data for 16 orders read from the parameter memory 47 in response to the start of a key press is sent to the timing synchronization circuit 459 and the selector 46.
, the selector 96 takes in the filter coefficient data C0EAI for the 16th order into the shift register 97 in synchronization with the timing of input to the storage circuit 481 via the distribution circuit 485, and the latch circuit 98.99 takes in the weighting data WE
IA1. Latch the even/odd identification data EOAI. From then on,
The memories in the shift register 97 and latch circuits 98 and 99 are held until a new pressed key is assigned to that channel. On the other hand, in the dynamic mode, selector 4 is selected from microcomputer interface 44 (Fig. 11).
6. In synchronization with the timing at which the dynamic control parameter data DPR for the 8th order is provided via the distribution circuit 485, the filter coefficient data C0EAI for the 8th order of the parameter data DPR is transferred to the shift register 97.
The weighted data WEIAI is loaded into the latch circuit 9.
8, and the even/odd identification data EOAI is sent to the latch circuit 9.
Latch to 9. Thereafter, the shift register 97 . The memories in latch circuits 98 and 99 are retained. Note that in the dynamic mode, the shift register 97
Of the 16 stages, filter coefficient data of dynamic control parameters for the 8th order is stored in 8 stages corresponding to the 9th to 16th orders, and the contents of the 8 stages corresponding to the 1st to 8th orders are set to O. .

The filter coefficient data output from the shift register 97 of each storage circuit 481-484 is given to a selector 486, where data of each channel is sequentially selected according to timing signal TS3 and time division multiplexed. In this way, the filter coefficient data for channels 1 to 4 are time-division multiplexed.

The data is supplied as A-series filter coefficient data C0EA to the A-series multiplier and accumulator section 41 (FIG. 14).

The weighted data output from the latch circuit 98 of each storage circuit 481-484 is given to a selector 487, where the data of each channel is sequentially selected according to the timing signal TS4 and time division multiplexed. Weighting data WEIA of channels 1 to 4 time-division multiplexed in this way
is the A-series multiplier and accumulator section 41 (the 14th
Figure).

Even-odd identification data EOAI-E of each channel 1-4 latched in the latch circuit 99 of each storage circuit 481-484
OA4 stores the state memory 401 of the corresponding channel.
404 (FIG. 14) in parallel.

Pitch synchronous output circuit 50: Fig. 16 In Fig. 16, the B input of the selector 501 receives channels 1 to 4 output from the A-series multiplier and accumulator section 41 (Figs. 11 and 14). Filtered musical tone signal sample value data SMA is provided in a time division multiplexed manner. The timing at which the filtered outputs of each channel 1 to 4 are captured in the latch circuit 85 in FIG. 14 is SU in FIG.
This is the cumulative final time slot (shaded area) in the M column, and the channel timing of the filtered sample value data SMA of each channel 1 to 4 is shown in FIG. 17.

The C input of the selector 501 receives filtered musical tone signal sample value data SMB of channels 5 to 8 output from the B-series multiplier and accumulator section 43 (FIG. 11).
are given in a time-division multiplexed manner.

The channel timing of this data SMB is as shown in FIG.

The output of an eight-stage shift register 502 is given to six inputs of the selector 501, and the output of the selector 501 is input to the shift register 502. This selector 5
01 and shift register 502 are for time-division multiplexing the filtered sample value data of each channel 1 to 8 according to high-speed time-division timing in units of 1 time slot as shown in the channel timing of PSL in FIG. It is. The timing signal LREGLDA from the decoder 56 in FIG.
．． Timing signal IR that becomes “1” at 44.64
EGLDB is generated and this is selected by selector 50 in FIG.
1 is applied to B selection control input SB and C selection control input SC. As a result, of the data SMA given to the B input, the data of channel 1 is selected at time slot 57 (this corresponds to the timing of channel 1 among the channel timings of PSL shown in FIG. 3), and the data of channel 2 The data is in time slot 13 (P in Figure 3).
SL channel 2 timing), and channel 3 data is selected at time slot 26 (PSl timing in FIG. 3).
The data of channel 4 is selected at time slot 46 (timing of channel 4 of PS1 in FIG. 3). Also, among the data SMB given to the C input, data on channel 5 is selected at time slot 11 (timing of channel 5 of PSl in FIG. 3), and data on channel 6 is selected at time slot 31 (timing of channel 5 of PSl in FIG. 3). Channel 7 data is selected at time slot 44 (timing of channel 7 of PSL in FIG. 3), data of channel 8 is selected at time slot 64 (timing of channel 7 of PSL in FIG. 8 timing)).

A signal obtained by inverting the timing signals IREGLDA and IREGLDB by a NOR circuit 503 is applied to the A selection control manual SA of the selector 501. Therefore, the filtered sample value data of each channel taken into the shift register 502 at each of the above-mentioned timings is cyclically held in the shift register 502 at other timings.

The output of the shift register 502 is given to the A input of the selector 504. The output of selector 504 is input to an 8-stage shift register 505.

The output of the shift register 505 is returned to the input side via the B input of the selector 504. The selector 504 and shift register 505 are for resampling the output musical tone signal of the digital filter in synchronization with its pitch. A delayed pitch synchronization signal PSID applied from the input interface 38 (FIG. 12) is inputted to the A selection control manual SA of the selector 5.4 through an eight time slot delay circuit 506.

In FIG. 12, the pitch synchronization signal PS1 is output from the OR circuit 5.
1 to a 64-stage shift register 100. The pitch synchronization signal delayed by 24 time slots by this shift register 100 is input to an AND circuit 101, the signal delayed by 40 time slots is input to an AND circuit 102, and the signal delayed by 48 time slots is input to an AND circuit 103. and is delayed by 64 time slots and input to the AND circuit 104.

The other inputs of each AND circuit 101 to 104 include a timing signal PSSI generated from the decoder 56 in FIG.
~PSS4 are respectively input. Each AND circuit 101-1
The output of 04 is given to an OR circuit 105, and a delayed pitch synchronization signal PS ID is obtained. Each signal PSSI~
The timing at which PSS4 occurs is shown in parentheses in FIG. There, for example, the designation rly8J indicates that the signal II II II occurs in the first time slot in a period of 8 time slots. Therefore, for timing signal PSS 1, rtys, 3y
8'', the signal 111 II is generated in the first and third time slots in the 8 time slot period. As is clear from the display in parentheses of each signal PSS 1 to PSS4 in FIG. 13 and the channel timing of PSl in FIG. 3, the signal PSSI is "1" at the timing of channels 1 and 3 in PSl. Then, P.S.
S2 becomes tr 1 u at the timing of channels 2 and 6 in PSL, PSS3 becomes 111'' at the timing of channels 3 and 7 in PSL, and PSS4 becomes 1'1 at the timing of channels 4 and 8 in PSL.
'''.

As described above, the pitch synchronization signal Psi of channels 1 and 5
is 24 time slots, 2 and 6 PSI is 40 time slots, 3 and 7 PSI is 48 time slots, 4 and 8 PSI is 48 time slots,
PSl is delayed by 64 time slots, and the delayed pitch synchronization signal PSID is set as the delayed pitch synchronization signal PSID. The reason why the delay time differs depending on the channel is that the delay time is adjusted to the difference in calculation timing of each channel 1 to 4.5 to 8 in the adaptive digital filter device 21 (FIG. 11).

Returning to FIG. 16, the delayed pitch synchronization signal PSID is further delayed by eight time slots in delay circuit 506 and is applied to input SA of selector 504.

The selector 504 selects the channel whose signal PSID is 1''.
'', the filtered sample value data of that channel is fetched from the shift register 502 and input to the shift register 505. Otherwise, the contents of the shift register 505 are held in circulation via the B input of the selector 504. Thus, in the selector 504 and shift register 505 circuits, the filtered sample value data of each channel is resampled in synchronization with the pitch of the musical tone to be generated in that channel.

Pitch synchronous/asynchronous switching of filter calculation> Pitch synchronous/asynchronous designation signal PAS given from the microcomputer interface 44 (Fig. 11) to the OR circuit 51 in Fig. 12
Y is always tz when performing filter calculation with pitch synchronization.
On, the input interface 38 outputs filter calculation request signals φF1 to φF8 in response to the pitch synchronization signal PS1.
and a delayed pitch synchronization signal PS10.

Therefore, the digital filter calculation is performed when the pitch synchronization signal PS1 is generated, that is, at a sampling period synchronized with the pitch of the musical tone signal to be filtered.

As a result, the obtained filter characteristic becomes a moving formant.

When performing filter calculations without synchronizing with the pitch, the pitch synchronization/asynchronous designation signal PASY is always set to 111". Therefore, the output of the OR circuit 51 in FIG. Therefore, the input interface 38 generates the filter operation request signals φF1 to φF8 and the signal PSID at a constant period for each filter operation cycle (64 time slots).

Therefore, the sampling frequency in the digital filter calculation is constant (for example, 50 kHz) regardless of the pitch, and the obtained filter characteristic is a fixed formant.

Example of Filter Characteristics> Examples of filter characteristics that can be realized by the above embodiment are shown in FIGS. 22 to 27.

FIG. 22 shows an example of the characteristics obtained when the order of the filter is set to an odd order (31st order), which realizes bypass filter characteristics.

fs/2 is 1/2 of the sampling frequency fs, and is a frequency synchronized with the pitch of a musical tone in pitch synchronous mode, and is a constant frequency in pitch asynchronous mode.

FIG. 23 shows an example of the characteristics obtained when the order of the filter is set to an even order (32nd order), which realizes a low-pass filter characteristic.

FIG. 24 shows an example of filter characteristics that change over time in dynamic mode. In this example, the sound source waveform signal generated from the tone generator section 18 is f
(forte), that is, corresponds to the strongest key touch, and musical tone signals corresponding to p (piano) touch, mp (mezzo piano) touch, and mf (mezzo forte) touch are obtained by filtering this sound source waveform signal. In the 1-hour column showing temporal changes in filter characteristics for each case, the timing at which each filter characteristic should be switched is shown in terms of time from the start of sound generation. The numbers in the filter characteristic diagram indicate the frequency at the change point, and the unit is Hz.

It is assumed that the pitch of the musical tone to be generated is F2 note.

Figure 25 shows the spectral envelope of the original waveform of the F2 piano sound played with the f (forte) touch, and Figure 26 shows the spectral envelope of the F2 piano sound played with the p (piano) touch.
shows the spectral envelope of the original waveform of the piano sound. The spectral envelope of the musical tone signal obtained by filtering the original waveform of FIG. 25 using the filter characteristics at the time of ○ms in the p (piano) column of FIG. 24 is shown in FIG. It can be seen that the spectrum envelope of the original waveform of p-touch shown in Fig. 26 is similar.

Example of modification> The pitch synchronization output circuit 5o shown in FIG. 16 uses shift registers 502 and 505 to perform pitch synchronization processing in channel time division. A circuit may be provided to perform pitch synchronization processing in parallel.

In the above embodiment, an FIR filter with symmetrical coefficients is used as the digital filter, but the present invention is not limited to this, and an FIR filter with asymmetrical coefficients may be used. Further, the filter type is not limited to FIR, but IIR (infinite impulse response) or other types may be used.

The storage format of the parameter memory shown in FIG. 21 is not limited to this, and various changes are possible. For example, such a hierarchical structure may not be adopted.

Further, the method of addressing the parameter memory is not limited to the procedure shown in the above embodiment, and various changes are possible. For example, in the embodiment, the key group table is accessed first, and then the touch group table is accessed, but
This may be the other way around. In addition, in FIG. 15, a microprogramming method is used in which the readout procedure is stored in advance in the program memory 451, and the parameter memory 47 is read out in this way. Readout control may be performed by a hard-wired circuit or a complete software program.

Further, in the above embodiment, the present invention is applied to a multi-tone electronic musical instrument, but it is of course applicable to a single-tone electronic musical instrument as well.

Furthermore, the present invention is applicable not only to dedicated electronic musical instruments but also to general devices having musical tone signal generation or processing functions.

In the above embodiment, it is assumed that the digital tone signal sample value data inputted from the tone generator to the adaptive digital filter device is itself sampled in synchronization with the pitch, but the present invention is not limited to this. For example, even when a digital musical tone signal sampled at a pitch-asynchronous fixed sampling period is input to a digital filter device, the input digital musical tone signal is resampled by a pitch synchronization signal and a filter calculation operation synchronized with the pitch is performed. do it.

Further, in the above embodiment, the pitch synchronization signal generation circuit is included in the tone generator, and the pitch synchronization signal generated therein is introduced into the adaptive digital filter device, but the present invention is not limited to this. For example, when a digital musical tone signal with a sampling period synchronized with the pitch is input to a digital filter, a pitch synchronization signal is generated by detecting a change in the sample value data of this digital filter, and the pitch synchronization signal generated in this way is used to control the filter. The calculation operation may also be controlled.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an overview of the invention, Fig. 2 is a block diagram showing the overall configuration of an electronic musical instrument according to an embodiment of the invention, and Fig. 3 shows the timing of main signals in the embodiment. Timing chart, Figure 4 is a block diagram showing an example of the pitch synchronization signal generation circuit included in the tone generator of Figure 2, Figure 5 is a block diagram showing the basic configuration of the FIR filter, Figures 6 and 7. are graphs showing an example of the symmetry of the impulse response in a linear phase FIR filter when the order N is an odd number and an even number, respectively. Figures 8 and 9 are graphs showing examples of the frequency response characteristics in a linear phase FIR filter when the order N is an even number. 10 is a flowchart showing an example of a procedure for determining filter coefficients, FIG. 11 is a block diagram showing an example of the adaptive digital filter device in FIG. 2, and FIG. Fig. 12 is a block diagram showing an example of the input interface x- in Fig. 11, Fig. 13 is a block diagram showing an example of the timing signal generation circuit in Fig. 11, and Fig. 14 shows the state memory and multiplication circuit in Fig. 11. FIG. 3 is a block diagram showing an example of a filter and an accumulator section (that is, an example of an FIR type digital filter circuit). FIG. 15 is a block diagram showing an example of the parameter processing unit and parameter supply circuit in FIG. 11. FIG. 16 is a block diagram showing an example of the pitch synchronization output circuit in FIG. 11, FIG. 17 is a timing chart showing an example of generation of various signals that control filter calculation timing, and FIG.
In the digital filter circuit shown in the figure, even order (
FIR when realizing filter characteristics consisting of (32nd order)
Figure 19 is a schematic diagram for explaining the basic operation of type filter calculation.
A schematic diagram for explaining the basic operation of the R-type filter operation. The figure shows an example of a storage format in the parameter memory shown in FIGS. 11 and 15. 22 and 23 are diagrams showing examples of filter characteristics for odd and even orders, respectively, realized in one embodiment of the present invention shown in FIGS. 2 to 21, and FIG. 24 is a diagram showing the same implementation. Figures 25 and 26 show examples of time-varying filter characteristics realized in the example dynamic mode for several touch intensities. and FIG. 27 is a diagram showing an example of the spectral envelope of a musical tone signal obtained when the Forte Touch original waveform is filtered with the Piano Touch filter characteristics in the above embodiment. 110... Pitch synchronization signal generation means, 111... Digital filter circuit, 10... Keyboard, 11... Key touch detector, 18... Tone generator, 19...
... Pitch synchronization signal generation circuit, 21.22 ... Adaptive digital filter device, 40.42 ... State memory, 41.43 ... Multiplier and accumulator section, 45 ... Parameter processing unit, 4
7...Parameter memory, 50...Pitch synchronization output circuit. Fig. 1 d,,'r adjustment adjustment 19 Fig. 4 Fig. 5 O; 0 Fig. 6 ''(-97''-138Figure 12-a, 7g-I'1;

Claims (1)

[Scope of Claims] 1. Pitch synchronization signal generation means for generating a signal synchronized with the pitch of a digital musical tone signal; and inputting the digital musical tone signal and synchronizing with the pitch synchronization signal generated from the pitch synchronization signal generation means. A musical tone signal processing device comprising a digital filter circuit that performs filter calculation at a sampling period of 2. Pitch synchronization signal generation means for generating a signal synchronized with the pitch of a digital musical tone signal, and generating a pitch synchronization/asynchronous designation signal that specifies whether the filter operation should be performed in synchronization with the pitch of the musical tone or asynchronously. means for inputting the digital musical tone signal and, depending on the pitch synchronization/asynchronous designation signal, performing either a sampling period synchronized with the pitch synchronization signal generated from the pitch synchronization signal generation means or a predetermined common sampling period. A musical tone signal processing device comprising a digital filter circuit that performs a filter calculation in one cycle.