JPS5949595A - Digital filter for electronic musical instrument - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] The present invention relates to a digital filter device for an electronic musical instrument.
In particular, it relates to a device that includes a plurality of digital filters with different configurations.

Recently, attempts have been made to use digital filters as means for imparting timbre with identified formant characteristics to digital musical tone signals. There are several basic types of digital filters, and it is possible to construct digital filters with various configurations based on these basic types. For example, even if the basic type is the same, digital filters with different configurations can be constructed by varying the number of arithmetic stages. ′! Furthermore, it goes without saying that if the basic model differs, the configuration of the digital filter realized will differ. When using a digital filter as a timbre circuit of an electronic musical instrument, it is preferable to employ a digital filter with an appropriate configuration depending on the purpose of timbre control.

However, since it is impossible to selectively change the configuration of a digital filter that has a fixed configuration, there is a problem in that once a filter with this configuration is installed in a timbre circuit, it cannot be easily changed. Furthermore, digital filters with various configurations are required depending on the models of various electronic musical instruments, so it would be advantageous in terms of manufacturing costs if a large number of digital filters with different configurations were individually created in advance. It becomes uneconomical.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to enable one digital filter device to selectively implement digital filters of various configurations. In addition, by combining a plurality of digital filter circuit devices with a common hardware configuration and selectively switching the filter configuration within each circuit device, various filter configurations can be selectively realized as a whole. The purpose is to reduce manufacturing costs by standardizing the hardware configuration. The above object is achieved by a digital filter device including a plurality of digital filters having different configurations and a connection switching means for selectively switching connection combinations of these digital filters in accordance with a selection signal. The filter configuration of the entire digital filter device can be expected to have a variety of combinations, such as digital filters having different configurations that are combined according to the connection combinations by the connection switching means.

The connection combination by the connection switching means can be fixed or semi-fixed in any combination depending on the control purpose, or can be changed at any time by switch operation. It is effective to use digital filters of different basic types as the plurality of digital filters. For example, a pole filter that can mainly control the pole in the amplitude frequency characteristic and a zero filter that can mainly control the zero point in the amplitude frequency characteristic are included. Further, even if the basic type of filter is the same, the configuration may be changed by changing the number of calculation stages, so that a plurality of filters may be included.

An example of a connection combination is a combination in which a pole filter is placed in the front stage and a zero filter is placed in the latter stage, and vice versa.
A combination of polar filters in order, a combination of zero filters alone,
A combination of pole filters alone, a combination of cascade-connecting two or more pole filters (or zero filters) with different numbers of stages,
Various combinations can be considered, such as a combination in which a pole filter and a zero filter are connected in parallel, and a combination in which pole filters (or zero filters) are connected in parallel. In addition to the pole filter and zero filter, it is also possible to use infinite impulse response filters (IIR filters) or finite impulse response filters (Fl, R filters) with other configurations.

Further, according to the present invention, a plurality of unitized filter circuit devices including a plurality of digital filters having different configurations and a connection switching means for selectively switching connection combinations of these digital filters according to a selection signal are provided. A digital filter device in which the units are connected to each other, and connection combinations of digital filters in each unit can be set arbitrarily by the connection switching means for each unit, and as a result, various filter configurations can be selectively realized as a whole. is proposed. For example, one unitized filter circuit device includes a pole filter and a zero filter, and the connection combination thereof can be switched.

Then, in the first filter circuit device, a combination is selected in which the zero filter is connected to the front stage and the pole filter is connected to the rear stage, and in the second filter circuit device connected cascaded to this first device, the pole filter is connected to the front stage. Select the combination in which the zero filter is connected to the subsequent stage.

In this way, it is practically possible to realize a filter configuration in which the filters are cascaded in the order of zero filter → pole filter → pole filter → zero filter. As another example, between the above-mentioned first filter circuit device and second filter circuit device,
Insert a third filter circuit arrangement in which a connection combination of only a polar filter is selected. In this way, it is possible to realize a filter configuration in which the filters are cascaded in the order of zero filter→pole filter→pole filter→pole filter→zero filter.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

In FIG. 1, the keyboard section 9 includes a plurality of keyboards (for example, an upper keyboard, a lower keyboard, and a pedal keyboard) and a key switch circuit including key switches corresponding to each key of these keyboards. The key assigner 10 includes a circuit for detecting whether each key switch of the keyboard section 9 is turned on or off, and a circuit for assigning a key corresponding to the turned-on key switch, that is, a pressed key, to one of a plurality of musical tone generation channels. Contains. Information indicating the key assigned to each musical tone generation channel (key code KC) and information indicating whether the key is suppressed or released (key-on signal KONl) are sent from the key assigner 10 to the musical tone signal generating section 11. The musical tone signal generating section 11 generates musical tone signals corresponding to keys pressed on the keyboard section 9 in accordance with the output of the key assigner 10, and converts the generated musical tone signals into keyboard notes, timbres, etc. Specifically, in order to be able to generate musical tone signals corresponding to one or more keys at the same time, the musical tone signal generating section 11 divides the musical tone signals into a plurality of sequences corresponding to the keys and outputs them in parallel. It is equipped with a number of sound source musical sound generation channels corresponding to each keyboard, and furthermore, these sound source musical sound generation channels are provided redundantly over multiple series, and the musical sound signals of each series are provided. Output in digital format in parallel.

The timbre selection device 12 includes a large number of switches for selecting timbres and various effects for each keyboard. A predetermined output TP1 among the outputs of the timbre selection device 12 is given to the musical tone signal generating section 11, and the musical tone signal generation operation in the generating section 11 (imparting a timbre to the musical tone signal to be generated, changing the amplitude envelope according to the timbre) settings, source waveform selection, etc.). Among the musical tone signals generated by the musical tone signal generating section 11, there are some musical tone signals for which a predetermined timbre is completely imparted within the generating section 11 in accordance with the tone selection by the tone color selection device 12. There are some that are not yet completed, and timbre control is applied to them in the digital filter section 14 at the subsequent stage. For example, a tone that always has the same spectral distribution regardless of the pitch (a so-called moving formant tone) is generated by the musical tone signal generator 11, and a fixed formant tone is generated by the digital filter section 14. Similarly, even for moving formant-type tones, there are some, such as positive low-frequency characteristics and Nutling-type complex power characteristics, for which it is preferable to perform spectral correction by further applying fixed formant filter control. The digital filter unit 14 is also used for these tones.

The digital musical tone signals for each series outputted from the musical tone signal generating section 11 are given to a musical tone signal distribution, accumulation and serial conversion control circuit 16. This control circuit 16 is supplied with a predetermined output TP2 among the outputs of the timbre selection device 12. The control circuit 16 divides musical tone signals into those that can be accumulated and those that should be passed through the digital filter unit 14 among each series according to the tone parameter TP2 given from the tone selection device 12, and allows accumulation. The one that accumulates (mixes) those musical tone signals and outputs it to the line 15, and the one that should pass through the digital filter section 14 serializes the parallel digital musical tone signals for each series in time and further converts the serial digital tone signals. Musical tone signals are time-division multiplexed between predetermined sequences and output to a common signal line. Note that the predetermined series to be time-division multiplexed are series that differ in keyboard type or tone color. As will be explained in detail later, in this embodiment, multiple sound sources or musical sound generation sequences (hereinafter referred to as sub-sequences) are prepared for one timbre to be achieved, and time-division multiplexing is performed between these sub-sequences. It is designed not to do this. Therefore, the control circuit 16 outputs serial digital musical tone signals time-division multiplexed between predetermined series for each sub-sequence (in parallel) and is applied to the digital filter section 14 via the line 16.

By temporally converting a multi-bit digital musical tone signal into 7 reals and then feeding it to the digital filter section 14, the arithmetic circuit inside the filter section 14 can be made into a serial arithmetic circuit, and the structure of the filter section 14 can be reduced. Contribute to Furthermore, time-division multiplexing of multiple series of digital musical tone signals and combining them into a common line eliminates the waste of having to provide a digital filter for each series, contributing to a reduction in the configuration of the digital filter section 14. However, it is not always necessary to perform unrealization and time division multiplexing, and a plurality of bits of digital musical tone signals may be input to the digital filter section 14 in parallel.

The table below shows an example of each series and an example of how they are distributed in the control circuit 13. The "single/double" column indicates whether the series is a single-tone generation series or a multiple-tone generation series. Of course, in the case of a multiple-tone series, a signal obtained by adding and mixing digital musical tone signals of a plurality of tones is output from the musical tone signal generating section 11 as a musical tone signal for one series. "Distribution"
The symbol ch1. shown in the column. ch2. ch3. ch4 indicates a filter channel, and is used as an identification symbol for each series when explaining time-division processing of musical tone signals of each series by the digital filter unit 14. Similarly, the filter channels chj to ch4 referred to herein are completely different from the tone generation channels to which the key assigner 1o assigns each pressed key, and indicate a series on which different filter processing is performed.

Table 1 In each series shown in the series column of Table 1, it is possible to select one or more of a plurality of types of tones. The above-mentioned sub-sequences are provided in each of the four streams guided to the digital filter section 14. That is, for example, in the "upper keyboard special type", it is possible to select one or more of a plurality of predetermined types of tones, and the musical tone signal (sound source signal) corresponding to the selected tone is divided into multiple sub-sequences. It is designed to occur in each case.

The musical tone signal on line 15 is applied to the mixing circuit 17, and the serial musical tone signal on line 16 is applied to the digital filter section 14.
The signal is applied to the mixing circuit 17 via. The mixing circuit 17 is for mixing (digital addition) the musical tone signal that has been filter-controlled by the digital filter section 14 and the musical tone signal of the line 15 that has not been filter-controlled, and the musical tone signal that has been subjected to filter control is serialized. Therefore, these serial musical tone signals are parallelized for each series and then the above-mentioned mixing is performed. The digital musical tone signal outputted from the mixing circuit 17 is converted into an analog signal by a digital/analog converter 18 and is provided to a sound system 19.

The digital filter unit 14 includes a pole filter that can effectively control the characteristic of the peak part of the filter characteristic and a zero filter that can effectively control the characteristic of the plateau part of the filter characteristic, and can switch the connection combination of both filters. The filter is configured so that complex filter characteristics can be realized. A predetermined output TP3 among the outputs of the timbre selection device 12 is given to the digital filter section 14, so that filter characteristics (for example, filter coefficients) for each of the filter channels ch1 to ch4 are set respectively according to the timbre selection. It has become. Further, in the digital filter section 14, out of the inputted musical tone signals of each sub-series, those to be passed through the filter and those not to be passed are sorted according to the timbre parameter TP3.

In order to set the filter characteristics, the filter section 14 includes a filter coefficient internal ROM (ROM stands for read-only memory, the same applies hereinafter), and this internal ROM
A predetermined filter coefficient is read out from M according to the timbre selection information (timbre parameter TP3) and used by the filter section 14. This filter coefficient internal RO
A filter coefficient external storage device 20 is provided separately from M. This external storage device 20 may be a semiconductor storage device, or may include a removable storage medium such as a magnetic card. Filter coefficient KO read from external storage device 20 is supplied to digital filter section 14 . A filter coefficient changeover switch 21 is provided in association with the digital filter section 14. This switch 21
is used to select whether to use the internal ROM or the external storage device 20 in the digital filter section 14, and the filter section 14 selects the filter coefficient of either one selected according to the output signal KS of the switch 21. Execute filter control.

Examples of filter coefficients stored in the external storage device 20 include filter coefficients that change over time. This is because a large storage capacity is required to change the filter coefficients over time, and an external storage device is suitable for this purpose. The external storage device 20 is supplied with the key-on signal KON from the key assigner 10 and the timbre parameter TP4 from the timbre selection device 12, and determines the time during key depression and after key release according to the key-on signal KOH. Changes in the filter coefficients over time are controlled, and the change characteristics of the filter coefficients are controlled in accordance with the timbre parameter TP4.

Similarly, the control circuit 16 generates a synchronization pulse 5Y in response to the reference timing of the serial transmission of musical tone signals to the line 16.
It is designed to output NC.

This synchronization pulse 5YNC is transmitted to the digital filter section 14.
and is applied to the external storage device 20 to serialize the filter coefficients in synchronization with the serial musical tone signal on the line 16 (
It is used for serial readout) and for synchronous control of serial calculation timing in the filter section 14.

Musical tone signal generator 1 with multi-sequence sound source, ie sub-sequences
1 and an example of the musical tone signal distribution and accumulation and serial conversion control circuit 13 connected thereto are shown in FIG. The musical tone signal generating section 11 includes a plurality of tone generators 22 having different types of keyboards or different characteristics of the sounds to be generated.
26 to 26, among which the series (tone generators 26 to 26) that may use the digital filter section 14 are each divided into three sub-series (+1°1
, +3). The pedal keyboard tone generator 22, the upper keyboard solo tone generator 26, and the upper keyboard custom tone generator 25 are single-tone tone generators, and the upper keyboard multitone tone generator 24 and the lower keyboard multitone tone generator 26 are multitone tone generators. It is. The key information (key code KC, key-on signal KO) output from the key assigner 10 (Fig. 1)
N, etc.) is input to each tone generator 22-26. This key information includes keyboard information, and the tone generators 22 to 26 corresponding to the keyboard information use the key information (
KC, KON, etc.) are used. The multitone tone generators 24 and 26 can generate a plurality of musical tone signals corresponding to a plurality of key information (KC, KON) assigned to each musical tone generation channel. The upper keyboard single-note tone generator 23.25 uses the upper keyboard key information (
When a plurality of KC, KON) are given at the same time, one of them (the highest note or the lowest note) is selected to generate that musical tone signal.

Each of the tone generators 22 to 26 can selectively apply one or more of a plurality of types of tones to the musical tone signal to be generated.

To this end, various timbre parameters TP1 corresponding to the selected timbre are given to each tone generator 22 to 26 from the timbre selection device 12 (FIG. 1), and a frequency corresponding to the timbre parameter TP1 is provided. A musical tone signal having a component or source waveform, an amplitude envelope, a number of feet, a volume, and various other musical tone elements is generated at a pitch corresponding to the pressed key. However, the timbre element based on the fixed formant is not provided here, but is provided in the digital filter section 14 at the subsequent stage.

The sub-sequences (+1 to #6) provided in the series (tone generators 23 to 26) that can utilize the digital filter section 14 are the sub-series (+1 to #6) provided in each series 23 to 26.
) is a multi-sequence sound source related to the musical tones that are about to be generated. For example, one musical tone signal to be generated by the upper keyboard solo tone generator 23 is generated by finally adding the musical tone signals generated by the tone generators corresponding to the three sub-sequences #1112 and +3. can get. Therefore, each sub-series #1゜#2
．． It is also possible that the tone signal generated at 13 is a partial tone signal. However, depending on the type of tone, all the tone generators of the sub-series may not be used. For example, only the tone generator of one sub-series #1 may be used to generate a musical tone signal. Such a multi-sequence sound source, that is, multiple sub-sequences #1
.about.#6 are advantageous when the digital filter section 14 can selectively control a part of the partial tone signals constituting one musical tone signal. This point will be explained in more detail later.

Each of the 1/-generators 22 to 26 generates a musical tone signal in digital format, and the musical tone generation method may be a frequency modulation calculation method, harmonic synthesis method, waveform memory reading method, or any other arbitrary method. method can be used.

The multitone tone generators 24 and 26 output digital musical tone signals corresponding to a plurality of pressed keys, respectively. Each tone generator 24.26 (D each sub series (#1 to #
3) Accumulators 27.2 provided respectively.
At step 8, musical tone signals corresponding to the plurality of pressed keys are accumulated for each sub-sequence.

Musical tone signal distribution and accumulation and serial conversion control circuit 13
At gates 29.30.31. Reference numeral 32 is for distributing each series of musical tone signals given from the musical tone signal generating section 11, and is controlled according to the tone color parameter TP2 given from the tone color selection device 12. The gate 29 is for selecting the output musical tone signal of the accumulator 27 corresponding to the tone generator of the first sub-series #1' of the upper keyboard multitone tone generator 24 and applying it to the accumulator 36. Referring to Table 1 above, the output of this gate 29 corresponds to an upper keyboard flute (UFL) tone signal. In other words, when some upper keyboard flute (UFL) tone is selected by the tone selection device 12, the first one of the upper keyboard multitone tone generators 24
A tone generator corresponding to sub-sequence #1 generates a musical tone signal of an upper keyboard flute type tone, and a gate 29 distributes it to the accumulator 36 side (a group that does not pass through the digital filter section 14).

The gate 60 is for selecting the W power tone signal of the accumulator 28 which has accumulated the outputs of the tone generators corresponding to the first sub-sequence #1 among the lower keyboard multitone tone generators 26 and giving it to the accumulator 66. Chiru. Referring to Table 1 above, the output of this gate 30 corresponds to a lower keyboard orchestral (LOR) tone signal.

In other words, the tone selection device 12 selects the lower keyboard orchestral (L)
oR) is selected, the lower keyboard -; the first sub-series # of the polytone tone generator 26
A tone generator corresponding to 1 generates a musical tone signal of the lower keyboard orchestral tone, and a gate 30 distributes it to an accumulator 33 side.

The gate 61 is for distributing the upper keyboard special system (USP) musical tone signal to the digital filter section 14 side, and the gate 62 is for distributing the musical tone signal of the lower keyboard special system (LSP) to the digital filter section 14 side. This is for sorting. Use the tone selection device 12 to select the upper keyboard special type (U
When some tone of SP) is selected, each sub-sequence #1 to #3 of the upper keyboard multitone tone generator 24 generates musical tone signals corresponding to the tone, and the tone signals given via the accumulator 27 are generated. Each sub-series #1 to #6
The musical tone signal is distributed to the multiplexer 34 side (digital filter section 14 side) via the gate 61. Similarly, when a lower keyboard special type (LSP) tone is selected, each sub-series #1 to #3 of the lower keyboard multitone tone generator 26 generates a musical tone signal corresponding to the tone, and the gate 62 is activated. and distributes them to the multiplexer 64 side.

Similarly, when the first sub-sequence #1 of the upper keyboard double tone tone generator 24 is used for the upper keyboard flute type (UFL) tone generator 24, the tone generator 24
Other subseries $2. #3 is the upper keyboard special type (US
In that case, the gate 31 selects the tone signal corresponding to the sub-series #2 to #6 and supplies it to the multiplexer 64. Similarly, when the first sub-sequence #1 of the lower keyboard multitone tone generator 26 is used for the lower keyboard orchestral tone generator (LOR), the other sub-series #2. #3 is the lower keyboard special type (L
SP).

In addition, it is dedicated to the tone generator 24 and 26id special series (USP, LSP), and the upper keyboard flute series (U
Dedicated tone generators for FL) and lower keyboard orchestral (LOR) may also be provided.

The accumulator 36 receives the upper keyboard flute type (UFL) and lower keyboard orchestra type (LOR) musical tone signals given from the gates 29 and 30, and the pedal keyboard type (PKB) musical tone signal generated by the tone generator 22. The output signal is applied via line 15 to mixing circuit 17 (FIG. 1).

The upper keyboard solo system (U
SL) musical tone signal, upper keyboard special system (USP) given from tone generator 24 via gate 61
The musical tone signal of the upper keyboard custom system (UO3) generated by the tone generator 25, and the musical tone signal of the lower keyboard special system (LSP) given from the tone generator 26 via the gate 32e are sent to the multiplexer 6.
4 and a parallel-to-serial converter 65 and line 16 to the digital filter section 14 (FIG. 1). The multiplexer 64 is connected to each series (USL, USP
, UO3, LSP) to filter channel c.
It is for time division multiplexing corresponding to h1 to ch4, and a control signal for this is given from a timing signal generator 66. Each series (USL, USP, UO3, LS
The musical tone signal of PI is divided into each sub-sequence 1. 1 and #6 are individually time-division multiplexed. The parallel digital musical tone signals outputted from the multiplexer 64 corresponding to each sub-sequence #1 to #3 are respectively input to a parallel-to-serial converter 65 provided corresponding to each sub-sequence. This converter 6
5 converts the digital musical tone signals of each sub-sequence #1 to #3 into temporally serial musical tone signals S□, S2 . The timing signal generator 66 provides a control signal for converting the signals into S3 and S3 respectively. Further, the timing signal generator 36 outputs the aforementioned synchronization pulse 5YNC.

FIG. 3 shows an example of the digital filter section 14 in a rough block diagram. Each sub-series #1 to output from the parallel-serial converter 65 in FIG.
Serial digital musical tone signals S□, S corresponding to #6
2. S3 is input to the filter input control circuit 67.

The filter input control circuit 37 receives each musical tone signal S, , S2 .
This is for distributing what should be input to the digital filter main circuit 38 and what should not be inputted to the digital filter main circuit 38 in accordance with the timbre parameter TP3. Musical tone signals (one or more of S□, S2 and S3) to be input to the digital filter main circuit 38 are added and mixed between the same filter channels, and are input from the input control circuit 7 to the filter main circuit 68. The remaining musical tone signals that do not pass through the digital filter main circuit 68 are sent to the digital filter section 1 via the output node control circuit 69.
Output from 4. The output control circuit 39 outputs the musical tone signal that has passed through the digital filter main circuit 68 and the musical tone signal that has not passed through the output line S□0. S20. This is to be distributed to S30.

The timing signal generation circuit 40 generates various timing signals for controlling filter calculation operations in the digital filter main circuit 38 based on the synchronization pulse 5YNC, and supplies these signals to the digital filter main circuit 68. The filter coefficient supply circuit 41 is for supplying the filter coefficient K to the digital filter main circuit 68, and includes the above-mentioned internal ROM for filter coefficients. Read and supply. Further, the filter coefficient supply circuit 41 is configured to receive the filter coefficient KO signal given from the filter coefficient external storage device 20 and the output signal KS of the filter coefficient changeover switch 21. Internal ROM according to
Either the filter coefficient read out or the filter coefficient KO given from the external storage device 20 is supplied to the digital filter main circuit 68. In addition, the filter coefficient supply circuit 4
1 includes a synchronization pulse 5YNC and a timing signal generation circuit 4
06 output signal is given, and the filter coefficients are supplied in synchronization with the filter calculation timing.

How to use the multi-sequence sound source (sub-sequences #1 to #6) will be described next with some examples.

One method is to create a slight pitch shift between the musical tone signals generated in each sub-sequence #1 to #3, and to pass all of the musical tone signals 81 to S3 of each sub-series to the digital filter main circuit 38. be.

Tones suitable for this usage include strings and chorus (a plurality of human voices). This is because: I) In the case of Gunnu tone, multiple sub-sequences #1 to #6
By generating musical tone signals whose pitches are slightly shifted from each other, it is possible to achieve the effect of playing multiple stringed instruments at the same time.Also, since every note contains a fixed formant, musical tones of all sub-series can be realized. This is because it is desirable to pass the signals si and -s3 through the digital filter main circuit 68 to give each a timbre component based on a fixed formant. -! , f? In the case of L1 chorus tone, multiple human voice sounds can be imitated more naturally by generating human voice sound signals whose pitches are slightly shifted from each other in multiple sub-sequences #1 to #6. Since the tone signals include fixed formants, it is preferable to pass the musical tone signals of all sub-sequences through the digital filter main circuit 68. As for the form of control in this case, for example, if a string tone is selected in the upper keyboard custom system (UC8), the three tone generators corresponding to each sub-sequence #1 to #6 in the tone generator 25 in FIG. The musical tone signals corresponding to the selected string tones are generated at pitches corresponding to the pressed keys and slightly shifted from each other, and the input control circuit 67 in FIG. 3 generates musical tone signals 8 of the upper keyboard custom system.
When 1 to S3 are input, all sub-sequences #1 to
The musical tone signals 81 to S3 of #6 are distributed to the digital filter main circuit 68 according to the tone parameter TP3 indicating a string tone. In this method, each subsequence #1
~#3 form independent musical tone signals, and all of these musical tone signals include fixed formants.

The second usage method is to make the pitches of the musical tone signals generated in each sub-sequence #1 to #6 the same, but to make the amplitude envelopes different, respectively, and to make the musical tone signals of a specific sub-series (S1 to S
This is a method in which only one or more of the three filters are passed through the digital filter main circuit 68. Tones suitable for this method include piano, vibraphone, and electric bass. Using piano tones as an example, each sub-series #1 to #6
An example of the amplitude envelope given by is shown in Figure 4 (a
), the amplitude envelope given in the first sub-sequence #1 is intended to imitate the amplitude envelope due to a soundboard, and the amplitude envelope given in the second and third sub-sequences F2 . The amplitude envelope given by $3 (longer sustain than #1) is intended to imitate the amplitude envelope caused by strings. In this case, the timbre component due to the soundboard is a fixed formant, and the timbre component due to the strings is a moving formant (the spectral distribution does not change even if the fundamental frequency changes), so the input control circuit 37 in FIG. , the musical tone signal S□ corresponding to the first sub-sequence #1 is passed through the digital filter main circuit 38, and the musical tone signal S2 . '83 is controlled so as to pass through the digital filter main circuit 68. In this method, each of the subsequences #1 to #3 forms a partial tone signal for forming one musical tone, and some of the partials include fixed formants.

The third usage method is to use the same fundamental frequency of the musical tone signals generated in each sub-sequence #1 to #6, but different bands of harmonic components, and to generate musical tone signals 80-S3 of all sub-sequences. This is a method of inputting to the digital filter main circuit 68. This method is suitable for synthesizing tones (for example, human voice sounds) having a plurality of fixed formants as shown in FIG. 4(b). That is, the first of multiple fixed formants.
The formant (mountain) of is emphasized by the musical sound signal S□ generated in the first sub-sequence #1, the second formant (mountain) is emphasized by the musical sound signal S2 of the second sub-sequence #2, and the formant (mountain) of the third Forman)-f mountain) is emphasized by the musical tone signal S3 of the third sub-sequence #6. In this case, sub-sequence #1 generates a musical tone signal S1 that intensively includes harmonic components corresponding to the first formant band, and sub-sequence #2 generates a musical tone signal S1 that intensively includes harmonic components corresponding to the second formant band. In step #3, a musical tone signal S3 containing concentrated harmonic components corresponding to the band of the formant of Edict 3 is generated. It is difficult to create a musical tone signal containing harmonic components evenly over a wide band at once.
This method of sharing the bandwidth among the sub-sequences #1 to #6 is extremely effective. In this method, each sub-series #1 to #6
, respectively, to form partial tone signals for forming one musical tone, and all of the partial tones include fixed formants.

The fourth usage method is to set the pitch of the musical tone signals generated in each sub-sequence #1 to #3 to be the same, but key-fingle their volume levels with different characteristics, and among them, the musical tone signal of a specific sub-series ( This is a method in which only one or more of St to S3 are passed through the digital filter main circuit 68.

This method is suitable for the tones of double-reed instruments such as oboes and bassoons. In such types of tones, the higher the range of the fundamental frequency, the stronger the moving formant component, and the lower the range, the stronger the fixed formant component. Therefore, the volume level of the musical tone signal generated in each sub-sequence #1 to #6 is key scaled with different characteristics depending on the pitch, that is, the fundamental frequency of the key, as shown in FIG. 4(C). The musical tone signal S□ of sub-sequence #1 with emphasis on the bass range is sent to the digital filter main circuit 3.
8, a fixed formant is given to the musical tone corresponding to the key in the low range. Sub-series #6 that emphasizes the treble range
The musical tone signal S3 of the sub-sequence #2, which has not been subjected to any key falling, is passed through the digital filter main circuit 68.
8 or not may be determined as appropriate according to the characteristics of the constant tone.

The fifth usage method is to generate musical tone signals with different foot systems in each sub-series #1 to #3, and to digitally filter only the musical tone signals of a specific sub-series (one or more of S1 to S3). This is a method of passing it through the main circuit 38. This is suitable for applying fixed formants only to a specific foot system.

The sixth usage method is to generate sound source signals with different waveforms (sine wave, square wave, sawtooth wave, etc.) in each sub-sequence #1 to #3, and generate only specific sound source signals (for example, square wave and sawtooth wave). wave) is passed through the digital filter main circuit 38.

In the above description, a plurality of musical tone signals corresponding to one tone selectable by operating the l switch in the tone selection device 12 are generated in each sub-sequence #1 to #6 using different methods, and these signals are synthesized. The selected l
The premise is that a musical tone signal corresponding to a tone is formed. However, the present invention is not limited to this, and each sub-series #1 to #3
generate musical tone signals with completely different tones, and only the musical tone signals (one or more of S1 to S3) to which a fixed formant should be added are sent to the digital filter main circuit 6.
It is also possible to control the input to 8.

In FIG. 3, the digital filter main circuit 68 includes a pole filter 42 and a zero filter 46, both filters 42, 43 being connected in series. A pole filter is one that can control the peak part of the filter characteristic (amplitude frequency characteristic), and a zero filter is one that can control the valley part of the filter characteristic. For example, in a human voice, the amplitude-frequency characteristic of the seventh male voice "A" is as shown in the solid line in Figure 5 (a), but if you try to realize this using only a polar filter, the valleys will become like broken lines. , the level does not drop sufficiently. This is because the polar filter alone can set the characteristic only by superimposing the peaks of the amplitude frequency characteristic. Therefore, if a zero filter is provided in series with the pole filter and the characteristics of the zero filter are set so as to sufficiently reduce the level of the desired frequency component, it is possible to
) The level of the valley can be lowered sufficiently as shown by the solid line.

FIG. 5(b) is a diagram showing the amplitude frequency characteristics of a positive tone, which is difficult to achieve with a polar filter alone, but can be achieved with a combination of a polar filter and a zero filter. That is, the characteristics of the zero filter may be set to lower the level of the low-frequency components (so that the zero point is the frequency zero), and the characteristics of the high-level high-frequency components may be set using a pole filter. Although it is difficult to achieve the amplitude-frequency characteristics of nutring tones as shown in Figure 5 (C) using a pole filter alone, it is possible to combine a zero filter and a pole filter to create a zero filter so that a predetermined frequency becomes the zero point. This can be achieved by setting the characteristics. It is advantageous to combine pole filters and zero filters in series, as in some of the examples described above, as complex frequency characteristics can be realized.

In general, a pole filter has coefficients Ki I, where i=t, 2 . It has a closed loop that feeds back to the input side the sum weighted by . In addition, the zero filter has a coefficient Ki (7
' (i = 1.2...n), which outputs the sum of the weighted results, and is expressed by a finite impulse response filter (hereinafter referred to as FIR filter) as shown in Figure 7. . In FIGS. 6 and 7, blocks marked with "delay", such as blocks with reference numbers 44 and 45, indicate delay circuits, which delay the input digital waveform signal for a time corresponding to its l sampling time. However, there will be a delay. Reference number 46.4
Triangular blocks such as the block numbered 7 are multipliers for multiplying the filter coefficients by 1 to Kn to the digital waveform signal. Blocks marked with a plus sign, such as reference numbers 48 and 49, indicate adders.

A lattice filter is a type of IIR filter, and this lattice filter is known as a filter suitable for speech synthesis. Furthermore, compared to other types, this lattice filter requires fewer multipliers and has the advantage of being able to downsize the hardware. It also requires fewer bits for the filter coefficients, and allows the desired filter to be filtered. This has the advantage that the method of setting coefficients for the characteristics is established. Therefore, in this embodiment, a lattice filter is used as a preferable example of the polar filter.

The basic format of the lattice filter is shown in FIG. 8(a), and FIG. 8(b) and (e) show formats obtained by isometrically converting the basic format. The representation of each circuit element in this figure is the same as in FIGS. 6 and 7, with reference numbers 50 to 55 representing one sampling time delay circuits, and 56 and 57 representing triangles. The one marked with the symbol 58.59 is the multiplier, and the one marked with a 10 sign (like 58.59) is the adder (or subtracter). In the figure, one stage (1
Although filter units (corresponding to the sampling time delay) are shown, an appropriate number of these filter units are connected in cascade to form a lattice-type polar filter circuit. The subscript i of the filter coefficient Ki is the first stage (i=1.2, 3
．． . . n) is the coefficient of the filter unit. The delay circuits 50, 51 and 52 are used to feed back the signal from one sampling time ago to the filter unit in the previous stage, and in actual circuits, the delay is calculated by subtracting the time delay in the arithmetic circuit from the l sampling time. Set as time. The final stage filter unit is configured to feed back its own output signal. For this purpose, a delay circuit 53 is installed on the output side.
54 and 55 are provided to set a time delay corresponding to one sampling time between the output of the final stage filter unit and its feedback input. Since the lattice filter of the type shown in FIG. 8C has the smallest number of multipliers, it is advantageous to use it.

FIG. 9 shows an example in which the pole filter 42 in the digital filter main circuit 38 (FIG. 3) is constituted by a lattice filter of the type shown in FIG. 8(e). The pole filter 42 is composed of a 12-stage lattice filter, and the filter units at each stage are designated by symbols L1 to L12. The pole filter 42 in FIG. 9 is constructed in consideration of the calculation time delay in the multiplier. An example of the zero filter 43 in the digital filter main circuit 68 (FIG. 3), which is also configured with calculation time delay in mind, is shown in the first example.
Shown in Figure 0. Since this zero filter 46 is a second-order zero filter (a zero filter including a delay element for two sampling times), it is simply a cascade connection of two stages of the delay circuits 44 in the FI'R filter shown in FIG. Although it may be configured as shown in FIG. 10, considering calculation time delay and other factors.

Before explaining FIGS. 9 and 10, this polar filter 42
The data format of the digital tone signal input to the zero filter 43 will be explained.

- As an example, if one musical tone signal consists of 24-bit digital data, each sub-sequence of serial musical tone signals is supplied from the control circuit 13 in FIG. 2 to the digital filter section 14 in FIG. 3 via the line 16. S1. S2.
S3 is temporally serialized using 24 time slots for each signal, and the serial musical tone signals for these 24 time slots are time-division multiplexed for 4 filter channels. Therefore, the serial musical tone signals S□, S2 . One sampling period of the musical waveform amplitude in S3 is "24 x 4-96 time slots". The first time slots are numbered from 1 to 96 within this 1 sampling period.
1(a).

FIG. 11(b) shows serial musical tone signals S□, S2 . This shows the data contents of S3. The timings shown in FIGS. 11(a) and (b) are as follows:
Serial musical tone signal S1 of each sub-series. This is common to B2° and B3. As shown in FIG. 11(1)), the serial musical tone signal S1. B2. In B3, the filter channel ch1 is placed in the first time slot to the 24th time slot.
(Upper keyboard solo USL) 7 real musical tone signal data,
7 real musical tone signals of filter channel Ch2 (JJIE special system USP) in the 25th to 48th time slots, filter channel ch3 (upper keyboard custom system UC8) in the 49th to 72nd time slots. 7 real musical tone signal data, filter channel ch4 (
Serial musical tone signal data of the lower keyboard smooth/yellow type LSP) are respectively assigned. In each musical tone signal data every 24 time slots, the first time slot (first
．． 25th. No. 49. The lowest pitch (LSB) is assigned to the 73rd time slot (23rd, 47th, 71st, and 95th time slots), and the later the time slots become, the more eastward the signal becomes. The most significant bit MSB is assigned and the last time slot (24th, 48th, 72nd, 96th time slot)
Sign pit SB is assigned to SB.

Returning to FIG. 9, the first stage filter unit L1 will be described. Reference number 61 is an adder functioning as a subtracter, 62 and 63 are adders, 64 is a multiplier, 65, 66 .
67 is a delay circuit. The number 32D shown in the blocks of delay circuits 65-67 indicates that a delay of 32 time slots is provided. FS-IN is a forward input terminal for musical tone signals, FS-OUT is a forward output terminal for musical tone signals,
BS-IN is a reverse input terminal, and B5-0UT is a reverse output terminal. Other units) L2 to L12 are also units L.
1, and the forward output terminal FS-OUT of each unit L1 to L11 is connected to the next unit L2 to L.
12 forward input terminals FS-IN, each unit)
The reverse output terminals B5-0UT of L2 to L12 are connected to the reverse input terminals BS-IN of the preceding units L1 to L11.

filter unit) Ll adder (function is subtracter)
61, the musical tone signal input from the forward input terminal FS-IN is subtracted from the musical tone signal fed from the next stage UNINNO) L2 via the backward input terminal BS-IN and the delay circuit 66. .

The output of this adder 61 is input to a multiplier 64, and the filter coefficient is multiplied by □. The subscript l in the compression coefficient indicates that it is a coefficient corresponding to the first stage unit L1. The output of the multiplier 64 is given to the adder 62, and the output of the multiplier 64 is applied to the terminal FS-I.
N and the input musical tone signal provided via the delay circuit 65. Here, the reason why the delay circuit 65f is provided is to meet the calculation time delay in the q-multiplier 64. That is, in this example, the calculation time delay of the multiplier 64 is designed to be 32 time slots.
In order to accommodate this delay, the delay circuit 65 provides a delay of 32 time slots.

The output of the adder 62 is input to the next stage unit L2 via the output terminal FS-OUT.

By the way, there must be a time delay corresponding to one sampling period between the output of the adder 61 and the signal fed from the next stage unit L2 to the adder 61 via the delay circuit 66. However, this is satisfied as follows. Next stage unit) L2 multiplier 6
A musical tone signal from the unit L1 via the adder 69 is input to the reverse input terminal BS-IN of the unit L1, and this is input to the delay circuit 6.
6 to the adder 61. Therefore, the output signal of adder 61 is delayed by 32 time slots in multiplier 64, then delayed by 32 time slots in multiplier 68 at the next stage, and further delayed by 32 time slots in delay circuit 66, resulting in an accounting of 96 time slots. It is then fed back to the adder 61 with a lot delay. As mentioned above, since one sampling period of the serial musical tone signals S1 to S3 is 96 time slots, the necessary delay time is secured as described above.

Adder 63 (
69 in L2) is the output of the multiplier 64 (68 in L2) and the next stage unit L2 (L3 in L2) which is provided via the output of the multiplier 64 (68 in L2) and delay circuits 66 and 67 (70, 711 in L2).
This is for adding the feedback signals from the The output of multiplier 64 corresponding to the output of delay circuit 66 lags the output timing of delay circuit 66 by 32 time slots. A delay circuit 67 is provided to set a time delay commensurate with this delay.

The final stage unit (L12) feeds its own output musical tone signal. Therefore, since the time delay of 32 time slots in the multiplier of the next stage unit as mentioned above cannot be expected, the output signal of the 1 axillary output terminal FS-OUT of the unit I12 is fed back to the reverse input terminal BS-IN. It is assumed that a delay circuit 72 is provided for setting a time delay of 32 time slots in the loop.

Similarly, in the following, KFSi and BS are used to specify the forward input terminal FS-IN and the reverse output terminal B5-0UT of the first-stage filter unit L1. The last filter unit L12 (7) forward output terminal FS-OUT
The symbols FSo and BSi are used to specify the reverse input terminal BS-IN.

In the zero filter 43 shown in FIG. 10, the second-order zero filter is composed of multipliers 73, 74, adders 75, 76, and delay circuits 77, 78, and 79. The first stage of this second-order zero filter includes a multiplier 76 to which an input musical tone signal is applied, a delay circuit 77 that delays the output signal of this multiplier 73 by 64 time slots, and this delay circuit 77.
Adder "75" which adds the output signal of 7 and the input musical tone signal
It consists of Multiplier 76 is given a filter coefficient of 03 corresponding to the first stage zero filter. Multiplier 73.
It is assumed that the computation time delay in 74 is 32 time slots as described above. Therefore, the multiplier 76 and the delay circuit 77
The delay time in T is 96 time slots in total, and T
degree l sampling period. Therefore, the adder 75 adds the musical tone signal of the current sampling time and the musical tone signal of one sampling period before the current sampling time to a signal obtained by multiplying the filter coefficient by 13. The second stage zero filter includes a delay circuit 78 that delays the input musical tone signal by 128 time slots, a multiplier 74 that multiplies the output signal of this delay circuit 78 by a filter coefficient KH, and a multiplier 74 that multiplies the output signal of this multiplier 74 by 328 time slots. A delay circuit 79 that delays the time slot, and an adder 76 that adds the output signal of this delay circuit 79 and the output signal of the adder 75.
It consists of The total delay time due to circuits 78, 74, 79 is 192 time slots, which is exactly 2 sampling periods. Therefore, in the adder 76, the output signal of the adder 75 is added to the signal obtained by multiplying the filter coefficient by 14 to the musical tone signal obtained two sampling times ago. In other words, in the adders 75 and 76, the musical tone signal of the current sampling time, the musical tone signal of one sampling period before the filter coefficient multiplied by □3, and the musical tone signal of two sampling periods before the filter coefficient are applied. The total overlap with the signal multiplied by 4 is calculated.

In this way, the output signal of the second-order zero filter is obtained from the adder 76.

The output signal of adder 76 is delayed by 64 time slots in delay circuit 80 and input to multiplier 81 .

The multiplier 81 is provided to control the output gain of the zero filter 43, and is inputted with a coefficient for gain control. In addition to the above coefficients, 3. K and 4 are involved in setting the filter characteristics of the zero filter 46, but the coefficient □5 is not involved in setting the filter characteristics but sets the gain of the entire zero filter. The calculation time delay in the multiplier 81 is 32 time slots as in the above case, and the delay circuit 80 which delays by 64 time slots adjusts the signal delay time in the gain control circuits 80 and 81 by one sampling period ( 96 time slot).

In addition, the first stage circuit 73, 77°75 of the zero filter 46
and delay circuits 77.78 in each of the second stage circuits 78, 74, 79, 76 and gain control circuits 80.81.
, 79.80 are not limited to the locations shown in the diagram, but the main point is 1.
It is sufficient that a delay of one sampling time is set in the first stage, a delay of two sampling times is set in the second stage, and a delay of one sampling time is set in the gain control stage. For example, a delay circuit 77 is provided on the input side of the multiplier 760, and the positions of delay circuits 78 and 79 are
・The delay circuit 80 is placed on the output side of the multiplier 81.
may be provided. However, as will be described later, in this embodiment, each filter coefficient □ to 15 is provided to the digital filter main circuit 68 in a time-serial data format, and each multiplier 64, 68 .・
. . 82.76.74.81 are designed to perform serial calculations in a predetermined time relationship. Therefore, each multiplier 64.68. ... It is necessary to appropriately control the input timing of signals to 82.73 and 74.81, and for this purpose delay circuits 77.78 are installed at the locations shown in FIG.
゜79.80 is provided.

The time delay between the input signal and the output signal in the pole filter 42 and zero filter 43 in FIGS. 9 and 10 is:
The polar filter 42 has 12 stages of filters (uniso) L1 to 1.
, 120 for a total of 384 time slots, or 4 sampling periods, and 3 sampling periods for the zero filter 46.

Filter coefficients of 0 to 05 for the pole filter 42 and the zero filter 46 are given from the filter coefficient supply circuit 41 (FIG. 3). The fill coefficients □~05 are assigned to predetermined multipliers 64, 68 . . . 82, 73° 74.81, but in this embodiment, the filter coefficients supplied from the filter coefficient supply circuit 41 to the digital filter main circuit 38 are provided for each filter coefficient. It is a temporal serialization of 0 to 15. The format for serialized filter coefficients is illustrated in FIG. - As an example, one filter coefficient is 8-bit digital data;
5 filter coefficients and 1. The total number of bits of l is 12
It is 0 bit. Therefore, the number of time slots required to serialize filter coefficients 0 to 05 for one tone (one filter channel) is 120, and the number of time slots required to send these to four filter channels is "
120X4=480J. One cycle time (480 time slot days) of serial time-division transmission using this fill coefficient is 5 sampling periods (480 time slots) of the serial musical tone signal.
Corresponds to ÷9 6=5>.

Referring to FIG. 12(a)', the filter coefficient serial data for one channel includes (K, 5, K, 4, K13
), and then in order from those corresponding to the latter stage of the polar film 42 (K□2, to □□...K 2r K
1)). Then, in the 7 real data of the individual filter coefficients for every 8 bits, the sign bit SB is sent out in order from the most significant bits (MSB indicates the most significant bit, and LSB indicates the least significant bit). Inside the digital filter main circuit 68, the filter coefficient serial data K is sequentially shifted, and 05 is serial-parallel converted into individual filter coefficients □ to 05, and predetermined multipliers 64, 68, . ...82.7
-3°74.81 (Figures 9 and 10). The data serialized in the format shown in FIG. 12 (L) for each channel is further divided into filter channels Ch1 to C as shown in FIG. 12B.
Between h4 (in the order of chl, ch2.ch3.ch4)
Time division multiplexed.

FIG. 13 shows a more detailed embodiment of the digital filter section 14 in FIGS. 1 and 3. In FIG. Specifically, FIG. 13 is a block diagram showing the internal configuration of one digital filter circuit device (chip) DFC that can be used as the digital filter unit 14 shown in FIGS. 1 and 3. The digital filter section 14 in FIG. 1 may be configured using only one digital filter circuit device DFC as shown in FIG.
As described later, a plurality of the devices DFC may be combined. In FIG. 13, each circuit 6 shown in FIG.
Portions corresponding to numbers 7 to 43 are given the same reference numerals. That is, one digital filter circuit device DFC is
Broadly speaking, as in FIG. 3, the filter input control circuit 6
7. Digital filter main circuit 38, output control circuit 69
, a timing signal generation circuit 40 and a filter coefficient supply circuit 41, and the digital filter main circuit 68 includes a pole filter 42 (
9) and a second-order zero filter 46 (see FIG. 10).

Musical tone signal input terminal "l+ 12+ ■3 is serial digital musical tone signal S□ corresponding to valley sub-series #1 to #3
+ S2 + S and l are applied, respectively. The filter input control circuit 37 includes an AND circuit 83 for individually gating each signal S~S3 given from the terminal ~3.
, 84, 85, and a serial adder 86 for adding the serial tone signals outputted from these AND circuits 86 to 85. Digital filter main circuit 3
8 includes the aforementioned pole filter 42 and zero filter 46 as well as selectors 87, 88, 89 for switching the connection combination of these filters 42, 43.

The first input A of the selector 87 receives the musical tone signal applied from the input terminal Fi, the second input B receives the serial musical tone signal Si output from the serial adder 86, and the third input B receives the serial musical tone signal Si output from the serial adder 86. The output signal 2° of the zero filter 43 is input to the input C. The serial musical tone signal (denoted as FS) output from the output S of the selector 87 is sent to the forward input terminal F of the filter unit L1 in the first stage of the polar filter 420.
It is input to Si (see FIG. 9). In addition, the polar filter 4
Reverse output terminal BS of 1st stage filter 2) Ll
. (See Figure 9) is output terminal B. given to.

The forward output terminal FSo (see FIG. 9) of the filter unit L12 at the final stage of the pole filter 42 is applied to the delay circuit 72 and output terminal F. and is applied to the second input B of the selector 89. A first input AK of the selector 89 receives the ζ serial tone signal Si output from the serial adder 86. This serial musical tone signal Si and the serial musical tone signal FS output from the selector 87 are as follows:
Both have the same data format and timing as the serial musical tone signals S□ to S3 applied to the input terminals 1 and 1 to I3. (See FIG. 11(b)).

The delay circuit 72 in FIG. 13 has the same function as the delay circuit 72 in FIG. The output signal of this delay circuit 72 is applied to the second input B of the selector 88. selector 8
The serial musical tone signal applied from the input terminal Bi is added to the first input A of the filter unit 8, and its output S is sent to the reverse input terminal B51 (
(see Figure 9). In addition, the selector 8
The output S of 9 is the input terminal ZSi (first
(see figure 0). Serial tone signal Z output from output terminal ZSi (see FIG. 10) of zero filter 43. is applied to the input C of the selector 870 as described above, and is also applied to the AND circuits 90 and 91 of the output control circuit 69.
．． 92.

In the digital filter main circuit 38, for example, the connection between the pole filter 42 and the zero filter 46 can be switched in three ways. One of them is to connect the pole filter 42 in the first stage, the zero filter 46 in the second stage, and connect them in series.

The other way is to put the zero filter 46 in the front stage, on the contrary.
Both are connected in series with the pole filter 42 in the latter stage. Yet another method is to use the pole filter 42 alone and not connect it to the zero filter 46. Such a pole filter 42 and zero filter 4
The connection switching of No. 6 functions effectively when a plurality of digital filter circuit devices DFC are used in combination as the digital filter unit 14. In order to control connection switching between the pole filter 42 and the zero filter 43, control codes CI and C2 are input to selectors 87, 88, and 89.

□ Details of connection switching mode and control code CI, 02
The contents will be explained in detail later, but for the time being, one digital filter circuit device DFC is used alone as the digital filter section 14, and the pole filter 42 is placed in the front stage and the zero filter 46 is placed in the rear stage, and both are connected in series. The explanation will be based on the connection.

In that case, both the control codes CI and C2 are set to the signal "B".The selector 87 selects the input B by "11" of the codes CI and C2, and the selector 88 selects the "1" of the code C2.
” selects input B, and selector 89 selects code C2.
Input B is selected by "1"'. Therefore, the serial musical tone signal Si output from the serial adder 86 of the input control circuit 67 is input as the signal FS to the forward input terminal FSi of the pole filter 42 via the selector 87, and the forward output terminal of the pole filter 42 The output signal of FSo is inputted to the input terminal ZSi of the zero filter 46 via the selector 89, and the forward output terminal FS.

A signal obtained by delaying the output signal by 32 time slots in the delay circuit 72 is fed back to the reverse input terminal BS of the polar filter 42 via the selector 88. In this way, the pole filter 42 is placed at the front stage and the zero filter 46 is placed at the rear stage, and both are connected in series.

The timing signal generation circuit 40 generates predetermined timing signals KL, L for controlling the serial filter operation based on the synchronization pulse 5YNC input via the terminal T1.
D, SH, and the channel selection code K c h synchronized with the time division timing of each filter channel ch1 to ch4 in the serial filter coefficient K, and each filter channel C in the serial musical tone signal S□ to S3.
A channel selection code Sch synchronized with the time division timing of h1 to ch4 and a synchronization pulse KSYNC for serializing filter coefficients are generated, respectively. The timing signals *L, LD, and sH are sent to the first stage filter unit L1 of the polar filter 42 via the line 95 (see FIG. 9).
supplied to The serial data of the filter coefficients output from the filter coefficient supply circuit 41 is also supplied to the first stage unit L1 of the polar filter 42. As described later,
The serial filter coefficient data is sequentially shifted through each stage in the polar filter 42, then enters the zero filter 46 via line 93, is sequentially shifted in each stage within this zero filter 46, and is finally transferred from the serial format. It is converted into a parallel format, and 1 to Kl are distributed to each coefficient in a predetermined stage.

Timing signals KL, LD, and SH are used to convert the serial filter coefficient K into parallel.

Therefore, these signals KL, LD, and SH are also provided to the zero filter 46 via line 94. As will be described later, the signal KL is applied to each stage of the filters 42 and 43 at the same time, but the signals SR and LD are sequentially shifted at each stage similarly to the serial filter coefficients.

An example of each of the timing signals KL, 'LD, and SH input to the first stage of the pole filter 42 via the line 95 is shown in FIG. Also, the time-division channel states (time-division channel states 1chj to ss1 to S3) of the serial musical tone signal FS inputted to the first stage filter Ll of the polar filter 42 via the selector 87
4 fz is shown in the FS column of FIG. Similarly, in the column K in FIG.
~ch4 is shown. In FIG. 14, the numbers written along with the signal waveform diagram indicate the numbers (corresponding to FIG. 11(a)) indicating the order of time slots within one sampling period. Details of the signal FS and data shown in FIG. 14 are as shown in FIG. 11(b) and FIG. 12(a).

Serial filter coefficient data K and timing signal KL
, LD is repeated with five sampling periods of the musical tone signal FS as one cycle. Assuming that each of these five sampling periods is the first to fifth sampling period, the timing signal KL is applied to the 23rd time slot of the first sampling period and the 4th time slot of the second sampling period.
7 time slots, the 71st time slot of the third sampling period, and the 95th time slot of the fourth sampling period. is a signal with one period of 120 time slots like KL, and is delayed by l time slots and 2
Kurunu is the signal that is generated. In the serial filter coefficient data K, 120 time slots are allocated to the filter coefficients of one channel as described above. First, the filter coefficient K of channel ch1 is assigned to 120 time slots from the 23rd time slot of the first sampling period to the 46th time slot of the second sampling period, and thereafter, the filter coefficient K of channel ch1 is assigned to 120 time slots in synchronization with the timing of signal KL. channel for each
2. ch3. The coefficient K of ch4 is sequentially assigned.

The timing signal 5I-I has a period of 24 time nullots and the 24th. No.48゜No.72. This occurs repeatedly every 96th time slot.

A channel selection code I (ch indicates the code content indicating each channel Ch1 to ch4 in synchronization with the time-division channel timing of the filter coefficient as shown in the column of FIG. 14) generated from the timing signal generation circuit 40. .

The other channel selection code SCh is applied to each channel Ch1 to c in synchronization with the time-division channel timing of the serial musical tone signal FS as shown in the FS column of FIG.
The code content indicating h4 is shown.

The filter coefficient supply circuit 41 has a filter coefficient ROM 97.
and a circuit for controlling reading of this ROM 97 according to the tone parameter TP3. The circuit for controlling the readout of RC) M97 according to the tone parameter TP5 includes a shift register 98 and a latte circuit 99.
, a writable and readable random access memory (hereinafter referred to as RAM) 100, and a selector 101.

The timbre parameter TP6 is composed of a serialized parameter f-data PD, and the shift register 98 and latch circuit 99 function as a serial/parallel converter for parallel-to-parallel conversion of this serial data PDk. The timbre selection device 12 (FIG. 1) outputs the serialized parameter data PD and a timing pulse PE indicating the reference timing of serialization as information shown in the timbre parameter TP3, and outputs the serialized parameter data PD and the timing pulse PE indicating the reference timing of the serialization, and outputs the serialized parameter data PD and the timing pulse PE indicating the reference timing of the serialization as information shown in the timbre parameter TP3. The signal is supplied to the digital filter section 14 via T3. In this way, the timbre parameter T
P3'(z) It is advantageous because the wiring from the timbre selection device 12 to the digital filter section 14 can be simplified by converting it into serial data.

An example of the tone color selection device 12 is shown in FIG. A plurality of tone color selection switches TC-3W are provided, and their outputs are input to the encoder 102. When the player operates one of the tone color selection switches TC-8W, a code signal indicating that switch is output from the encoder 102.

Further, when the switch TC-8W is operated, a load pulse is applied from the AND circuit 104 to the load control input of the launch circuit 106, and the output code signal of the encoder 102 is taken into the latch circuit 106. Launch circuit 1
The code signal latched to No. 06, that is, code No. 18 indicating the selected timbre, is applied to the address input of the timbre parameter memory 105. Tone parameter memory 105
data indicating tone color parameters corresponding to various selectable tone colors is stored in advance, and tone color parameter data corresponding to the selected tone color is read out in accordance with a code signal given from the latch circuit 106. Of these, the parameter data TP3 to be applied to the digital filter section 14 is input in parallel to the latch circuit 106. The AND circuit 104 is used to manually control the load of the latch circuit 106.
The load pulse output from the delay flip-flop 1
07. Therefore, the latch timing of the latch circuit 106 is slightly delayed from that of the latch circuit 106. This means that the timbre parameter TP3 corresponding to the code signal latched by the latch circuit 106 is
The latch circuit 10 waits for the data to be reliably read from 05.
This is to perform the latch operation of No. 6.

The timbre parameter TP3 is, for example, digital data of lO pits, of which 5 bits are a timbre code TC representing the selected timbre, and 3 bits are each sub-sequence #1.
~#6 musical tone signals S□~S3 that indicate which one should be passed through the digital filter main circuit 68.Feeler enable signal FE1°FE2. FE3, and 2 bits indicate which series (USL, US
P.

UO3, LSP), that is, which filter channels ch1 to ch4 should be given this tone. Latch circuit 10
6 has 10 latching points, and the parameter TP
3 bits respectively. The output signal of each latch point of the latch circuit 106 is transmitted through ten AND circuits 108, 1
Both inputs on 09 and 110 were done manually.

The shift register 111 has 11 stages and sequentially shifts the pulse signal applied to the first stage from the delay flip-flop 107 in accordance with the clock pulse φ. The output signals from the first stage to the first O stage of the shift register 111 are output from ten AND circuits 108,1.
09 and 110, respectively. The outputs of each AND circuit 108゜109.110 are all OR circuit 11
2, and this OR circuit 112
The output signal is the serial data P of the tone parameter TP3.
The signal D is applied to the digital filter section 14. The output signal of the 11th stage of the shift register 111 is applied to the set signal S of the flip-flop 116, and is also applied to the digital filter section 14 as a timing node PE.
given to.

The shift timings of input signals in the shift register 111 are indicated by 1 to 11, and an example of the state of the serial data PD corresponding to these timings is shown in FIG. Further, the timing pulse PE is generated at timing 11 as shown in the figure, that is, immediately after the sending of the serial data PD is finished.

All tone selection switches TC-3 are included in the OR circuit 114.
The output signal of W is inputted, and when any one of the knobs is pressed, the output of the OR circuit 114 becomes a signal "1". The output signal of the OR circuit 114 is applied to the AND circuit 104 and also to the reset input R of the flip-flop 113. The output Q of the flip-flop 116 is delayed by one period of the clock pulse φ by the delay flip-flop 115 and then applied to the AND circuit 104 . Normally, the flip-flop 116 is in the cent state, and the AND circuit 104 is operable. When the tone selection switch T C-SW is pressed, the AND circuit 104 responds to the rise of the output signal of the OR circuit 114.
The output becomes the signal "1". flip flop 11 at the same time
After one cycle of the clock pulse φ, the output of the delay flip-flop 115 falls to "0", and the AND circuit 104 becomes inoperable. Therefore, AND circuit 1
04 outputs a short parnu with a time width of one cycle of the clock pulse φ at the moment the tone selection switch T C-SW is pressed. Based on the output pulse of the AND circuit 104, the serial data PD and timing pulse PE are sent out as described above. When timing pulse PE occurs, flip-flop 116 is set. This sets the AND circuit 104 in an operable state so that it can generate a load pulse the next time the tone selection switch TC-8W is pressed.

The tone selection device 12 further includes various musical tone control operators 11.
6, and a parameter generating circuit 117 generates a predetermined tone parameter in accordance with the operation of this operator 116. Among the parameter data other than the filter control tone parameter TP3 read from the tone parameter memory 105 and the parameters output from the parameter generation circuit 117, predetermined ones are the tone parameters TPI, T.
P2. A musical tone signal generating section 11 as TP4. Control circuit 1'
6, respectively supplied to the external storage device 20. These tone parameters TP1. TP2. TP4 may be supplied in serial data format like TP3.

In FIG. 15, the timbre selection device 12f is shown as being constituted by a discrete circuit, but the process is not limited to this and may be processed by a microcomputer system. In that case, the keyboard section 9 and key assigner 10 (FIG. 1) can also be processed by a microcomputer system.

Returning to FIG. 13, the 7 real data PD of the timbre parameter TP3 is input to the shift register 98. The shift register 98 has 10 stages and performs shift control in synchronization with the time-division time slots of the serial data PD using a clock pulse φ. Timing pulse PE is applied to the load control input of latch circuit 99. The output of each stage of the /ft register 98 is input in parallel to the latch circuit 99, and when the timing pulse PE is supplied, the state of the output signal of each stage is input to the latch circuit 99.
It is latched to 9. Since the relationship between the serial data PD and the timing pulse PE is as shown in FIG. 16, the channel code CH enters the 11th and 2nd stages of the shift register 98, and the filter enable signal enters the 3rd, 4th, and 5th stages. F'E3. FE2. , FEl are input, and when the tone color code TC is input to the sixth to first O stages, a timing pulse PE is supplied so that these data are reliably latched in the latch circuit 99.

The RAM 100 is for storing tone codes TC corresponding to each filter channel ch1 to ch4,
The RAM 118 is for storing filter enable signals FE1-FEB corresponding to each filter channel Ch1-ch4. The RAMs 100 and 118 have storage locations (addresses) corresponding to each channel ch1 to ch4. A signal obtained by delaying the timing pulse PE by a delay flip-flop 119 is applied to the write control W of the RAMs 100 and 118. Channel code CH latched by latch circuit 99 is applied to write address designation input WAD.

The tone color code TC latched by the launch circuit 99 is input to the data input of the RAM 100. Filter enable signals FE1 to FE3 latched by the latch circuit 99 are input to the data input of the RAM 118. New data TC in latch circuit 99.

FE1-FE3. RAM100 immediately after CH is imported.
．． 118 enters the write mode, and the tone code T is written to the address specified by this new channel code CH.
C and signals FE1 to FE3 are written respectively. In this way, each time a tone selection operation is performed (data PD, PE
data is written to RAMs 100 and 118, and finally each filter channel ch1 to c
The tone code TC of the tone selected corresponding to h4 is RA
M100, and filter enable signals FE1 to FE3 of selected tones corresponding to the filter channels ch1 to ch4 are respectively stored in the RAM 118.

Read address designation of RAM 100 The manual RAD contains channel selection codes K for each channel ch1 to ch4.
Ch is provided in a time-divisional manner by the timing signal generating circuit 4o. RAM118 read address specification manual RA
D also has a channel selection code Sch from circuit 4o.
is given in a time-sharing manner. The RAMs 100 and 118 are of a type that can be written to even while being read. Channel selection code Kch
is for each channel ch1~c as shown in the column of Figure 14.
A code signal indicating h4 is generated in a time-division manner with a width of 120 time slots per channel. RAM1
00 corresponds to each channel ch1~ according to this code Kch
The tone color code TC of ch4 is read out in a time-division manner. on the other hand,
As shown in the FS column of FIG. 14, the channel selection code Sch is a code signal indicating each channel ch1 to ch4 that is generated in a time-division manner with a width of 24 time slots per channel. The RAM 118 reads out the filter enable signals FEj to FE3 of each channel chj to ch4 in a time-division manner according to this code SCh.

The tone code TC read from RA and Mloo is applied to the control input of the selector 101. The selector 101 selects the filter coefficient ROM 97 according to the contents of the tone code TC.
Select the filter coefficients read from . The filter coefficient ROM 97 stores in advance sets of filter coefficients corresponding to various tones selectable by the tone color selection device 12. As mentioned above, one set of filter coefficients corresponding to one timbre consists of 15 filter coefficients from 1 to 15, and since one filter coefficient is 8 bits, one set of filter coefficients is 120 bits of data. be. Since the number of tones that can be selected by the 5-bit tone color code TC is 32, the ROM 97 stores, for example, 32 sets of filter coefficients. A synchronizing pulse KSYNC for reading filter coefficients generated from the timing signal generation circuit 40 is supplied to the ROM 97. ROM97 is synchronized pulse K
At a predetermined timing based on SYNC, a set of filter coefficients consisting of 120 bits is sequentially read out one bit at a time/real time, and the seven real readings in parentheses are performed simultaneously and in parallel for all tones. , the states of each set of serial filter coefficient data read out in parallel are as shown in FIG. 12(a).

Serial data of filter coefficients for each tone color read from the ROM 97 is input to the selector 101. The selector 101 selects a set of serial filter coefficient data according to the timbre code TC given from the RAM 100 in a time-division manner. In synchronization with the time width of 120 time slots in which the tone color code TC for one channel is applied to the selector 101, serial readout of one set of filter coefficients for 120 bits is repeatedly performed in the ROM 97. On the other hand, the contents of the tone code TC read from the RAM 100 are the channel selection code K c
It changes in a time-division manner every 120 time nulls according to h. Therefore, seven real data of four sets of filter coefficients corresponding to the timbre selected for each filter channel Ch1 to ch4 are output from the selector 101 in a time-division manner every 120 time slots. The channel state of the serial filter coefficient data output from this selector 101 is the same as that shown in the column of FIG.

The output of selector 101 is given to input A of selector 120. 7 real data KO of filter coefficients read from the external storage device 20 (FIG. 1) is applied to the other input B of the selector 120 via the terminal T5. The serial data format of this serial filter coefficient data KO is exactly the same as that output from the selector 101, and is
Serial filter coefficient data for channels ch1 to ch4 are time-division multiplexed as shown in the column of FIG. The B selection control input SH of the selector 120 receives the output signal K of the filter coefficient changeover switch 21 (FIG. 1).
S is applied through the terminal T4, and the inverted version of this signal KS is applied to IJ and A selection control manual SA.

Therefore, depending on whether the switch 21 is turned on or off, either the output of the external storage device 20 or the output of the selector 101 (ie, the output of the ROM 97) is selected. The serial filter coefficient data selected by the selector 120 is input to the first stage filter unit L1 of the polar filter 42 via the line 96.

The filter coefficient external storage device 20 may have a similar configuration to the filter coefficient ROM 97 provided inside the digital filter unit 14, but may be configured to supply filter coefficients that change over time based on the key J1 ON signal KON. It may be a configuration.

An example of the latter type of external storage device 20 is shown in FIG. In FIG. 17, filter coefficient memory 1
Reference numeral 21 stores a plurality of sets of filter coefficients for one timbre in advance, corresponding to a plurality of types of timbres, and a timbre parameter TP4 given from the timbre selection device 12 (FIGS. 1 and 15). selects a plurality of sets of filter coefficients corresponding to l timbres according to
One set at a time is read out sequentially as time passes in accordance with R8.

The address signal generation circuit 122 generates an address signal ADR8 whose value changes over time based on the key-on signal KOH given from the key assigner 10 (FIG. 1), and also generates a pattern of change over time of this address signal ADR8. It is controlled according to the timbre parameter TP4.

Address signal AD in address signal generation circuit 122
An example of occurrence of R8 is shown in FIG. Key-on signal K ON
The address signal ADR8O value becomes "0" in synchronization with the rising edge of
The signal ADR8O value is "0" according to a predetermined attack rate.

It increases sequentially as "1", "2", and so on. When the address signal ADR3O value reaches the predetermined sustain value A8,
The increase in the number stops and the sustain value A8 is maintained. Eventually, when the key-on signal KON falls, the signal ADR8 changes to rA8J, rA8+ according to a predetermined decay rate.
It increases sequentially as IJ, rA8+2J, and so on. When the final value 1'NJ is reached, the increase stops and the key-on signal K
The time change of address signal ADR8 in response to ON ends. The number of sets of filter coefficients stored in the filter coefficient memory 121 corresponding to one tone is N sets, and each set of filter coefficients is read out sequentially in accordance with the address signal ADR8O values "o" to rN-IJ. .

In FIG. 18, the attack rate, decay rate, and sustain value A8 are variably set according to the tone parameter TP4.

Similarly, since the timbre types assigned to each of the filter channels Ch1 to ch4 are known in advance, it is automatically determined to which filter channel Ch1 to ch4 the selected timbre belongs from the contents of the timbre parameter TP4. Therefore, in the filter coefficient memory 121, each channel c
The filter coefficients of the tones selected corresponding to h1 to ch4 can be read and compared in a time-division manner corresponding to each channel timing. In this way, from the filter coefficient memory 121, a set of filter coefficient data consisting of 120 bits is stored in parallel and for each channel ch1.
-ch4 are read out in a time-division manner, and the set of filter coefficients changes over time in accordance with changes in address signal ADR8. Parallel/serial converter 1
26 is 120 read out in parallel from memory 121
It is for converting a set of filter coefficients consisting of bit data into temporally serial data (consisting of 120 time slots). Synchronous pulse 5YNC is used as a reference timing signal during serial conversion. In this way, the serial filter coefficient data KO supplied from the external storage device 20 is as described above.
The data format is as shown in KwA in FIG.

A storage device 20 that supplies a filter coefficient KO that changes over time, as shown in FIG. 17, is useful for realizing a timbre whose frequency characteristics change over time. In particular, since the frequency characteristics of human voices vary slightly over time, it is suitable for supplying filter coefficients for human voices. That is, the filter coefficient memory 121 and the address signal generation circuit 122 may be configured to supply filter coefficients in response to changes in frequency characteristics of desired human voice sounds. In FIG. 18, a constant value A8 is used as the address signal ADR8 in the sustain section to read out a constant filter coefficient, but this is not limited to this. You may also do so. For example, by subtly and periodically changing the address signal ADR3O value in the sustain section,
It is also effective to make the filter coefficients change slightly periodically.

Returning to FIG. 13, the filter enable signals FE1 to F"E read out from the RAM 118 are input to the AND circuits 86 to 85 of the input control circuit 67 and the AND circuits 124, 125, and 126 of the output control circuit 39, respectively. Of the AND circuits 86 to 85, those to which the filter enable signals FE1 to FE3 inputted are 1# become operational, and the corresponding serial musical tone signal (S
□ to S3) are selected and input to the serial adder 86. As mentioned above, RAM11
Filter enable signals FE1 to F read from 8
The timing of E30 channels ch1 to ch4 is the 14th
This corresponds to the channel timing of the serial musical tone signals 80 to S3 as shown in the FS column of the figure. Therefore, the serial musical tone signals S□-S3 of each sub-series are selected in combinations set corresponding to the respective filter channels Ch1-ch4.

To explain the details of the serial adder 86, the adder 127 adds the serial musical tone signal S2 supplied from the AND circuit 84 and the serial musical tone signal S3 supplied from the AND circuit 85, and adds the output signal of this adder 127 and the AND circuit. Serial musical tone signal S1 given from 83
and are added by an adder 128. Adders 127 and 128 are both full adders with carry input C1, and their own carry output C6+ is connected to AND circuits 129 and 130.
They are input to the carry human power Ci via the respective input terminals. It is assumed that there is a time delay of l time slots between the addition timing at which the carry out signal is generated and the timing at which the signal "l" is output from the carry output C8+□. As shown in FIG. 11(b), in the serial musical tone signals S□ to $3, the data of the upper bits is assigned to a later time slot. Therefore, 1
By adding the carry aud signal output from the output C80□ after a time slot delay to the carry human power Ci, the carry aud signal can be added to the upper data of the l pit. The other inputs of the AND circuits 129 and 160 are supplied with a signal obtained by inverting the timing signal S H generated from the timing signal generating circuit 40 by one time slot in a delay circuit 131 and inverting it in an inverter 162 . As shown in FIG. 14, the timing signal 5R4I
i 24th. No. 48゜No. 72. 11' at the 96th time slot, and the output signal of the delay circuit 131, which is delayed by one time slot, is the signal at the 25th time slot. No. 49.
The 73rd and 1st time slots are 11#, respectively.

On the other hand, since the serial musical tone signals S-S3 are as shown in FIG. 11(b), the output signal of the delay circuit 161 is "1'', and the output of the inverter 132 becomes 0''.

As a result, in the serial addition for each channel Ch1 to ch4, the carry signal generated by the operation of the sine pin 1-(SB) of another channel in the time slot of the lowest bin) (LSBI) is
can be prohibited from being given to i.

On the other hand, the control code C2 is input to other inputs of the AND circuits 124 to 126 of the output control circuit 39. As will be described later, when the output signal 2° of the zero fill filter 46 is used as the output musical tone signal of this digital filter circuit device DFC, C2 of the control codes CI and C2 is necessarily determined to be lII. ing. Therefore, when the output signal 2° of the zero filter 43 is used as an output musical tone signal, the AND circuits 124 to 126 are always enabled.
The outputs of the AND circuits 124 to 126 are "l" or "0#" depending on the values of the filter enable signals FE1 to FE3.
becomes. The outputs of the AND circuits 124 to 126 are separately input to AND circuits 90, 91, and 92. On the other hand, signals obtained by inverting the output signals of the AND circuits 124 to 126 are separately input to the AND circuits 133, 164, and 155, and the other inputs of each of the AND circuits 166 to 165 are serial musical tone signals S of each sub-series. □ to S3 are input separately.

The outputs of AND circuits 90 and 133 are given to output terminal O□ via OR circuit 166, the outputs of AND circuits 91 and 134 are given to output terminal 02 via OR circuit 137, and the outputs of AND circuits 92 and 165 are given to output terminal O□. is applied to the output terminal o3 via the OR circuit 138.

When using the output signal 2° of the zero filter 46 as an output musical tone signal, the filter enable signals FE1 to FE
A signal Z outputted from the zero filter 46 corresponding to the channel timing when 3 becomes "l". The AND circuit 90 corresponding to the signals FE1 to FE6 in which is "l"
, 91, 92 to the output terminal o corresponding to each sub-sequence.
1. o2. distributed to o3. In that case, the AND circuits 133, 134, and 135 corresponding to the sub-sequences in which the filter enable signals FEI to FE3 are "0" are enabled, and the serial fundamental tone signals S to S that do not pass through the filter are enabled.
3 is led to the output terminal O, 0□, o3. In other words, the input musical tone signals S1 to S3 are directly guided to the output terminals O to o3 to which the output signal 2° of the zero filter 46 is not distributed.

On the other hand, the output signal Z of the zero filter 46. When not using as an output musical tone signal, code c2 is "0",
AND circuits 136-165 are always enabled, AND circuits 90-92 are always disabled, and input musical tone signals 81-83 are directly guided to all output terminals 01-03.

Pole filter 42 and zero filter 46 in FIG.
The same one as shown in FIG. 9 and FIG. 1θ can be used. By the way, FIGS. 9 and 10 only show the basic configuration, which includes a circuit for converting serial-parallel filter coefficient data K into string data and distributing it to string data 81, and a plurality of channels Ch1 to ch4.
Circuits that enable time-divisional filter operations and circuits that enable serial filter operations are omitted from illustration. Therefore, the filter units) Ll to L of the pole filter 42 having the basic configuration as shown in FIG.
12 will be described in detail with reference to FIG. 19, and then a detailed example of the zero filter 46 will be described.

(Figure 19 shows the first stage filter unit of the polar filter 42)
A detailed example of Ll is shown. The other filter units L2 to L12 also have exactly the same or almost the same configuration. Circuits corresponding to adders 61, 62, 63 and delay circuits 65, 66, 67 in FIG. 9 are given the same reference numerals in FIG. Further, circuit portions corresponding to the multiplier 64 in FIG. 9 are shown comprehensively in FIG. 19 using the same reference numerals.

A coefficient distribution circuit 139 that parallel-converts the serial filter coefficient data K using timing signals KL, LD, and SR and distributes it to the multiplier 64 is omitted in FIG. 9, but is shown in FIG. 19. This circuit 139 will be explained first. In Figure 1, delay circuits that delay l time slots are indicated by +1)1 by blocks marked with the symbol rDJ, and reference numbers for individual one time slot delay circuits are omitted unless specifically stated. do. The coefficient distribution circuit 169 includes delay circuit arrays 140, 142, 143, a latch circuit 141, and a filter coefficient storage device 144. A delay circuit array (that is, an eight-stage serial shift parallel output type shift register) 140 in which eight one-time slot delay circuits are connected in cascade, and this delay circuit array 14
A latch circuit 141 consisting of eight 1-bit type latch circuits each inputting the output of each delay circuit of 0 is used to convert serial filter coefficient data K into parallel. The delay circuit array 140 contains serial filter coefficient data K.
is input. This data is sequentially shifted by each delay circuit and is sent to the next filter unit after 8 time slots.
given to 2.

A timing signal KL is applied to each latch control input of the latch circuit 141, and when this signal KL is "1", the output of each delay circuit of the delay circuit array 140 is latched into each latch circuit. Similarly, in this example, the output timing of the latch circuit 141 is delayed by one time slot from the latch timing.

Similarly to 140, 142 and 143 are delay circuit arrays (series shift parallel output type shift register) in which eight one-time slot delay circuits are connected in series.

A timing signal LD is input to the delay circuit array 142,
A timing signal SH is input to 146. These signals LD and SI (are sequentially delayed by each delay circuit of the delay circuit arrays 142 and 146, and are applied to the next stage filter unit) L2 after 8 time slots.

Delay circuit arrays 140, 142, 143 and latch circuit 14
Circuits similar to 1 are used in other filter units L2 to 1.
2 is also provided. Therefore, 1 timing signal LD is added to the serial filter coefficient data.

SH is sequentially delayed by 8 time slots in each filter unit L1 to L12. On the other hand, the timing signal KL
from each filter unit) Ll to L1 without being delayed.
2 at the same time. Furthermore, the data output from the final stage filter unit L12 of the pole filter 42, KL, KD, and SR, are input to the zero filter 43 through lines 93.94 (FIG. 13). Zero filter 460 three multipliers 73.74.81 as described below
Coefficient distribution circuit 169 in FIG. 19 corresponds to (FIG. 1O).
(Delay circuit arrays 140, 142, 143, latch circuit 14
1, a circuit similar to the storage device 144) is provided,
The timing signals LD and SR are zero-filled and sequentially delayed by 8 time slots each in 4603 calculation stages. Further, the timing signal KL is not delayed and is output to the zero filter 4.
It is simultaneously supplied to each of the 6 processing stages.

Line 9 from the timing signal generation circuit 40 (FIG. 13)
As described above, the pulse generation timings of the timing signals KL, LD, and SH given to the first stage filter unit L1 are as shown in FIG. Also,
The channel timing of the serial musical tone signal FS given from the selector 87 (FIG. 13) to the first stage filter unit L1, and the serial filter coefficient data given to the unit L1 from the selector 120 (FIG. 13) via the RIE/96. The channel timing for 2 is also as shown in FIG.

As is clear from FIG. 14, the timing signal KL is generated immediately after serial transmission of one channel's worth of filter coefficient data is completed. As shown in FIG. 12(a), the serial filter coefficient data for one channel corresponds to the subsequent arithmetic stage (multiplier 81°74.73, filter units L12 to Ll) (K□5. to □ 4.・
...K1) are sent in order. Therefore, when the timing signal KL occurs, the individual pole filter units) Ll
The 8-bit filter coefficients 1 to L12 corresponding to the zero filter operation stage are exactly entered into the delay circuit array (corresponding to 140 in FIG. 19) of the predetermined operation stage corresponding to each. These are respectively latched by latch circuits (corresponding to 141 in FIG. 19) in each arithmetic film. In this way, the serial filter coefficient data K is converted into parallel data from 0 to 0 in the respective predetermined filter units L1 to L12 and the zero filter operation stage.

This parallel data is held in the latch circuit (141 in FIG. 19) until the next latch timing arrives. For example, in the 2nd degree 3rd period of the first sampling period shown in FIG.
When the timing signal KL is generated in the noise slot, the filter coefficient data of channel ch4 is transmitted to each unit)L
1 to L12 and the latch circuit (141 in FIG. 19) of the zero filter operation stage, and then the timing signal KL is latched at the 47th time slot of the second sampling period.
The filter coefficient of channel ch4 is held until this occurs. Therefore, when channels ch1 to ch4 of the filter coefficients output from the latch circuit 141 are shown, the first
It will look like KD in Figure 4.

In FIG. 19, a filter coefficient storage device 144 stores the filter coefficients of each channel ch1 to ch4, respectively, and supplies these to the multiplier 64 in accordance with the timing of the serial tone signal FS of each channel. The filter coefficient storage device 144 includes eight shift registers SR1 to SR corresponding to each bit of the filter coefficient.
Consists of 8. The output of each latch circuit 141 that latches each bit of the 8-bit filter coefficient is applied to the KDi input of the corresponding shift register SR1 to SR8. SR among shift registers SR1 to SR8
1 corresponds to the least significant bit (LSI3) of the filter coefficient, SR7 corresponds to the most significant bit (MSB) of the coefficient, and S
R8 corresponds to the sign bit (SB). Similarly, the 8-bit filter coefficient data is expressed in sine-magnitude format, where the lower 7 bits represent the absolute value of the filter coefficient, and the upper sine-magnitude (SB) indicates the positive or negative sign of the coefficient. "l" indicates negative).

Assume that the weight of the most significant bit (MSB) of the coefficient, that is, the bit corresponding to shift register SR7, is 0.5 in decimal.

Timing signal SH input to filter unit L1
and LD are the SHi input of shift register SR1 and LD
are respectively input to the i input. Further, these signals LD are processed by delay circuit arrays 142 and 143.

SR is sequentially delayed to form shift registers SR2 to S.
It is input to the SHi input of R8 and the LD single-person input, respectively. Similarly, the fifth stage delay circuit 145.1=46 in the delay circuit arrays 142 and 143 is not input to any register,
This is provided to match the calculation time delay in the multiplier 64, which will be described later.

Each of shift registers SR1 to SR8 is configured as shown in FIG. Four delay circuits with a delay time of l time slots 147, 148° 149.150
A four-stage shift register is constructed. KDi is a data input, LDl is a new data acquisition control input, and SHl is a shift control input. New data given to the KDi input is passed through the AND circuit 151 and the OR circuit 160 to the first stage delay circuit 14 when the signal "l#" is given to both the LDi input and the SHi input.
Incorporated into 7. When the SH1 input signal is “0”,
The output of the inverter 164 which inverts this signal is l'', and the AND circuits 153, 155, 157 .
159 is enabled and each delay circuit 147, 148, 14
9. The output of 150 is the AND circuit 153, 155, 15
7.159 and OR circuit 160, 161, 162, 16
Self-retained via 3. When the SHi input signal is 1", the above hold AND circuit 153.155°15
7.159 is disabled and the shift AND circuit 152,
154,156.158 are enabled. This results in
The output Q1 of the first stage delay circuit 147 is sent to the second stage delay circuit 148, the second stage output Q2 is sent to the third stage delay circuit 149, and the third stage output Q6 is sent to the third stage delay circuit 147.
is shifted to the fourth stage delay circuit 150, and the fourth stage output Q4 is shifted to the first stage delay circuit 147. Similarly, a signal obtained by inverting the LDi input signal by the inverter 165 is input to the AND circuit 152, and when new data is taken into the first stage delay circuit 147, the fourth stage output Q4 is shifted to the first stage. It is prohibited to do so. With the above configuration, each time the signal "l" based on the timing signal LD is applied to the LDi input (every 120 time slots), the filter coefficient data is transferred from the filter F-circuit 141 (FIG. 19) to the shift registers SR1 to SR8. Every time the signal "l" that is taken into the first stage and based on the timing signal SR is applied to the SHi input (every 24 time slots), the data in each stage of each shift register SR1 to SR8 is shifted to the next stage. Ru.

Shift register SR1 of the first stage filter unit L1
Looking at this, it is when the timing signal LD is generated that the filter coefficient data of the latch circuit 141 is taken into the l-th stage delay circuit 147 through the KD1 manual operation. That is, in the 24th time slot of the first sampling period, the filter coefficient data of channel ch4 is
In the 48th time slot of the second sampling period, the data of channel ch1 is transferred to the 7th time slot of the third sampling period.
In the 2nd time slot, the data of channel ch2 is taken in, and in the 96th time slot of the 4th sampling period, the data of channel ch3 are taken into the first stage (see SRj of LD, KD, and Ll in FIG. 14). Since the timing signal SH is generated five times during one cycle of the timing signal LD, shifting in the shift register SR1 is performed five times. Therefore, at the 24th time 70 of the first sampling period, the first stage delay circuit 147
The data of channel ch4 imported into the 48.7
Every time the signal SR is generated in the 2,96.24 time slot (see SH in Figure 14), it is shifted to the 2nd stage, 3rd stage, 4th stage, lth stage, and then the second sampling period. At the 48th time slot of
When the data is taken in, the data of channel ch4 that was taken in earlier is shifted to the second stage delay circuit 148.

In this way, the filter coefficient data of each channel ch1 to ch4 is sequentially taken in to each stage (delay circuits 147 to 150) of shift register SR1. One rewrite of the filter coefficient data of each channel ch1 to ch4 in the shift register SR1 is completed in four periods of the timing signal LD, that is, in five sampling periods. This rewriting is repeated every five sampling periods. With the control described above, the outputs Q1, Q2, . Q3. Channels ch1 to ch4 of filter coefficients appearing in Q4 are as follows:
It changes as shown in SR1 of Ll in FIG.

Returning to FIG. 19, the SHi inputs of the other shift registers SR2 to SR8 in the filter unit L1 and the LD
The i input is the S Hi input and L of the shift register SRI.
Signals that are sequentially delayed by one time slot from the signals SR and LD applied to the Di input are added. Therefore, the pattern of change in the outputs Q1 to Q4 of each stage in these shift registers SR2 to SR8 is similar to S of Ll in FIG.
It is the same as that of shift register SR1 shown in R1, but
The timing of the change is sequentially delayed by one time slot. However, since extra delay circuits 145 and 146 are provided between shift registers SR5 and SR6, the timing of change (shift timing) in shift register SR6 is delayed by two time slots from that of SR5.

In this way, the change timing (shift timing) of each of the seven shift registers SR1 to SR8 is sequentially shifted with a delay of eight time slots in total per filter unit.

In the filter unit L1 shown in FIG. 19, the fourth stage output Q4 (see FIG. 20) is taken out as the output Q of the shift registers SR1 to SR8, and is input to the multiplier 64.

Now, the serial musical tone signal FS input from the face input terminal FS-IN (FSi) is inverted by the inverter 166 and applied to the B input of the adder 61. The adder 61 is a full adder, and the musical tone signal fed back from the next stage filter unit R2 via the delay circuit 66 is applied to the A input.

CO+1 is a carry field output, and it is assumed that there is a time delay of l time slots between the addition timing at which the carry field signal is generated and the timing at which the signal "1" is output to the output C8+1.

The high-power signal of the carryout output C6+1 is applied to the C1 input of the adder 61 via the OR circuit 2.

As shown in FIG. 11(b), in the serial tone signal FS, the upper bit data is assigned to a later time slot. Therefore, the carry signal outputted from output C8+□ with a delay of l time slots is
By adding it to one input, the carry signal can be added to the data one bit higher. OR circuit 2
The other input is the first stage delay circuit 1 of the delay circuit array 146.
A signal SH1 output from 67 is applied. This signal SH1 is obtained by delaying the timing signal SH generated by one time slot as shown in FIG.
, "1" in the 49th, 73rd and 1st time slots.
”.On the other hand, the input terminal FS-IN (FS
The serial musical tone signal FS input to i) is shown in FIG.
b), each channel cb1 to ch4
The signal SH1 becomes "l" corresponding to the timing of the least significant bit (LSB) of the serial musical tone signal, and the adder 61 repeatedly adds 1'' at the timing of the least significant bit (LSB). .This sweeping is done at the input terminal FS.
Musical tone signal F given from -IN to B input of adder 61
This is for converting S into a negative value. That is, the musical tone signal FS is inverted by the inverter 166 and 1 is added to its lowest pitch (LSB, ) to convert it into a negative value in two's complement format. It is assumed that negative values of the musical tone signal FS applied to the input terminal FS-IN are also expressed in two's complement format. Therefore, when the musical tone signal FS has a negative value, it is substantially converted into a positive value by the two's complement operation using the inverter 166 and the signal SH1. In this way, the adder 61 adds the musical tone signal applied to the forward input terminal FS-IN from the amplitude data of the musical tone signal fed back to the A input via the backward input terminal BS-IN and the delay circuit 66. The output of 61 is input to delay circuits 16 and 8 and is also applied to the data input of latch circuit 169.

The multiplier 64 corresponds to a portion from an input point P1 shown between the adder 61 and the delay circuit 168 to an output point P6 shown on the output side of an OR circuit 202, which will be described later.

The output signal of the adder 61 indicating the difference between the feedback musical tone signal and the input musical tone signal FS is delayed by 24 time slots in a delay circuit 168 and is applied to the exclusive OR circuit 6. The output of the exclusive OR circuit 3 is given to the A input of the adder 4.

The delay circuit 168, the latch circuit 169, the exclusive OR circuit 6, and the adder 4 convert the output signal of the adder 61, which is expressed in two's complement format, into a sign-magnitude (sign bit and absolute value) format. It is something.

A timing signal SH is input to the latch control input of the latch circuit 169. At the 24th time slot or the 48th, 72nd, and 96th time slots where the signal SH is generated, the adder 61 outputs a signal representing the sign pitch (SB) (see FIG. 11(b)). Therefore, the value of the sign bit (SB) is latched into the latch circuit 169.

The output of this latch circuit 169 is given to exclusive OR circuit 3 and AND circuit 5. For example, in the 24th time slot, the signal for channel Ch1 (SB)'!
When the latched signal is output from the latch circuit 169 during 24 time slots from the 25th time slot to the 48th time slot, the output from the adder 61 at the 1st to 24th time slots is A signal obtained by delaying the signal related to channel Ch1 by 24 time slots is output from delay circuit 168. Therefore, the channels of the sign bit signal output from latch circuit 169 and the signal output from delay circuit 168 match. When the sign bit signal latched by the latch circuit 169 is II OII, that is, positive, the output signal of the delay circuit 168 passes through the exclusive/OR circuit 3 as is, and is output as is from the S output via the A input of the adder 4. '. When the sign bit signal is 1” or negative, the delay circuit 168
The output signal of is inverted by exclusive OR circuit 3. At this time, the AND circuit 5 is enabled by the output "1" of the latch circuit 169, and the AND circuit 5 outputs "1" at the timing of the signal SH1, and the Ci large input II 111 of the adder 4 is output via the OR circuit 6. Given.

This signal SH1 is a signal delayed by the time slot of the timing signal SH'il, and corresponds to the least significant bit. For example, if a signal related to channel ch1 is transmitted to delay circuit 1
In the 25th to 48th time slots output from 68, the signal SH1 is n I at the 25th time slot.
II, and the adder 4 adds 1 to the output signal of the exclusive OR circuit 6 regarding the least significant bit. The carry signal generated as a result of the addition is output from the output CO+1 with a delay of l time slots, and is sent to the AND circuit 7 and the OR circuit 6.
Ci large input is given through. The other input of the AND circuit 7 is a signal S obtained by inverting the signal SH1 by an inverter 170.
H1 is given. At the operation timing of the least significant bit, the AND circuit 7 is disabled by II OII of the signal SH1, and the carry-out signal from the most significant bit of the channel whose operation timing precedes is prohibited. By inverting and adding 1 to the least significant bit in the exclusive OR circuit 3, a negative value expressed in two's complement is converted into an absolute value.

With the above configuration, the output S of the adder 4 is transmitted to the adder 6.
A signal FS' representing the output signal of 1 in absolute value is output. The state of this signal FS' is determined by channels chj to ch.
4 is like FS' in FIG. 14, which is 24 time slots behind the timing of the input musical tone signal FS.

Similar to the signal FS shown in FIG. 11(b), this signal FS' is serial data of 24 bits (time slots) per channel, with the least significant bit (LSB) leading by 1.

The multiplier 64 adds the 24-bit serial data FS' output from the adder 4 to each shift register SR1 to S.
Multiply by the 8-bit filter coefficient output from R8. Serial multiplication of 24 bits and 8 bits normally requires calculation time for 32 time slots, but since time-sharing calculations must be performed for each series every 24 time slots, the multiplication results for the lower 8 bits are truncated and the design The product is calculated for the upper 24 bits including bits. Multiplier 64 includes seven multiplier sections M1 to M7 corresponding to each bit of the absolute value portion of the filter coefficients output in parallel from shift registers SR1 to SR7. These parts M1 to M7 are connected in cascade in sequence. Although detailed drawings of the portions M4, M5, and M6 are omitted, they have the same configuration as the portions M2 and M3.

Each portion Ml to M7 is an AND circuit 171, 172, 173 . . . 174, and each pip) K of the absolute value portion of the filter coefficient outputted from each shift register SR1 to SR7 to each AND circuit 171 to 174.

K2...K7 are input respectively. Also, the parts Ml to M
6 is a cascade-connected delay circuit 175, 176°177.
The output signal FS' of the adder 4 is sequentially delayed by one time slot by these delay circuits 175, 176, 177, etc., and the respective delayed outputs are sent to the AND circuits 172, 173, . ...174 respectively. The AND circuit 171 of the portion M1 receives the undelayed signal F.
S' is applied. Parts M2 to M7 are adders 178,
179. ... 180, and the partial products obtained by each AND circuit 171 to 174 are added to these adders 17.
Add from 8 to 180. The signal FS' is transmitted to each delay circuit 17.
5°17<S, 177, so the weights of the outputs of the AND circuits 171 to 174 for each individual time slot are the same, and therefore the adders 178 to 180
Now we can add partial products of the same weight.

In adders 178-180, the partial products of the individual bits, ie the outputs of AND circuits 172-174, are applied to the A inputs, respectively. A partial product or a sum of partial products is input to the B input via AND circuits 181, 182, 186, . The output of the AND circuit 171 and the output signal SH1 of the innoctor 170 are input to the AND circuit 181. The AND circuits 182, 183... have an adder 178,
The output S of 179... and the above signal SH1 are sent to the delay circuit 1.
Signals sequentially delayed at 84°, 185, 186, etc. are added.

These AND circuits 181, 182, 183, . . . are for discarding lower partial products. Each adder 17
8,179. ...180 carry-out output CO+
1 is input to the carry-in input CI via AND circuits 188, 189=-190. AND circuit 188,1
The other inputs of 89...190 are connected to the delay circuit 1 for the signal SHI.
Signals delayed sequentially at 84, 185, 186, etc. are added. AND circuits 188, 189...190 enable the addition of carry signals related to the same channel, while the carry signals related to the most significant bit of another channel whose calculation timing precedes are added to the least significant bit of the next channel. This is to prevent this from happening.

Delay circuit 191°19 provided between portions M5 and M6
2.193 is AND circuit 1 in parts Ml to M5
81, 182, 183... and adder 178, 179
This is to compensate for the delay in operation. The total calculation operation delay time in these parts Ml to M5 (
(This is less than one time slot) is synchronized with the change in time slots in the delay circuit 192, resulting in a delay of one time slot, and in order to match this, the delay circuits 175, 176, and 177 are delayed. circuit 191
, and a delay circuit 193 is inserted in the path of the delay circuits 184, 185, 186. Further, in order to accommodate this delay, extra delay circuits 145 and 146 are inserted into the delay circuit arrays 142 and 146.

In this way, serial data corresponding to the product of the signal FS' and the absolute value portion of the filter coefficient (bits 1 to 1?) is output from the adder 180 of the portion M7. This adder 18
The output of 0 is applied to the A input of adder 195 via exclusive OR circuit 194. Exclusive OR circuit 194 and adder 195
is for converting the product into two's complement format according to the result of multiplying the signal FS' and the sign bits of the filter coefficients. 8 is the exclusive OR circuit 19 from the shift register SR8 to the data indicated by the filter coefficient (, 5B)
6 is input. The sign bit of signal FS' is latched in latch circuit 169.

The output signal of this latch circuit 169 is transferred to a shift register SR.
A latch circuit 197 is provided to synchronize the output of the latch circuit 169 with the output of the delay circuit array 143.
It is latched at the timing when the output of the eighth stage delay circuit 198 becomes "1". The output of this latch circuit 197 is given to the other input of exclusive OR circuit 196. Since the launch timing of the launch circuit 197 and the shift timing of the shift register SR8 are the same, the sign bit data of the filter coefficient and the sign bit data of the signal FS' regarding the same channel are input to the exclusive OR circuit 196 in synchronization. That will happen. The exclusive OR circuit 196 outputs "1" indicating a negative value when the two sign bits do not match.
When they match, OII indicating positive is output. When the output of this exclusive OR circuit 196 is 0'' and the sign of the sum product is positive, the output of the adder 180 is
and the adder 195 as is, and the AND circuit 199
given to. The output of exclusive OR circuit 196 is '°1'''
In other words, when the sign of the product is negative, the output of adder 180 is inverted by exclusive OR circuit 194 and applied to the A input of adder 195. When the output of the exclusive OR circuit 196 is 01'', the Ci large input of the adder 195 is sent from the AND circuit 200 to the OR circuit 2 at the timing of the least significant bit as described later.
1'' is given through 01. Thus, the product of negative values is converted to two's complement form.

The product expressed in two's complement form is sent from the adder 195 to A of the adder 62 via an AND circuit 199 and an OR circuit 202.
given to the input. The AND circuits 203 and 204 for controlling the supply of the carry-out output CO+1 of the adders 195 and 62 to the carry-in human power Ci are provided for the same purpose as the AND circuits 188, 189°, . . . 190.

A loop consisting of an OR circuit 205, an AND circuit 206, and a delay circuit 207 which inputs the output of the adder 180 is for detecting whether or not all bits of the product are '0''.The signal SH1 is inputted for 7 times. A lot-delayed signal SH8 is applied to the AND circuit 206, and the stored contents of this loop are reset by this signal SH8.If the output of the adder 180 reaches n I II even once, this loop 205, 206 °1'' is stored in .207. When the output of the adder 180 never becomes II I II, that is, when the product is all 1101+, n I II is not stored in the loops 205 to 207, and II
It remains OII. The outputs of the delay circuit 207 and exclusive OR circuit 196 are input to an AND circuit 208.

If the product is not all “0”, the output of the exclusive OR circuit 196, that is, the product of the sign bits, is sent directly to the AND circuit 20.
Pass 8. If the product is all “0”, AND circuit 2
08 is disabled, and the output of the AND circuit 208 becomes 0'' (indicating a positive sign) regardless of the output of the exclusive OR circuit 196. Adder 6 via circuit 202
It is given to the A input of 2. AND circuit 209 outputs signal SH
3 is inverted by the inverter 210, and is enabled only at the timing of the sign bit. Therefore, the output of the AND circuit 208 indicates the sign bit of the product, and when the product is all "0", the sign bit is forced to be '0', that is, positive.

Next, details of the calculation operation will be explained with reference to FIGS. 19 and 21. The time slot column in FIG. 21 shows the 25th to 56th time slots of the first sampling period.
Time slots are shown. Total 3 shown here
Using two time slots, the 24-bit signal FS' for channel ch'l is multiplied by the 8-bit filter coefficient. However, of the 32 time slots, the first 8 time slots (25th to 32nd time slots) are the channels that precede channel C111.
In this part, priority is given to the calculation regarding channel ch4, and the calculation regarding channel chl is discarded.

Therefore, the actual multiplication operation regarding channel chj is performed during a total of 24 time slots from the 33rd to the 56th time slot.

Shift register SR1 is shown in columns Kl to 8 in FIG.
The states of 1 to 8 for each bit of the filter coefficients output in parallel from SR8 correspond to channels Ch1 to ch4.
is shown regarding. The least significant bit Kl of the filter coefficient output from the shift register SR1 is connected to channel Ch1 between the 25th time slot and the 48th time slot, as also shown in Q4 in the SR1 column of Ll in FIG.
From the 49th time slot, it switches to the channel ch2. As mentioned above, the shift timing of shift registers SR1 to SR8 is 1.
Since the time slots are sequentially shifted, the bit 2 output from the shift register SR2 is switched to the bit related to channel ch1 at the 26th time slot, and the bit K3 is output from the shift register SR2.
Regarding items 7 to 7, although not shown in Figure 21,
7. Switch to channel ch1 at the 28th, 29th, 31st, and 32nd time slots, respectively. Then, bit K8 output from shift register SR8 is switched to channel ch1 at the 33rd time slot. Note that because the extra delay circuits 145 and 146 are provided, 6 is the 30th bit in the bit output from the shift register SR6.
The channel is switched to ch1 at the 31st time slot instead of at the time slot.

The column FS' in FIG. 21 shows the state of the signal FS' serially output from the adder 4. As shown in the FS' column of FIG. 14, the signal FS' regarding channel Ch1 is output during 24 time slots from the 25th to the 48th time slot.

FIG. 21 shows the signal FS regarding this channel ch1.
'The timings of each pip) Fl to F24 are shown. Fl is the least significant bit (LSB).

In columns 171 to 174 in FIG. 21, each multiplier section M
AND circuits for partial product calculation of 1 to M7-171 to 17
4 shows the state of partial product calculation regarding channel ch1, which is executed for each time slot. For example, "Fl·KtJ" indicates that the least significant bit Fl of the signal FS' is multiplied by 1 to the least significant bit of the filter coefficient.As is clear from the figure, the AND circuit 171 of the portion M1
Here, the signal FS is applied serially starting from the lower bit.
Each bit FI HF2 ) F 3 . . . F24 of ' is always multiplied by the least significant bit Kl of the filter coefficient.

The timing at which bit Kl is switched to channel chl coincides with the timing at which the least significant bit Fl of signal FS' of channel ch1 is applied to AND circuit 171, that is, it is the 25th time slot, and this 25th time slot From the AND circuit 171, the partial product r
Fl・K+J is output. Therefore, during the 24 time slots (from the 25th to the 48th time slot) in which bit Kl maintains the value for channel Ch1,
As shown in FIG. 21, each bit FI to 24th of the signal FS' and the least significant bit of the filter coefficient! The partial product with ``
Fl−Kl” to “F24・KlJ are AND circuits 171
can be found sequentially. The multiplication of the filter coefficients F2 to F7 by the signal FS' is also performed in the AND circuits 172 to 174 of each portion M2 to M7, respectively, in the same manner as described above. However, the signal FS' is
．． Since each bit is multiplied by 2 to 7 by sequentially delayed values 177, . . . , the calculation timings are sequentially shifted as shown in FIG.

The columns SH1 to SH9 in FIG. 21 show the states of the signal SH1 and the signals SH2 to SH9 obtained by sequentially delaying the signal SH1 by the delay circuits 184 to 187. The signal SH2 output from the delay circuit 184 is also 1 compared to the signal SH1.
The signal SH3 outputted from the delay circuit 185 is delayed by two time slots from the signal SH1. Further, the signal SH5 outputted from a delay circuit (not shown) in the portion M6 is the signal SH1 delayed by seven time slots. The signal SH9 output from the delay circuit 187 of the portion M7 is the signal SH8 further delayed by one time slot.

In the 25th time slot, the AND circuit 181 of the portion M1 is disabled by 'O' of the signal SH1, and the partial product "Fl·Kl" output from the AND circuit 171 is discarded. At this time, in parts M2 to M7, partial products of channel Ch4 whose calculation timing precedes are obtained, and the multiplication result regarding channel c1]4 is output from the multiplier 64.

In the next 26th time slot, the NOI of signal SH2
+ disables the AND circuit 182 of portion M2;
The AND circuit 171 also outputs the partial product “F2・KtJ
The partial product [Fz・Kz
The sum of j, ie the output of adder 178, is truncated. At this time, the partial products of channel ch4 are obtained in parts M6 and M7, and the multiplication result regarding channel ch4 is output from the multiplier 64.

Thereafter, until the 31st time slot, the multiplication results for channel ch1 are truncated by the delayed signal SH3 of the signal 'SH1. That is, in the 31st time slot, the output of the adder (not shown) of the group M6 is inhibited by the signal 5H7 (not shown) delayed by the signal SH1't6 time slots.

At this time, from the adder of this part M6, [F6・K1
+F5・K2+F4・K3+F3・K4+F2・K5+
The sum of partial products F1·Kaj is output. 21st
Referring to the diagram, DingF6・KIJ, “F5・K2J,”F
4.KsJ... is the partial product at the 30th time slot, but as mentioned above, the sum of the partial products of the parts M1 to M5 is delayed by one time slot in the delay circuit 192, so the sum of the partial products of the part M6 is delayed by one time slot. is output at the 31st time slot.

In the 32nd time slot, the multiplication result of channel ch1 is not truncated in portions M1 to M7. Therefore, the adder 180 of part M7 is rFt ·K, +F
The sum of the partial products is 6.K2+F5.K3+...10F1.K7J. However, the output of this adder 180 is input to an AND circuit 199 via an exclusive OR circuit 194 and an adder 195.
99 is inhibited by a 0'' on the signal SH8 which is added to the other input.

Therefore, the multiplication result of channel Ch1 is also truncated in the 32nd time slot. As described above, up to this 32nd time slot, the multiplication result of channel ch4 whose calculation timing is earlier is outputted from the multiplier 64 (from the OR circuit 202 which is its output circuit).

From the 33rd time slot to the 48th time slot, the signals SH1 to SH8 are all 1'', and the AND circuits 181, 182, 183, and 199 are all enabled. Therefore, during this time, the signals SH1 to SH8 are all 1''. The calculated sum of all partial products for channel ch1 is output from the multiplier 64. From the 49th time slot to the 5th time slot
In the 6 time slots, the signals SH1 to SH8 become 110 I+ in sequence, which is the next channel ch
It acts to truncate the partial product with respect to 'l, and ensures that the multiplication result with respect to channel chi is output from the multiplier 64. Therefore, the substantial multiplication results for channel ch1 are output from multiplier 64 in 24 time slots from the 33rd time slot to the 56th time slot.

The timing of each bit S1 to 823 of the serial multiplier output for channel C1]1 is shown in the Mout column of FIG. As is clear from the above, the least significant bit S of the multiplication result output at the 33rd time slot is 0 consisting of the sum of partial products as shown below, and S2 + 83
+ ”°S21 + S22 + S23 is as follows.

S, = p8・K, 10F7・K2+F6・K3+ 10F
2・K7S2””F9・K, +F8・K2+F7・K3
+...10F3・K7S3=1+F9・K2 for F1o-
+F8・K3+ ・10F4・K7S21”F24・K5
+F23・K6+F2□・K7822"l"24・K6
+F23・K7S 23=F24 +7 Note that the most significant bit F24 of the signal FS' is the sign bit of the output of the adder 61, and when it is positive, "0" passes through the exclusive OR circuit 6 as it is, and becomes negative. In this case, "1 knee" is inverted by the exclusive OR circuit 6 and becomes O", so F24 is always 0".

As can be seen from FIG. 21, the signal SH9 becomes 0'' at the timing of the least significant bit S of the multiplication output. Therefore, by inverting this signal SH9 with the inverter 211 and inputting it to the AND circuit 200, the signal SH9 becomes 0''. 1 can be added to the least significant bit of the two's complement conversion in the circuit 195.

Also, loops 205 to 20 for all “0” detection
A signal SH8 is input to the AND circuit 206 of No.7. As can be seen from FIG. 21, the signal SH8 becomes 0'' just before the lowest pix (Sl) of the multiplication output. Therefore, just before the new multiplication result is output from the adder 180 (for example, at 205-207 are reset. If any bit of the multiplication result output from the adder 180 is 0, the delay circuit 207 is still in the next time slot (for example, the 56th time slot) after the output timing of the most significant bit (S23) of the multiplication output. 0” is output from. in this way,
At the time slot following the timing of the most significant bit (823) of the serial multiplier output, all bits of the multiplier output are 0''
It is officially known whether or not. At this time, the AND circuit 209 is enabled by a signal obtained by inverting the signal SH8 by the inverter 210, and data indicating the sign bit of the multiplication output is selected. As mentioned above, this sign bit data is normally the output signal of the exclusive OR circuit 196, but when the multiplication output is all "0", the sign bit data is the output signal If 01 of the delay circuit 207.
It is forcibly set to "0" based on 1.

In this way, the output of the multiplier 64, which is applied to the eight inputs of the adder 62 via the OR circuit 202, is the 23-bit serial data S1 to S2 appearing in order from the least significant bit.
3, the sign bit is assigned to the next time slot. Further, regarding negative values, these multiplication output data Sl to S23 are expressed in two's complement format.

On the other hand, the musical tone signal dFS applied from the delay circuit 65 to the B input of the adder 62 is as shown in FIG. That is, between the first to 24th time slots, the input terminal F
Musical tone signal FS of channel Ch1 given to S-IN
is delayed by 32 time slots in the delay circuit 65, so that the musical tone signal dFS of channel Ch1 is outputted from the delay circuit 65 between the 33rd to 56th time slots. Therefore, the channels of the signals applied to the A input and B input of the adder 62 match, and the multiplier output and musical tone signal of the same channel can be added. By the way, the least significant bit (LSB) of the musical tone signal (this is the signal FS
If the weight of the bit (which has the same weight as Fl) is set to "1" in decimal notation, the lowest bit of the output of the multiplier 64, )
, )S is also a decimal value of "1". This bit S1 is as described above.
It consists of the sum of partial products J. Now, looking at the partial product [F2・K7J, bit F2 is one bit above bit F1, so the weight of ``2'' in lO base is 9, and ``F2・K7J is ``1'' in decimal. Since the weight is , it can be seen that the bit 7 is the weight of the decimal number 1'-0,'5J. In this way, the filter coefficient has 1
Arithmetic processing is performed so that the weight of 7 becomes "o, 5J" in the most significant bit of 7. This means that the absolute value of the filter coefficient is a number less than 1.

The output of the adder 62 is input to the next stage filter unit R2 via the forward output terminal FS-OUT. In the next stage filter unit) R2, its j forward input terminal (19th
A musical tone signal given from the previous stage filter unit L1 via the filter unit L1 (corresponding to FS-IN in the figure) and a shift register (corresponding to SR1 to SR8 in Figure 19)
The same calculation as described above is performed based on the filter coefficients etc. stored in . However, each filter unit L1 to L1
Input terminal FS-IN and output terminal FS-OUT in 2
The time delay of the musical tone signal between the two units is 32 time slots, while the time delay of the timing signals LD and SH is 8 time slots. If the configuration is exactly the same as Ll, the filter coefficients in the multiplier (corresponding to 64 in FIG. 19) will be 1 to 8, and the channel of the signal FS' will be shifted. Therefore, each unit L1 to L12
In order to match the channel/channel of -K8 and signal FS' with the filter coefficient in the multiplier (corresponding to 64 in FIG. 19), the outputs Q of shift registers SR1 to SR8 are
Assume that the stages from which the units are taken out are different for each unit L1 to L12 as follows. That is, in the unit L1, the output Q4 of the fourth stage (see FIG. 20) is taken out as the output Q of the shift registers SR1 to SR8, but in the unit L2, the output Q1 of the first stage is taken out.
, UNITSU) In R3, the output Q2 of the second stage, UNISO)
The stages that are taken out as the output Q are sequentially shifted, such as the output Q3 of the third stage in R4, the output Q4 of the fourth stage in R5, and so on.

FIG. 22 shows the zero filter shown in FIG. 10 in more detail, and the multipliers 73, 74,
81, adders 75, 76, delay circuits 77, 78, 79 .
Circuits corresponding to 80 are given the same reference numerals in FIG. 22 as well. serial filter coefficient data K to timing signal K
Coefficient distribution circuits 212, 213, and 214 for converting into parallel filter coefficient data according to L, LD, and SH and distributing it to each multiplier 73, 74, and 81 are omitted in FIG. This is illustrated in the figure.

The internal configurations of the multipliers 73, 74, 81 and coefficient distribution circuits 212, 213, 214 in each operation stage can be the same as those shown in FIG. 19 (64 and 139). That is, each of the multipliers 73, 74.81 can have the same configuration as the multiplier 64 shown in FIG. 19, and each of the coefficient distribution circuits 212, 213. Circuit 169 (delay circuit array 140
142.143, the part consisting of the latch circuit 141 and the coefficient storage device 144).

Specifically, the input points pl and p2 in the block of the multiplier 76 and the coefficient distribution circuit 212 in the first arithmetic stage are
．． p3. p4. F5 and output point P6. P7. P8
．． P9. plo.

Pll corresponds to the point with the same symbol in FIG. The detailed circuit of the multiplier 64 leading to the output point P6 and the output point F7 shown on the line of the signal SH9 is exactly the same as the detailed circuit of the multiplier 73 in FIG. Also, from the input points P2 to P5 shown on the input lines of the data K and each signal KL, LD, SH in FIG. 19, to the output point) P shown on the output line.
Detailed circuit of the coefficient distribution circuit 169 from 8 to P11 and the second
The detailed circuit of the coefficient distribution circuit 212 in FIG. 2 is completely the same. In addition, in FIG. 19, each shift register SRI to SRI of the filter coefficient storage device 144 in the coefficient distribution circuit 139
Just as the output Q of R8 is input to the multiplier 64, in FIG.
A signal indicating a filter coefficient is input to the filter. Similarly, in the multiplier 74 and coefficient distribution circuit 216 in the second calculation stage and the multiplier 81 and coefficient distribution circuit 214 in the third calculation stage, each input/output point P1 to P11 corresponds to the point with the same symbol in FIG. are doing.

Note that the stage from which the output Q of the shift registers SR1 to SR8 (FIG. 19) in each coefficient distribution circuit 212, 213, and 214 is taken out is the aforementioned polar filter unit L1 to L1.
As in 2, it is assumed to be shifted sequentially. In the last polar filter unit L12, the third stage output Q3 (Fig. 20)
is taken out, the first calculation stage (distribution circuit 212) in the zero filter 43 outputs the output Q4 of the fourth stage.
(Fig. 20) and the second calculation stage (distribution circuit 21
In step 6), the output Q1 of the first stage is taken out, and the output Q2 of the second stage is taken out in the third calculation stage (distribution circuit 214).

In FIG. 22, the last unit of the polar filter 42) L
Serial filter coefficient data K and timing signals KL, L provided via lines 93 and 94 from l2.
D and SH are input to the first stage coefficient distribution circuit 212.

The data K, signals KL, LD, and SH that have passed through the first-stage coefficient distribution circuit 212 are given to the second-stage coefficient distribution circuit 216, and further from the second-stage circuit 213 to the third-stage circuit 21.
given to 4. As mentioned above, data K, signal L D
, S H is 8 in each stage of circuits 212, 213, and 214, respectively.
The time slot is delayed and the signal KL is not delayed.

Finally, the coefficient distribution circuits 212 and 213 of each stage
．． 214 (see FIG. 19), predetermined filter coefficients (13 in FIG.
+ K14 + KI6) for each channel chj~
It is stored for each Ch4.

Incidentally, the states of the timing signals LD and SH input to the first stage of the zero filter 46 are shown as *LD and * in FIG.
Shown in the SH column. The FS column in FIG. 23 shows the channel timing of the musical tone signal FS output from the selector 87 (FIG. 13), as in FIG. 14. Signal LD
and SH are the 12 units L1 to L of the polar filter 42.
12, the signals LD and SH shown in FIG. 14 are delayed by 96 time slots and are input to the first stage of the zero filter 46. Therefore, the timing signal LD with a period of 120 time slots is delayed by 96 time slots as shown by *LD in FIG. 23, but the signal SH with a period of 24 time slots is
is virtually the same as SH in FIG. 14, as shown by *SH in FIG.

The column KD in FIG. 23 shows the channel of the filter coefficient latched by the latch circuit (corresponding to 141 in FIG. 19) of the first stage coefficient distribution circuit 212, which is the same as described above. As shown, it is the same as KD in FIG.

Therefore, the output Q1 of each stage of the shift register SR1 of the least significant bit of the filter coefficient storage device (corresponding to 144 in FIG. 19) in the first stage coefficient distribution circuit 212
The channel status of ~Q4 (see FIG. 20) is shown in the 5RIJ column of ``212'' in FIG. 23.

It will be understood that this is the same state as in the column 5R1J of rLl in FIG. Also, as mentioned below,
The channel state of the serial musical tone signal *FS input to the input terminal ZSi of the zero filter 43 is the same as the channel state of the serial musical tone signal FS input to the pole filter 42 in any case. Therefore, the serial calculation timing in the first stage multiplier 73 of the zero filter 43 is the same as that of the first stage Uniso) Ll multiplier 64 of the pole filter 42.
It is synchronized with the serial calculation timing of

This is advantageous because, as will be described later, when switching the connection combination of the pole filter 42 and the zero filter 46, it becomes possible to switch freely without considering the calculation timing.

On the other hand, the musical tone signal *FS applied to the input terminal ZSi of the zero filter 43 is input to the input B of the adder 75 and the delay circuit 78.
The signal is input to the first stage multiplier 76 via the input point P1 (see FIG. 19). As mentioned above, the multiplication result corresponding to this musical tone signal *FS is output at point P6 with a delay of 32 time slots (see Fig. 19).
is output from. The serial tone signal output from output point P6 is delayed by 64 time slots in delay circuit 77 and then applied to input A of adder 75. The serial musical tone signal given to input A is delayed by 96 time slots (exactly one sampling period) from the timing of the serial musical tone signal *FS given to input B, and the bits of the serial musical tone signals of the same channel have the same weight. are added by an adder 75. The carry output Co+1 of the adder 75 is connected to the carry input C via the AND circuit 215.
given to I. The other input of the AND circuit 215 is given a signal obtained by delaying the signal SH9 (see FIG. 21) outputted from the output point P7 (see FIG. 19) of the multiplier 73 by 64 time slots in the delay circuit 216. . As mentioned above, this signal SH9 is a serial musical tone signal outputted from the output point P6 (OR circuit 202 in FIG. 19) (its timing is shown in M.ut in FIG. 21).
is 0'' when the weight is the least significant bit.Delay circuit 21
Reference numeral 6 is provided to synchronize with the delay operation of the delay circuit 77, and the carry signal generated by the addition of the most significant bit of the preceding channel is converted into a carry signal Ci at the timing of addition of the least significant bit of the next channel. AND circuit 215 to prevent input
is provided.

The serial musical tone signal *FS delayed by 128 time slots in the delay circuit 78 is input to the input point P1 of the second stage multiplier 74.

When performing unreal multiplication using the coefficient distribution circuit (139) and multiplier (64) configured as shown in FIG.
Synchronize the serial operation timing in the multiplier (
As is clear from the above, in order to synchronize the serial musical tone signal to be multiplied with the channel of the filter coefficient and the weight of each bit, the input timing of the serial musical tone signal is delayed by 32 time slots from the input timing of the previous stage multiplier. must be maintained. Therefore, the second stage multiplier 7
Comparing the musical tone signal input timing of No. 4 with that of the first stage multiplier 73, the input timing of the second stage is divided into 1 sampling period (96 time slots) and 32 time slots (total 128 time slots) by the delay circuit 78. ), the condition of a delay of 32 time slots is satisfied. Therefore, the second stage multiplier 7
4, the serial calculation timing can also be synchronized.

The serial musical tone signal, that is, the multiplication result output from the second stage multiplier 74 (output point) P6 (see FIG. 19) is delayed by 32 time slots in the delay circuit 79 and then applied to the input A of the adder 760. . An input B of the adder 76 is supplied with the output S of the adder 75 at the previous stage. Similarly to the above, the signal SH9 output from the output point ) P 7 (see FIG. 19) of the multiplier 74 is delayed by 32 time slots in the delay circuit 217 in synchronization with the delay time of the delay circuit 79, and then outputted by the AND signal. It is input to circuit 218 . The other input of the AND circuit 218 is the carry output CO+ of the adder 76.
1 is given, and its output is given to the carry human power Ci. This delay circuit 217 and AND circuit 218 perform the same functions as the circuits 215 and 216 described above. The delay circuit 79 is
As described above, this is to ensure that the timing of the signal input to input A of adder 76 is delayed by two sampling periods (192 time slots) from the timing of input signal *FS. That is, by setting a delay of 128 time slots in the delay circuit 78, a delay of 32 time slots in the multiplier 74, and a delay of 32 time slots in the delay circuit 79, a delay of 192 time slots in total is set.

The output signal of adder 76 is delayed by 64 time slots in delay circuit 80 and then input to multiplier 810 input point P1. A serial musical tone signal is output from the output point P6 of the multiplier 81 at a timing delayed by 32 time slots from the timing of the input point P1.
This is applied to the output terminal 280 as the output musical tone signal Zo of the zero filter 46. The delay circuit 80 is configured to set a time delay of 32 time slots between the musical tone signal input timing of the second stage multiplier 74 and that of the third stage multiplier 81 for the same reason as described above. It has been established. That is, a time delay of 32 time slots is set inside the multiplier u74, a time delay of 32 time slots is set in the delay circuit 79, and a time delay of 64 time slots is set in the delay circuit 80, for a total of 1 time slot.
A delay of 28 time slots is set between the two. 1
Since 28 time slots are 1 sampling period (96 time slots) and 32 time slots, there are essentially 32 time slots between the musical tone signal input timing of the second stage multiplier 74 and that of the third stage multiplier 81. This means that a time slot delay is provided.

Comparing the timing of the input signal *Fs of the zero filter 46 and the output signal Zo, it is found that the delay circuit 78, the multiplier 74,
A total of 288 time slot delays are provided by the routes of the delay circuits 79 and 80 and the multiplier 81, which is exactly 3 sampling periods, so the timing of the input signal *FS and output signal Zo (channel and serial data The timing of each bit's weight is completely synchronized. Therefore, the output signal zo is as shown in FIG. 14 or 23.
This is a serial musical tone signal completely synchronized with the FS timing shown in the figure.

Incidentally, the timing of the serial musical tone signal output from the forward output terminal FS of the final stage UNISO L12 of the polar filter 42 is also completely synchronized with the FS shown in FIG. tsutp,
Since the musical tone signal is delayed by 32 time slots in each of the 12-stage units 1 to L12, the total delay time is 384 time slots, which is exactly 4 sampling periods, so that the forward input terminal of the polar filter 42 F.S.
The timings of the serial tone signal of i and the forward output terminal FSO are synchronized. As shown in FIG. 13, either the signal at the output terminal FSo of the pole filter 42 or the serial musical tone signal Si output from the input control circuit 37 is selected by the selector 89, and the signal at the input terminal ZS of the zero filter 43 is selected.
given to i.

Therefore, the timing of the serial tone signal *FS input to the zero filter 43 via the input terminal ZSi is synchronized with the FS shown in FIG. 14 in any case, as described above. Therefore, the serial musical tone signals Sl to S3 input from the input terminal 1-I3 in FIG. 13 and the input control circuit 37
a serial musical tone signal SI output from the serial musical tone signal SI, a serial musical tone signal FS input from the selector 87 to the polar filter 42,
The timing of the serial musical tone signal outputted from the output terminal FSo of the pole filter 42, the serial musical tone signal *FS inputted to the input terminal ZSi of the zero filter 43, and the serial musical tone signal zo outputted from the output terminal ZSo of the zero filter 46 ( The timings of the channels and the weights of each bit of serial data are all synchronized, as shown in the FS column of FIG. 14 or FIG. 23.

In Fig. 1, the digital filter section 14 can be constructed by using a digital filter circuit device DFC as shown in Fig. 13 alone or by appropriately combining a plurality of digital filter circuit devices DFC. In FIG. 13, a control code c1. It is controlled to one of four states by c2. Control code c1. By using one or more digital filter circuit devices DFC controlled to a desired state according to c2, combinations of pole filters and zero filters can be realized in various variations.

An example of four states of the digital filter circuit device DFC corresponding to the contents of the control codes CI and C2 is shown in the table below.

Table 2 The truth values of the control codes C1°C2 are shown in the cl and C2 columns of the above table. The ``type of rDFC'' column shows the identification code of the digital filter circuit device DFC corresponding to each state. The "Status" column shows the connection combinations of the pole filter 42 and zero filter 43 and the reference numbers of the input/output terminals used for inputting and outputting musical tone signals.

"Pole" only indicates that only the pole filter 42 is used, "Zero → Pole" indicates that the zero filter 46 is the first stage and the pole filter 42 is the second stage, and is connected in series.
"Pole→zero" indicates that the polar filter 42 is placed at the front stage and the zero filter 46 is placed at the front stage and connected in series.

The control code c1 is input to the control input of the selector 87 in FIG.
．． c2 has been input, and input A as shown in the table below according to the contents of this code c1°C2.

Select either B or C.

Table 3 Selector 87 Further, control code C2 is input to the B selection control input SB of the selector 88, and a signal obtained by inverting this code C1 is input to the A selection control input SA. Similarly, the selector 89
Code C2 is input to selection control input SB, and an inverted signal of code c2 is input to selection control input SA.

Control code is CI = “O”, C2-”O” (7)
To explain the case, as shown in Table 3 above, the selector 87 selects the input A, and the serial musical tone signal applied to the input A from the outside via the input terminal Fi& is output from the selector 87 and is output as the signal FS. It is applied to the forward input terminal FSi of the filter 42. In the selector 88, manual power A is selected by code c2 0'', and input terminal B
A signal applied to the input A from the outside via the selector 88 is outputted from the selector 88 and applied to the reverse input terminal BSi of the polar filter 42. In the selector 89, the input A is selected by "0" of C2, and the serial musical tone signal Si is input to the zero filter 43, but the output signal zo of the zero filter 43 is prohibited from being output by the output control circuit 39, and the selector 87 However, since it is not selected, zero filter 46 is effectively not used. In the output control circuit 39, the AND circuits 124 to 126 are always disabled by 0'' of the code C2, and thereby the AND circuits 90 to 92 are always disabled, and the output of the zero filter output signal Zof is prohibited.Therefore,
The state of the digital filter circuit device DFC is such that a serial musical tone signal input from the outside via an input terminal Fi is passed through a pole filter 42, and an output signal of the pole filter 42 is sent to an output terminal F. output to the outside via the zero filter 43
is virtually unused. The device DFC in this state is indicated by IDFc-IJ as shown in Table 2, and it consists of only the 12-stage lattice type polar filter 42 as described above. However, the last filter unit) L1
The reverse input terminal BSi of No. 2 has its own forward output terminal FS via a delay circuit 72.

A signal given from the outside is inputted through the input terminal Bi instead of the output of the input terminal Bi. This means that the filter system is not completed with the pole filter 42 alone, but that a lattice filter is added at a later stage (to terminals F and Bi).

Control code is c1=”1”, C2-”0
”, as shown in Table 3 above, the selector 87 selects the input C, and the output signal 2° of the zero filter 46 is used as the signal FS to be sent to the input terminal F of the polar filter 420.
Give to Si. The selector 88 selects the manual power A by C2's °'0'', and similarly to the above, the signal applied from the outside via the terminal Bi is sent to the reverse input terminal B of the polar filter 42.
Give to Si. The selector 89 selects the input A by 0'' of C2, and the serial musical tone signal Si given from the input control circuit 67 is passed through the selector 89 to the zero filter 4.
6 input terminal ZSi. In the output control circuit 39, '0' of C2 prohibits the zero filter output signal zo from being guided to the output terminals 01 to 03, as described above.Therefore, the state of the digital filter circuit device DFC is different from that of the input terminal. The serial musical tone signal Si given through the input control circuit 37 from ~■3 is passed through the zero filter 46 through the selector 89, and the zero filter 43
The output signal Zo is passed through the selector 87 to the pole filter 42.
The output signal of this polar filter 42 is passed through the output terminal F.

The state is such that it is output to the outside via . In other words,
As in the type l'-DFC-['' in Table 2, the zero filter 46 is connected at the front stage and the pole filter 42 at the rear stage. However, the reverse input terminal BSi of the last filter unit L12 of the polar filter 42 is given a signal from the terminal B1 instead of the delay circuit 72, as described above. Therefore, in this case as well, the terminals F and Bi
) means that a lattice filter is added.

To explain the case where the control codes are c 1 = "o" and C2 = "l", the selector 87 selects the input Ai as shown in Table 3 above, and outputs the serial musical tone signal given from the outside via the input terminal Fi. It is input to the polar filter 42 as a signal FS. In selector 88, C2 °'1"
Shift input B is selected, and a signal obtained by delaying the output signal of its own facial output terminal FSo by 32 time slots is input to the reverse input terminal BRi of the polar filter 42.

In the selector 89, the 1" of C2 causes the pole '
The serial musical tone signal given from the output terminal FSo of the filter 42 is selected and input to the zero filter 46. In the output control circuit 39, the AND circuit 124 is
-126 are enabled, and as described above, AND circuits 90-92 are enabled according to filter enable signals FEi-FE3, and the output signal Zo of zero filter 46 is distributed to output terminals 01-03. Therefore, the state of the digital filter circuit device DFC is such that the serial musical tone signal applied from the outside via the input terminal Fl is passed through the pole filter 42 via the selector 87, and the output signal of this pole filter 42 is passed through the selector 89. The output signal of the pole filter 42 is returned to its own reverse input terminal BSi via the delay circuit 72 and selector 88, and the output signal 2° of the zero filter 43 is passed through the output control circuit 69 to each A state is reached in which the signals are distributed and output to the output terminals O1 to O3 for each sub-series. [DFC-] in Table 2 above
1, the polar filter 42 is connected to the zero filter 4 at the front stage.
3 is connected to the subsequent stage, a musical tone signal is input from the input terminal Fi, and a musical tone signal is output from the output terminals 0, .about.03.

To explain the case where the control codes are c1=''1'' and C2="l'", the selector 87 selects input B as shown in Table 3 above, and the input control circuit 37 is connected from the input terminals Il to ■3. A serial musical tone signal Si given through the filter is outputted, and this signal Si is inputted to the polar filter 42 as a signal FS. In the selectors 88 and 89, the input B is selected by the 1'' of C2 in the same manner as described above.In addition, the output control circuit 69 also selects the input B by the 1'' of C2 as described above.
”, the output signal 2° of the zero filter 43 becomes the signal FE1.
-Distributes to output terminals O1-03 according to FE3. Therefore, the state of the digital filter circuit device DFC is such that the serial musical tone signal Si applied from the input terminals 1 to 3 through the input control circuit 67 is input to the polar filter 42 through the selector 37, and the polar filter 42 is input to the zero filter 46 via the selector 89, the output signal of the pole filter 42 is returned to its reverse input terminal BSi, and the output signal 2° of the zero filter 46 is input to the output control circuit 69. Then, the signal is distributed and outputted to the output terminals O1 to O3 for each sub-series. That is, as shown in "DFc-■j" in Table 2 above, the polar filter 42 is at the front stage, the zero filter 46 is at the rear stage, musical tone signals are input from input terminals Il to ■3, and musical tone signals are input from output terminals 01 to 03. will be output.

In addition, in the above-mentioned types DFC-1 and DFC-II of the digital filter circuit device DFC, since the code C2 is 0'', the AND circuits 133 and 13 of the output control circuit 39
4,135 are enabled at all times. Therefore, input terminal 11
All the serial musical tone signals given to the circuits 1 to 3 are always guided to the output terminals 01 to 03 via AND circuits 133 to 135 and OR circuits 136 to 138. On the other hand, D.F.C.
-■ and DFC-IVO types, code C2 is 1″
Therefore, as mentioned above, the filter enable signal Fi
1 to FE3, only the sub-series serial musical tone signals that are not passed through the filter are led to output terminals 01 to 03 via AND circuits 166 to 165 and OR circuits 166 to 138.

As shown in FIG. 13, a control code generator 219 is provided in connection with the digital filter circuit device DFC, from which control codes CI and C2 are generated and applied to each selector 87.
-89 and AND circuits 124-126. This generator 219 is constituted by a ROM, for example, and the device D
Occurrence code c1. The truth value of c2 may be fixed. In addition, a switch output signal or the like is added as an address input from the outside, and the generated code c1. c2
It may also be possible to freely switch the truth value of . In addition, desired control from the outside: ff-)”01.C2
may be supplied directly.

Next, one or more digital filter circuit devices DFC
Some examples of the digital filter unit 14 configured by combining the following are shown below.

The filter configuration in the digital filter section 14 is
4(a), a one-chip digital filter circuit device DFC of the DFC-■ type is used alone as shown in FIG. 4(a). As mentioned above, the device DFC
If it is of type DFC-1'%I, the pole filter 42 is the first stage and the zero filter 43 is the second stage, as shown in FIG. The output signal of the zero filter 43 is input to the pole filter 42 via the circuit 37, and the output signal of the zero filter 43 is input to the output terminals 01 to 0.
Output from 3. In the same figure (b), terminals 11 to 01, , 01 to o3, which are connected to external circuits are shown. Only T1 to T5 are shown. Therefore, the terminal Fl +Fo (not shown)
, BI, and Bo (see the first diagram) are not connected anywhere when the DFC is used alone. In addition, in the same figure (b), control codes CI and C2 in type DFC-1 are shown.
The truth value of is added. The reason why cl and c2 are shown as being input by broken line arrows is to show that they may be input from the outside, as described above.

The same illustrative method as described above is also adopted in FIG. 25) and FIG. 26). This single use type DFC-
IV has a filter configuration in which a 12-stage lattice pole filter (42) and a second-order zero filter (46) are connected in series, and filter characteristics corresponding to the filter configuration are obtained.

When the filter configuration is as shown in FIG. 25(a), the digital filter section 14 is configured using two digital filter circuit devices DFC of DFC-u and DFC-[1 type, as shown in FIG. 25(a). . As mentioned above, DFC-I
In the T type, the zero filter 43 is the front stage and the pole filter 42
is the latter stage, the musical tone signal input terminals are I to ■3, and the output terminal is F. On the other hand, in the DFC-m type, the pole filter 42 is at the front stage and the zero filter 43 is at the rear stage, the musical tone signal input terminal is Fl, and the output terminals are O1-03.

Therefore, as shown in FIG. 3(b), a DFC, -1 type output terminal F is used. IDFc-111 type input terminal Fi
Connect the input terminal Bi of the DFC-II to the output terminal Bo of the DFC-■, and connect the output terminals O1 to 03 of each sub-series of the DFC-11 to the input terminals 1 to I of the DFC-II.
Connect to 3. Then, as shown in FIG. 4A, a second-order zero filter 43-■, a 12-stage lattice-type pole filter 42-■, and a 12-stage lattice-type pole filter 42-II
The filters are connected in series in the order of I and second-order zero filter 43-■. Terminal F of DFC-II.

, Bi and the terminals Fi and Bo of the DFC-11 are connected, so that the output terminal FSo and the input terminal BSi of the previous stage (mostly of the DFC-II) polar filter 42-... are connected to the terminals (of the DFC-II).
It is connected to the input terminal FS i and the output terminal BSo of the polar filter 42-■ of 1pDFc-Ill.

As mentioned above, in the DFC-II type, the signal of the terminal Bi is added to the terminal BSi by the function of the selector 88 (Fig. 13), and the output signal of the terminal FSo delayed by 32 time slots by the delay circuit 72 is sent to the terminal BSi. This is because it is controlled so that it does not occur. As a result, the polar filter 4
2-■ and 42-■ effectively constitute a 24-stage lattice-type polar filter.

It is known that in a lattice filter, as the number of stages increases, a frequency characteristic with more peaks (poles) can be realized. Similarly, in a zero filter, as the order (number of stages) increases, more valleys (zero points) can be controlled. Therefore, according to the combination shown in FIG. 25, the 24-stage lattice type pole filters 42-■, 42-III and the total 4th-order zero filters 46-■, 43-III provide even more power than the case shown in FIG. It is possible to set and control complex frequency characteristics.

When the filter configuration is as shown in FIG. 26(a), DFC-II, DFC'-1, and DFC are used as shown in FIG.
The digital filter section 14 is configured using three -III type digital filter circuit devices DFC. This is the DFC-n type and DF type explained in Figure 25 (b).
DFC-1 type is inserted between C-11 [type]. As mentioned above, 5. The DFC-■ type uses only the polar filter 42, and uses Fi as the musical tone signal input terminal and F as the output terminal. use. Therefore, as shown in the same figure (b), DFC-I
The output terminal Fo of the t type is connected to the input terminal F1 of the DFC-1 type, and the output terminal B of the DFC-1 is connected. DFC-I
Connect to input terminal B1 of DFC-1 and terminal F of DFC-1. .

Bi, connect to terminal FI + BO of 1DFC-■.

In addition, output terminals 01 to 03 for each sub-series of DFC-1
Connect to input terminals ■1 to ■3 of DFC-1, and
Connect the output terminals 01 to 03 of 1 to the input terminals of DFC-
Connect to I3. Then, as shown in Figure (a), 2
Next zero filter 43-■, 12-stage lattice-type pole filter 42-■, 12-stage lattice-type pole filter 42-1
．． The filters are connected in series in the following order: a 12-stage lattice pole filter 42-2, a second-order zero filter 46-2, and so on.

Terminal F of DFC-1. , Bi and terminal F1. of DFC-1.
By connecting Bo, and the terminal F of DFc-1
. , Bi and the terminal FI +Bo of DFC-Ill are connected, so that the terminal FS of the front and rear polar filters 42-H
o, BSi and the terminal FSi of the middle pole filter 42-■,
BSo is connected to the terminals FSo, FS i of the pole filter 42-■ in the middle stage and the terminals FSi, BS of the pole filter 42-■ in the subsequent stage.

will be connected. The reason for this will be clear from the explanation of each type DFC-1, DFC-11, and (2) above. As a result, three 12-stage lattice-type polar filters 42-n,
42-1.42-I[1 effectively constitutes a 36-stage lattice pole filter. Therefore, the second
According to the combination shown in FIG. 6, it is possible to set and control more complex frequency characteristics than in the case shown in FIG. 25.

In FIG. 26, the number of digital filter circuit devices DFC0 of the DFC-■ type provided in the middle stage is not limited to one, but may be more. In this case, the number of stages of the lattice pole filter increases further, making it possible to set and control more complex frequency characteristics.

In FIG. 25(b) and FIG. 26(b), between each chip of the digital filter circuit device DFC, output terminals 0. -03 and input terminals 1-3 are connected in sequence. This connection allows an unfiltered serial tone signal to be conducted from the first device DFC-It to the last device DFC-Ill.

As shown in FIG. 25(b) and FIG. 26(b), a plurality of digital filter circuit devices DFC (DFC-1, n) are connected.

When using (2), it is effective to use different filter coefficients for each, so that the frequency control characteristics of each are different. To this end, measures may be taken such as making the stored contents of the filter coefficient ROMs 97 (FIG. 13) provided inside each different, and making the filter coefficients KO supplied from the outside different. Also,
A plurality of digital filter circuit devices DFC (DFC-1, If, II
External filter coefficient KO in one or more of I)
, and use internal filter coefficients for the rest.

Note that the selection circuit or gate (selector 8f, 8f in FIG. 13) inside the digital filter circuit device DFC
8. ．． 89 etc.), it is possible to realize a different connection combination of the pole filter 42 and the zero filter 43 from that described above. Accordingly, it is also possible to realize a combination of a plurality of digital filter circuit devices DFC other than those described above. For example, device DF
It is also possible to realize a connection in which the zero filter 43 is used alone in C, and a multi-stage zero filter is configured by cascading a plurality of such digital filter circuit devices DFC that use only the zero filter. It is possible to do so.

As explained above, according to the present invention, by switching the connection combinations of a plurality of digital filters having different configurations, it is possible to selectively realize a filter configuration that is larger than the number of digital filters. In addition, by combining multiple unitized digital filter circuit devices with a common hardware configuration and selectively switching the connection combinations of the multiple digital filters for each circuit device, a variety of filter configurations can be selected as a whole. Furthermore, manufacturing costs can be reduced by standardizing the hardware configuration of the filter circuit device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the overall configuration of an example of an electronic musical instrument implementing a digital filter device according to the present invention, and FIG. 2 is a musical tone signal generation section, musical tone signal distribution, accumulation and serial conversion control in FIG. A block diagram showing an example of the circuit; FIG. 3 is a block diagram showing an example of the digital filter section in FIG. 1; FIGS. 4(a), (b),
(C) is a diagram showing an example of the use of the multi-sequence sound source (sub-sequence) shown in Fig. 2, and Fig. 5 (a), Φ), and (C) can be realized by a combination of a pole filter and a zero filter. Figure 6 is a block diagram showing the basic configuration of an infinite impulse response filter that can be used as a pole filter, and Figure 7 is a diagram showing the basic configuration of an infinite impulse response filter that can be used as a zero filter. Figure 8 (a) is a block diagram showing the basic configuration of a lattice type filter that can be used as a polar filter. Figures 8 (b) and (C) are similar to the lattice type filter. 9 is a block diagram showing an example of the pole filter shown in FIG. 3 configured by a 12-stage lattice filter; FIG. 10 is a block diagram showing an example of the zero filter shown in FIG. Figure 11 is a timing chart showing an example of the serialization format of musical tone signals, Figure 12 is a timing chart showing an example of the serialization format of filter coefficients, and Figure 13 is used as the digital filter section in Figures 1 and 3. FIG. 14 is a block diagram showing a detailed example of a possible digital filter circuit device, and shows an example of the serial musical tone signal, filter coefficients, and timing signals input to the pole filter of FIG. A timing chart showing channel timing states of main signals, FIG. 15 is a block diagram showing an example of the timbre selection device in FIG. 1, and FIG. 16 shows an example of the serialization format of the timbre parameters output from FIG. 15. 17 is a block diagram showing an example of the filter coefficient external storage device in FIG. 1, FIG. 18 is a diagram showing an example of address signal generation in the address signal generation circuit of FIG. 17, and FIG. A circuit diagram showing a detailed example of the first-stage filter unit of the lattice-type polar filter in FIG. 9, and FIG.
9 is a circuit diagram showing an example of the internal configuration of the shift register for storing filter coefficients, FIG. 21 is a timing chart for explaining the serial multiplication operation of the multiplier in FIG. A circuit diagram showing a detailed example of the filter, FIG. 23 is a timing chart illustrating the states of various signals in the first calculation stage in FIG. 22, and FIG. A block diagram showing an example of a connection combination of a filter and a zero filter. FIG. 13(b) is a block diagram showing that the filter configuration of FIG. 13(a) is realized using only one digital filter circuit device shown in FIG. 25(a) is a block diagram showing another connection combination example of the pole filter and zero filter in the digital filter section of FIG. 1, and FIG. FIG. 26(a) is a block diagram showing another connection combination example of the pole filter and zero filter in the digital filter section of FIG. 1. , the same figure (b) shows the same figure (a) using three digital filter circuit devices shown in FIG.
) is a block diagram showing the implementation of the filter configuration. 11... musical tone signal generation section, 12... timbre selection device,
13... Musical tone signal distribution and accumulation and serial conversion control circuit, 14... Digital filter section, 20...
Filter coefficient external storage device, 21... Filter coefficient changeover switch, 37... Filter input control circuit, 38.
...Digital filter main circuit, 39...Output control circuit, 40...Timing signal generation circuit, 41...Filter coefficient supply circuit, 42...Pole filter, 43...
・Zero filter, L1 to L12...Lattice type filter unit, DFC, DFC-1, DFC-11, D
FC-11, DFC-IV...Unitized (]
chip) digital filter circuit device, 87.88.
89...Selector for checking and switching digital filter connections, FSi...Forward input, FSo...Forward output, BSi...Reverse input, BS. ...Reverse output. Patent applicant: Nippon Musical Instruments Manufacturing Co., Ltd. Figure 8 (b)

Claims (1)

[Claims] 1. A device comprising a plurality of digital filters having different configurations and a connection switching means for selectively switching connection combinations of these digital filters according to a selection signal, inputting a digital musical tone signal, and A digital filter device for an electronic musical instrument, wherein the musical tone signal is controlled according to the combination of the digital filters switched by a connection switching means. 2. The connection switching means is provided on the input side of each digital filter, and selectively connects one of the output signal of one of the digital filters and the inputted digital musical tone signal to the input of the corresponding digital filter. 2. The digital filter device for an electronic musical instrument according to claim 1, further comprising a plurality of selectors for providing a filter. & At least one of the digital filters is of a type having a forward input, a forward output, a reverse direction input, and a reverse direction output, and the digital filter of this type is compatible with face direction input and reverse direction input. 3. A digital filter device for an electronic musical instrument according to claim 2, further comprising said selectors. 4. The electronic musical instrument according to claim 1, wherein each of the digital filters includes a pole filter capable of controlling a pole in the amplitude frequency characteristic and a zero filter capable of controlling a zero point in the amplitude frequency characteristic. Digital filter device. 5. The digital filter includes one of the pole filters and one of the zero filters, and the connection switching means includes at least a fourth combination for inputting the output of the pole filter to the zero filter, and the output of the zero filter. A digital filter for an electronic musical instrument according to claim 4, wherein the digital filter can be selectively switched to either a second combination in which the polar filter is inputted to the polar filter, or a third combination in which the polar filter is used alone. Device. 6. The polar filter is a lattice-type filter collar, and this digital filter device has a first input terminal for inputting the digital musical tone signal and a first input terminal corresponding to the facial input of the lattice-type polar filter. 2 input terminals and a third input terminal corresponding to reverse input, and the first combination uses the signal of the first input terminal as a forward input signal to the lattice pole filter. and the case of using the signal of the second input terminal, and the connection switching means connects the forward output to the reverse input of the lattice pole filter depending on the selected combination. 6. The digital filter device for an electronic musical instrument according to claim 5, wherein the digital filter device is capable of switching whether the third input terminal is connected or not. 7. A plurality of unitized filter circuit devices including a plurality of digital filters having different configurations and a connection switching means for selectively switching connection combinations of these digital filters according to a selection signal are interconnected. The electronic musical instrument is characterized in that connection combinations of the digital filters are selected for each of the filter circuit devices by the connection switching means inside the filter circuit devices, and the overall filter configuration is determined by a set of these combinations. digital filter device. 8. The plurality of digital filters include a filter that can control the pole in the amplitude frequency characteristic and a zero filter that can control the zero point in the amplitude frequency characteristic, and the filter circuit device has a zero filter in the first stage and a zero filter in the second stage. A first filter circuit device in which a polar filter is selected as a connection combination, and a connection combination in which the first filter circuit device is connected in cascade with the first stage as a pole filter and the rear stage as a zero filter is selected. 8. The digital filter device for an electronic musical instrument according to claim 7, further comprising a second filter circuit device. 9. The third connection combination in which the pole filter alone is selected
9. The digital filter device for an electronic musical instrument according to claim 8, wherein one or more filter circuit devices are inserted between the first filter circuit device and the second filter circuit device. 10. The digital filter device for an electronic musical instrument according to claim 8 or 9, wherein the polar filter is a lattice filter having a forward input, a forward output, a reverse input, and a reverse output. .