JP2697701B2 - Electronic musical instrument parameter supply device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic musical instrument and others.
Device with digital tone generation function or digital audio processor
Parameters of electronic musical instruments that can be used in
The present invention relates to a meter supply device. 2. Description of the Related Art A digital filter is used for a tone circuit of an electronic musical instrument.
For example, Japanese Patent Application Laid-Open No. 59-44096 discloses
In the report. One set of filter parameters
Supplied to the digital filter, and the filter
Characteristics (amplitude-frequency characteristics) are set. Tone determinant
Note that multiple sets of filter parameters are
According to the content of the selected tone determinant.
Then, a set of filter parameters is read. [0003] In the prior art
Can be used for multiple timbre determinants (eg, key touch, range,
Timbre selection information, information over time, brilliant
Different sounds depending on the operation amount of the manual operation
When performing color control, one to one
Store multiple sets of filter parameters in memory corresponding to 1
I had to remember. For example, 44 sounds
Area, 16 key touch groups, 32 kinds of stationary sounds
One-to-one pairing for all combinations of colors (22528 patterns)
If the filter parameters are stored individually,
22528 sets of parameters can be stored in the meter memory.
Large capacity is required. The present invention has been made in view of the above points.
Determinants (timbre determinants)
One set of parameters according to the combination of
Or, when supplying for control,
Electronic musical instruments that can save the capacity of parameter memory
Is intended to provide a parameter supply device. [0004] An electronic musical instrument according to the present invention.
Device parameter supply device stores multiple sets of parameters
Parameter storage means, timbre information, and first parameter
Determinant information and second parameter determinant information
Input means for inputting each of them, and the first parameter for each tone color.
The values of the determinant are divided into groups, and the group
The first group address data relating to the
1 group address storage means, and the second parameter
Group each value of the determinant,
The second group storing the second group address data
Loop address storage means, tone color, and first parameter determination
Corresponding to the combination of the factor and the second parameter determinant.
Parameters to be read from the parameter storage means
A parameter indicating an address in the parameter storage means.
Parameter address data.
In each of the stored parameter address data.
Is the timbre, a group of first parameter determinants and
Different combinations of groups of second and second parameter determinants
The same address in the parameter storage means
Parameter indicating that there is an instruction for
Memory means, the tone color information and the first parameter
In response to the input of the determinant information,
The combination of the timbre and the first parameter determinant
Corresponding first group address data to the first
Read from the group address storage means of the
In response to the input of the second parameter determinant information,
The second group address data corresponding to the input is
2 from the group address storage means.
Corresponding to the combination of the first and second group addresses
The specific parameter address data
Read from the address storage means,
From the parameter storage means according to the data address data.
Reading means for reading a set of parameters.
The supplied parameters are supplied for setting or controlling the tone.
That's what I did. [0005] Basically, the parameters stored in the parameter storage means are stored.
Parameters are timbre and two parameter determinants
(A first and second parameter determinant)
Read by combining. Where the combination of the three
Parameters can be read directly from the parameter storage
Parameter address storage means
Parameter according to the parameter address read from
The parameters are read indirectly from the storage means. Ma
Input timbre information, first parameter determinant information
Parameter and the second parameter determinant information
Parameter address directly from data address storage means
Instead of being read out, the input timbre information and the first
Is the first group address.
Determined second parameter input to storage means
The factor information is input to the second group address storage means.
And the first and second addresses read from each group address storage means.
Specified according to the combination of and the second group address
The parameter address data of the parameter address
It is configured to read from the storage means. Like this
Corresponding to the read specific parameter address data
The corresponding parameter is read from the parameter storage means.
You. Thus, the first and second group address storage
Means including parameter means and parameter address storage means.
Parameter storage means by adopting an addressing configuration
Characterized in that it is configured to read parameters from
doing. Here, the first group address storage means
Group the values of the first parameter determinant for each timbre.
The first group related to the group for each tone
Because the address data is stored, it is optimal for the tone
Grouping is possible, and the optimal parameters
Meter generation can be performed with a simple configuration.
The effect is excellent. Also, group
This reduces the overall data volume and simplifies the configuration.
Can be abbreviated. Furthermore, parameter address storage
The means comprises a timbre, a first parameter determinant and a second parameter determinant.
Parameter corresponding to the combination of parameter determinants of
The parameter to be read from the data storage means
Parameter address indicating the address in the storage means
Data is stored, but the stored
Each of the parameter address data includes the tone color,
The first parameter determinant group and the second parameter
Data for different combinations of groups of data determinants.
Pointing to the same address in parameter storage means
Therefore, even if the combinations are various,
Without increasing the amount of storage parameters
It is possible to supply appropriate parameters according to various combinations.
It has an excellent effect. Therefore, parameter storage
The column stores a plurality of sets of parameters.
The parameter address read from the meter address storage means
Read parameters based on dress data
Because of the indirect addressing method, the timbre and the first and second
One-to-one correspondence with all combinations of parameter determinants
No need to memorize parameters
In the means, the number of parameter sets smaller than the number of combinations is
It is only necessary to memorize. In other words, the tone and
And the combination of the first and second parameter determinants is different
However, some parameter sets may use common ones
It may be possible to store it in the parameter storage
The number of parameter sets to be
The amount can be saved. For example, the above range, key
22528 combinations of pitch and tone types
Only 2620 sets of parameters
In the examples described later, it is possible to deal with
Is shown. In such a case, the timbre and the first and
Parameter according to a certain combination of the two parameter determinants.
Parameter address read from the
Parameters read according to the data and another combination
The address data may be the same as the parameter
From storage means the same for each of these different combinations
Read parameters. Note that the first and second parameters
As data indicating the data determinant, for example, a pressed key
Key code, touch data indicating key touch, time
Use the information according to the excess, the output information of the appropriate manual operator, etc.
Can be. BRIEF DESCRIPTION OF THE DRAWINGS FIG.
The embodiments of the present invention will be described in detail. <Description of Overall Configuration of One Embodiment> In FIG.
Equipped with multiple keys to specify the pitch of the musical tone to be generated
doing. The key touch detector 11 is pressed by the keyboard 10
To detect a touch applied to the key
Detects touch or after touch
It may be something. The tone selection device 12 is a
It is made up of a group of operators for selecting the tone of the sound. Pick
The tibend operator 13 determines the pitch of a musical tone to be generated.
This is for continuously modulating according to the operation amount.
For example, it is composed of a dial-type operator. Microcomputer
Data 14 is a CPU (central processing unit) 15,
ROM (read-only memory) that stores
Memory 16), RA for working and data storage
M (random access memory) 17
And each circuit in the electronic musical instrument via the address bus 28
Between the keyboard and the keyboard, and detects key presses on the keyboard 10.
Processing and sound assignment of pressed keys for multiple sound channels
Guessing processing, detection of a timbre selection operation in the timbre selection device 12.
Output processing, detection of the operation amount of the pitch vent operator 13
Processing and other various processing are executed. The tone generator 18 has a plurality of tone generators.
Generating digital tone signals independently on each channel
Indicates the key assigned to each channel
Key code KC and key-on signal indicating on / off of the key
No. KON and other necessary data from microcomputer 1
4 via the bus 28 and, based on this,
A digital tone signal is generated on the channel. Tone Gene
The pitch synchronizing signal generation circuit 19 is included in the
The pitch of the tone signal generated on each channel.
A synchronized pitch synchronization signal is generated for each channel. In the specification of this embodiment, the tone
The neerator 18 is provided for the first to sixteenth channels (Ch1 to C
h16) Digitally in a time-division manner with a total of 16 channels
Generates a tone signal. Hours and minutes from tone generator 18
Digital tone waveform sample value data output
The data is indicated by TDX. Emitted from master clock generator 20
The generated master clock pulse φ
The basic operation time of the data 18 is controlled. Day
Time division multiplexing of digital tone waveform sample value data TDX
Is 64 cycles of the master clock pulse φ.
And the time of each cycle in this 64 cycles of one cycle
The slots are numbered 1 to 64 as shown in FIG.
It is. The figure shows a multiplexed digital tone waveform
Channel timings 1 to 16 of sample value data TDX
Are also shown. For example, the first channel data
TDX is divided into four time slots 33 to 36.
Has been applied. In the specification of this embodiment, the
The sample value data TDX has data for 16 channels
As described above, they are multiplexed and output in common.
The channel pitch synchronizing signals PS1 and PS2 are divided into two systems.
The data is time-division multiplexed every eight channels and output. on the other hand
Are the first to eighth (Ch1 to Ch).
8) Time-division multiplexed pitch synchronization signal
The channel timing is as shown in FIG. The other
The switch synchronization signal PS2 is ninth to sixteenth (Ch9 to Ch1).
6) Time-division multiplexed pitch synchronization signal
The channel timing is as shown in FIG. Apparent from the figure
Like the pitch synchronizing signals PS1, P
S2 occurs in a time slot width and its time division multiplex
One cycle of the conversion is 8 time slots. Two-line adaptive digital filter
Apparatus (hereinafter sometimes abbreviated as ADF) 21, 22
Is configured to be suitable for filtering the tone signal
A digital filter device according to this embodiment
Now the filtering of the music signal for 8 channels
One ADF 21 is the first to eighth channels
Of the other ADF 21
Is the filtering of the tone signals of the 9th to 16th channels
I do. A predetermined model is provided inside the ADFs 21 and 22.
Digital filter circuit, filter parameter memo
And various circuits to control the supply of filter parameters
Filter synchronized with the pitch of the tone signal to be filtered
Control circuit for performing arithmetic operation, filtered musical tone signal
Pitch synchronization output circuit that outputs the signal in synchronization with the pitch
Circuit for various functions such as
The structure is suitable for filtering. The data output from the tone generator 18
Digital tone waveform sample value data TDX is ADF21
And 22. In addition, the first to eighth channels
The pitch synchronization signal PS1 is input to the ADF 21, and the ninth to
The pitch synchronization signal PS2 of the 16th channel is ADF22
Is input to In the ADFs 21 and 22, the pitch synchronization signal
The signals PS1 and PS2 are generated (signal "1")
The data TDX of the channel corresponding to the
To the sample data of that channel.
Perform a filter operation on Therefore, one ADF
At 21, the first to eighth channels according to the pitch synchronization signal PS1
The filter operation of the channel tone signal is performed, and the other AD
In F22, the ninth to first signals are performed according to the pitch synchronization signal PS2.
The filter operation of the musical tone signal of 6 channels is performed. Like this
The unit time of the filter operation in the ADFs 21 and 22
(The signal delay time synchronized with the sampling period)
It is synchronized with the pitch of the tone signal to be filtered.
The unit time of the filter operation may fluctuate depending on the pitch.
Realizes filtering of moving formant characteristics
Is done. Note that the basic operation timing of the circuit is controlled.
Master clock pulse φ and system sync
Luth SYNC is provided to ADFs 21 and 22. Cis
The system sync pulse SYNC has 64 pulses as shown in FIG.
It is a pulse generated in the time slot cycle and is a digital
This is synchronized with one cycle of time division multiplexing of a tone signal.
The ADFs 21 and 22 control the filter operation.
Data for the microcontroller via the bus 28
Provided under the control of the computer 14. In the ADFs 21 and 22, the actual
Of the tone signal to be filtered
Not only in sync with the
The sound waveform sample value data is sampled in synchronization with the pitch.
Re-ring and output with complete pitch synchronization
It has become. Turn this filtered data into pitch
Pitch synchronization signal P for synchronous resampling
S1 and PS2 are used. ADF21 and 22 output
Digital tone waveform sample value data for each channel
Are summed by the accumulator 23, and 16 channels
Musical sound waveform sample value data summing sample value data
Ask for. The output data of the accumulator 23 is digitized.
/ Analog converter 24 converts to analog tone signal
Then, the sound is pronounced via the sound system 25. In the specification of this embodiment, the filter coefficient
Is controlled in two modes. One is "Statistics
Mode, which is a
This mode does not change the data coefficient. The other is "Dyna
`` Mic mode '', which is
This mode changes the filter coefficient over time.
A temporal change in timbre due to the ring is obtained. Statistic
Filter coefficients for the ADFs 21 and 22
Stored in the filter parameter memory inside the
You. The filter coefficients for the dynamic mode are
Stored in the dynamic control parameter memory 26.
This is time under control of the microcomputer 14.
The ADF 21 is read out after being switched
And 22. Dynamic / Static selection
The selector switch 27 selects either mode for supplying the filter coefficient.
This is a switch for selecting whether or not to control with a command. What
As an example of the clock frequency, the master clock
The clock pulse φ is about 3.2 MHz, and a pitch synchronization signal
One cycle of time division of PS1 and PS2 (8 time slots)
G) is 400 kHz and the digital
Time-division 1 cycle of tone waveform sample value data TDX
(1 operation cycle in filter) (64 time slots
) Is 50 kHz. Next, a detailed example of each circuit in FIG. 1 will be described.
Will be explained. <Generation of pitch synchronization signal> FIG.
2 shows an example of the signal generation circuit 19, which is one of the systems.
(1st to 8th channel) pitch synchronization signal PS1
Live. The other pitch synchronization signal PS2 is also the same as in FIG.
Generated by the configuration. The pitch synchronization signal PS1 is
The P number read from the P number memory 29 is counted by the counter 3
Based on time-division counting for each channel at 0
Is generated. P number is a certain reference octave
Of the tone waveform having the frequency corresponding to each note name C-B
This is a number indicating the number of sample points in one cycle. Pitch synchronization signal
Signal PS1 is generated by 8 channels time division as shown in FIG.
If you want to, its basic sampling frequency
(In other words, the resolution of the pitch synchronization signal PS1) is the master
1/8 of the frequency of the clock pulse φ (for example, 400 kHz
z), which is common to all note names. On the other hand,
Since the basic sampling frequency is common,
The P number has a different value for each note name frequency.
Show. The frequency of a certain note name in the reference octave is fn
And the above-mentioned common sampling frequency (400 kHz
If z) is fc, the P number corresponding to the pitch name is
It is determined as follows. P number = fc ÷ fn (1) where the common sampling frequency fc is fc = 400 kHz.
z, the frequency fn of the pitch name A is fn = 440 Hz (that is, A4
Sound), the P number of note name A is
Therefore, the P number of the pitch name A = 400000 ÷ 440 = 909. On the other hand, it can be generated in the tone generator 18.
Sampling of different sample point amplitude values per cycle of musical tone waveform
If the number of points is 64, the effective sample of the frequency fn
The ring frequency fe is represented by fe = fn × 64 (2). In the case of fn = 440 Hz, fe = 440 × 64 = 28160 Hz. Similarly, each sound in a certain reference octave
The P number of the name and the effective sampling frequency fe are shown in the table below.
Can be determined as follows. In this case,
The pitch is one octave from the G4 note to the F # 5 note. [Table 1] In the counter 30 shown in FIG.
Signal PS1 is established based on master clock pulse φ.
The common sampling frequency fc is divided according to the P number.
It is obtained by going around. As is clear from the above,
P number is the common sampling frequency fc in one cycle waveform
Is the number of periods, or number of sample points.
Effective per musical sound waveform period that can be generated by the nerator 18
The number of sample points is 64 as described above. Therefore, common
Assuming that the frequency dividing frequency of the sampling frequency fc is frequency dividing number = P number 64 (3), the frequency divided output is 64 pieces per musical tone cycle.
Pulse, which allows 64 effective
All sample points can be established. in this way
Sampling frequency fc depending on the division number determined by
Is divided from the above equations (1), (2) and (3), fc ÷ division number = (fn × P number) ÷ (P number ナ ン 64) = fn × 64 = fe (4) The sample point address is changed by this divided output.
To establish the effective sampling frequency fe
can do. The effective sun established in this way
The pulling frequency fe is in harmony with the pitch frequency fn,
Pitch synchronization is realized. Generated from counter 30
The pitch synchronization signal PS1 of each channel is
(4) corresponding to the note name of the key assigned to
Divided output signal, that is, effective sampling frequency
This is a signal having fe. The frequency division number determined by the above equation (3) is an integer.
And often contains decimals. For example, sound
In the case of the name A, the division number = 909９０64 = about 14.20. Therefore, the frequency division operation of the counter 30 is performed later.
As described above, two integers close to the frequency division number determined by equation (3)
Frequency division as appropriate, and the average result is the amount determined by equation (3).
To get the same result as dividing by the frequency
You. In FIG. 3, the P number memory 29 is
P of each note name in the reference octave as shown in Table 1
The number is stored in advance. Assigned to each channel
Key code KC of the key
To the tone generator 18, and
Key codes KC for the first to eighth channels in the figure
Time as shown in PS2 channel timing
Time-division multiplexed by
-Code KC corresponds to the channel timing of PS2 in FIG.
Time division multiplexing is performed at the timing shown. In this way
Time division multiplexed key codes of first to eighth channels
KC is input to the P number memory 29. P number memo
Re 29 is the input key code of the first to eighth channels
The P number is read out in a time-division manner corresponding to the note name of the KC. The counter 30 is read from the P number memory 29.
An adder 31 for inputting the read P number;
A selector 32 which inputs the output of the arithmetic unit 31 to the "0" input
And an 8-stage system to which the output of the selector 32 is input.
Shift register 33 and the lower order of the output of the shift register 33.
Gating a bit (decimal part) to another input of the adder 31
A gate 34 for giving a signal and the upper part of the output of the shift register 33
Enter the bit (integer part) and set all 7 bits to “1”
And an adder 35 for adding an all "1" signal
Contains. The P number itself is a 12-bit binary code.
The output of the adder 31 is a carry signal.
From a 13-bit signal that contains one extra bit
Become. Inversion key-on pulse / KONP (/ is the inversion bar
From the output CO of the adder 35
The output signal is input to the AND circuit 36.
Of the AND circuit 36 is the selection control input of the selector 32
Join. When the output signal of the AND circuit 36 is "0"
Provided from the adder 31 to the “0” input of the selector 32
When a signal is selected and "1", it is applied to the "1" input.
Is selected. The “1” input of the selector 32 includes:
The lower bits (decimal part) of the output of the shift register 33 and the addition
13 bits consisting of 7 bits (integer part) of the output of the arithmetic unit 35
Signal is given. The key-on pulse KONP is
This signal is "1" only once at the start of pressing,
Those corresponding to 8 channels are time-division multiplexed
You. The reverse key-on pulse / KONP is
This is a signal obtained by inverting the signal KONP. Selector 32, shift register 33, addition
The part of the vessel 35 is shown in the above equation (3) according to the P number.
Establish a frequency division number that is common to the integer part of this frequency division number.
This is a circuit for dividing the sampling frequency fc.
You. The adder 31 controls the integer according to the decimal part of the frequency division number.
It is for adjusting the value of several parts. Equation (3)
Since the divisor 64 is “2 to the sixth power”, the divisor is calculated.
Without any special division, just under the P number
Just by treating the 6 bits as decimal places,
A corresponding frequency division number can be established. Therefore, the adder
31, output signal of selector 32 and shift register 33
The lower 6 bits of the 13 bits are the weight of the decimal part,
The upper 7 bits are the weight of the integer part. In adder 35
Adding all “1” signals means subtracting 1
equal. Therefore, in the adder 35, the shift register
1 is subtracted from the integer value of the output of the star 33. This
The result of the subtraction by the adder 35 is 6
It is returned to the "1" input of the selector 32 together with the bit data.
Input to the adder 35 again via the shift register 33.
Is forced. The shift register 33 outputs the master clock pulse
Since the shift is controlled by φ, the signal of the same channel
The cycle in which the signal is output from the shift register 33 is the master clock.
8 times the period of the lock pulse φ, that is, the common sampling period
This is the cycle of the wave number fc. At the beginning of key press, the key is assigned
Key-on pulse / KO at the specified channel timing
NP becomes “0” only once, and at this time, the selector 32
The P number of the key is selected via the “0” input of the key. This
The integer part of the P number of the shift register 33 is
5 at the period of the common sampling frequency fc.
1 is repeatedly subtracted from the integer part. The result of subtraction of the integer part is
When the value is 1 or more, the carry-out output C of the adder 35
O continuously outputs carry-out signal "1",
Since the condition of the AND circuit 36 is satisfied, the selector 32
Keep selecting "1" input. By repeated subtraction
When the output of the adder 35 becomes "0"
When the same number of fc cycles as the number of integer parts of the
The carry-out signal of the calculator 35 is not output, and
The condition of the road 36 is not satisfied. At that time, the selector 32
Select the "0" input and enter the P number and shift register 33
Addition by adding lower 6 bits (decimal part data) of output
The output of the container 31 is selected. Thus, the addition of decimals
Thus, the P number having a slightly changed value is
From the integer value of the changed P number.
The subtraction is repeated. Note that the gate 34 is
-Only at the beginning of key press due to ON pulse / KONP
Enabled, otherwise always add fractional data
Give to 31. Small for P number in adder 31
Dividing number actually used for frequency division by adding several part data
Is 1 more than the integer value of the dividing number obtained from the P number.
May be larger. For example, P number of note name A is 9
09, and its division number is 14.20,
The frequency division is performed in accordance with the integer value 14, and the next is 14.20.
+ 0.20 = 14.40 and eventually 15.00
The frequency division is performed in accordance with the integer value 15. like this
And the same as the integer value of the division number obtained by the P number
Or common sampling according to a number one greater than
The frequency fc is divided, and as an average result the P
A frequency division operation according to the frequency division number obtained by the frequency division is achieved.
The signal of the carry-out output CO of the adder 35 is divided.
This is equivalent to the output, and this is
The inverted signal is output as pitch synchronization signal PS1. For better understanding, taking note name A as an example,
An example of a change in the output of the selector 32 is shown. Change timing
Is the period of the common sampling frequency fc. Initially
The frequency division number corresponding to P number 909 is 14.20.
Is 13.20, which is 1 less than the integer value of 12.20, 11.2
0, 10.20, ... 2.20, 1.20 and their integers decrease by one
I do. In the 14th cycle of fc, input “1” of selector 32
The added value is 0.20, at which time the carry-out signal
Becomes “0” and the pitch synchronization signal PS1 becomes “1”.
The selector 32 selects the "0" input. selector
The "0" input of 32 is the frequency division number corresponding to the P number 909
Decimal value 0.20 given from shift register 33 at 14.20
14.40 obtained by adding. Therefore, 14.40 becomes
Output from the selector 32. After that, the selector 32
The force is 13.40, 12.40, 11.40, ... 2.40, 1.40, one by one
The frequency of the selector 32 decreases in the 14th cycle of fc.
The value added to the “1” input is 0.40 and the adder 3
5 carry-out signal becomes "0" and the pitch synchronization signal
A signal PS1 is generated. At this time, the output of the adder 31 is 1
4.20 + 0.40 = 14.60, which is the
It is supplied to the shift register 33 via the “0” input.
Thus, in the case of note name A, 14 or 15 is used as the frequency division number.
The frequency division is performed, and the common sampling frequency fc (for example, 400
kHz) every 14 or 15 cycles
S1 becomes "1". The other 9th to 16th channels
The pitch synchronization signal PS2 corresponding to the
Generated. <Description of Tone Generator>
In the nerator 18, each channel generated as described above is used.
Utilizing the channel pitch synchronization signals PS1 and PS2,
Sampling timing synchronized with the pitch of the musical tone to be generated
The tone signal is generated according to the
Wear. Of course, not limited to this,
Generates tone signals according to sampling timing
It is also possible to Sample point of musical tone to be generated
The address data that specifies the address (instantaneous phase angle)
The pitch synchronization signals PS1 and PS2 of each channel are
This is caused by counting each channel independently.
Can be. However, the pitch synchronization signals PS1 and PS2 are
This corresponds to the pitch of the reference octave (G4-F # 5).
When the above address data is generated
Depends on the octave range of the musical tone to be generated.
Counts when counting the sync signals PS1 and PS2.
It is necessary to switch the port. For example, G3 to F # 4
To generate the tone of the pitch, the pitch synchronization signal PS
1, every time PS2 occurs, 0.5 is counted and G4 ~
To generate an octave tone of F # 5,
Count 1 each time the period signals PS1 and PS2 are generated,
To generate octave musical sounds of G5 to F # 6,
2 each time the switch synchronization signals PS1 and PS2 are generated.
To Thus, the pitch and octave of the tone to be generated
Address data that changes in synchronization with the
Generated every time the digital music
Generates a sound signal. A tone signal in the tone generator 18
Any generation method may be used. For example, on
Music sound wave stored in the waveform memory according to the address data
Method for sequentially reading sample value data (memory read
Method) or the above address data with the phase angle parameter.
Performs a predetermined frequency modulation operation as data
For obtaining sampled sample value data (FM method) or
Uses the above address data as phase angle parameter data
Performs a predetermined amplitude modulation operation to execute the tone waveform sample value data.
Any known method such as a method for finding data (AM method)
Expressions may be used. Also adopts a memory read method
In this case, only one cycle waveform is stored in the waveform memory
, But a multi-period waveform improves sound quality
Is preferred because Store multiple cycle waveforms in waveform memory
A method for reading out the information is disclosed in, for example,
Full wave from the start to the end as shown in 313
A method of storing a shape and reading it once, or
As shown in No. 8-142396, a plurality of attack parts
Store the periodic waveform and one or more periodic waveforms of the sustain part,
The waveform of the sustain part is repeated after reading the waveform of the lock part once.
Readout method or Japanese Patent Application Laid-Open No. 60-147793
Multiple discretely sampled waveforms as shown
Specify the waveform to be stored and read out by sequentially switching over time
And read out the specified waveform repeatedly.
The methods are known, and these may be appropriately adopted. <Preparation of adaptive digital filter
Description> The basic operation type of digital filter is
A finite impulse response (FIR) filter and an infinite
There is an impulse response (IIR) filter.
In the example adaptive digital filter devices 21 and 22
In this case, an FIR filter is employed. First, FIR
Provides a general description related to filters. (A) Basic circuit configuration of FIR filter FIG. 5 is a basic circuit configuration diagram of the FIR filter.
(n) is the digital tone waveform at any nth sample point
Sample value data, the input signal of the FIR filter
It is. Where: Is the unit time delay element, the time of one sampling cycle
This is to set a delay. Therefore, x (n-1) becomes n-1
Digital tone waveform sample value data at the th sample point
X (n-N + 1) is the (n-N + 1) th sample
Digital tone waveform sample value data of a point. N is
The duration of the impulse response,
It corresponds to the order. h (0) to h (N-1) are N-order filters
It is a coefficient. The triangular block with this filter coefficient
The lock is a multiplication element, and each sample delayed by the delay element
For pull point data x (n) to x (n−N + 1), respectively
The corresponding filter coefficients h (0) to h (N-1) are multiplied.
Blocks with + sign to which multiplication output is input need addition
, And sums the respective multiplied outputs to obtain an output signal y (n).
obtain. The impulse response Δh of such an FIR filter
(n)} z-transformation, that is, transfer function
, It is expressed as (B) Linear phase characteristic of FIR filter One characteristic of such an FIR filter is that the phase characteristic is
That is, a linear phase can be obtained. Linear phase
Then, the phase between the input and output waveforms of the filter is completely
And the output waveform is not distorted. Follow
To filter signals such as music, voice, audio, etc.
It is suitable. In a linear phase FIR filter,
It is required that the phase characteristics be θ (ω) = − αω (6) as a function of the angular frequency ω. Where α is called the phase lag
Is a constant. In addition, it has a linear phase characteristic as described above.
The necessary and sufficient conditions of the FIR filter are expressed by the following equation (8).
The impulse response has symmetry, as shown in the following equation (7).
The phase delay α depends on the duration (the order of the filter) N
It is uniquely specified. α = (N−1) / 2 (7) h (n) = h (N−1−n) (8) where 0 ≦ n ≦ N−1 (c) Symmetry of filter coefficient If the impulse response has symmetry as shown in equation (8)
This means that the filter coefficients h (0) to h (N-1)
Meaning to have. That is, the filter coefficients are
The linear phase characteristics described above can be realized by setting
You can do it. Impulse response is a symmetry
FIG. 5 shows an example in which the order N is odd.
FIG. 6 shows a case where N is an even number. Clear from figure
Thus, a symmetric characteristic centered on n = (N-1) / 2 is shown.
You. When N is an odd number, (N-1) / 2 is the center,
The impulse responses on both sides are symmetric. N is an even number
In this case, the center between (N-2) / 2 order and N / 2 is the center.
The impulse response on both sides of is symmetric. In symmetric position
Since the filter coefficients of the orders are the same, all the orders
There is no need to prepare a number N of filter coefficients,
Good. Specifically, when N is an odd number, from the 0th order to (N-1)
/ ({N-1) / 2} +1 filter coefficients up to the 2nd order
From ({(N-1) / 2} +1 order to N-1 order)
Are from 0th order to {(N-1) / 2} -1st order
What is necessary is just to use the filter coefficient in a symmetric position. Sand
That is, the same filter coefficient is used for the 0th order and the N-1th order,
The same filter coefficient is used for the second order and the N-th order. Ma
If N is an even number, the order from 0th order to (N-2) / 2th order
What is necessary is just to prepare N / 2 filter coefficients.
Filter coefficients from the 0th order to the (N-1) th order are (N-2) / 2
Use the filter coefficients at the symmetrical positions up to
No. (D) Frequency response of linear phase FIR filter
Answer As shown in Figs. 5 and 6, the impulse response shows a symmetrical straight line.
Frequency response of phase FIR filter FIG. 7 and FIG. 8 exemplify the characteristics of. N is odd
In the case of ω = π (where π is a sampling
(Corresponding to 1/2 of the frequency fs)
It is not fixed to 0 and can be set arbitrarily. If N is even
As shown in FIG. 8, the level when ω = π is necessarily 0.
As is clear from this, when the order N is odd, the filter is
Realizes high-pass filter characteristics by setting the filter coefficient
However, if N is an even number,
It is impossible to realize the filter characteristics. But N
The even number is easier to design the filter,
Suitable for bandpass filter design. So, the real
The order N of the filter according to the filter characteristic to be expressed
It is preferable to switch between even and odd
In the example adaptive digital filter devices 21 and 22
In such a case, even-odd switching of order N can be performed.
It is a specification that can be cut. That is, bandpass
Filters the characteristics of filters and low-pass filters
In this case, the order N is set to an even number,
When performing filtering, the order N is set to an odd number. (E) Other features of the FIR filter Other features of the FIR filter include feedback.
Because there is no croup, it is characterized by good stability.
That is, like the IIR filter, the feedback loop
If there is a filter, problems such as oscillation will occur.
In this case, problems such as oscillation do not occur, and the design is easy. Also,
Even when the filter characteristics are changed over time, the FI
An R filter is advantageous. In this case, usually
A set of filter coefficients corresponding to each of the different filter characteristics
Must be prepared respectively, but then the filter
To make the time variation of characteristics fine, many sets of filter coefficients
Is required. To solve this problem,
Prepare two sets of filter coefficients that are separated to some extent
By interpolating between a set of filter coefficients,
A set of filter coefficients is generated densely over time,
Thus, the time is determined by the filter coefficient generated by interpolation.
It is possible to set filter characteristics that fluctuate
You. In this way, interpolation of filter coefficients is performed in real time.
FIR filter
For those with good stability, such as
It is very advantageous because it is not necessary to devise
You. The word length of the signal in the digital filter is
Signal data within the limited word length
Must be rounded. Such rounding is noise
However, in the FIR filter, the feedback loop is
There is no accumulation of rounding errors
This is advantageous for noise suppression. Note that F as described above
Regarding various characteristics of the IR filter, for example, see the book “Theory
and Application of Digital Signal Processing "(Author)
: Lawrence, R. Rabiner; Bernard, Gold, Publisher: P
rentice-Hall Inc). Next, the adaptive decoding in this embodiment will be described.
Some of the digital filter devices 21 and 22
The features will be briefly described in advance. (F) How to calculate filter coefficients The filter coefficients are obtained by analyzing actual musical tones.
It is. FIG. 9 shows an example of a procedure for obtaining a filter coefficient.
Referring to the description, first, there are two types of sounds that indicate different timbres.
Sampling sound waveform (original music sound waveform) from natural musical instrument sound
Prepare by doing. For example, Haraku tone waveform 1 is strong
This is the waveform of the piano sound played by touching the key.
Form 2 is the waveform of the piano sound played with a weak key touch.
You. Next, fast Fourier transform is performed, and the original musical sound waveforms 1, 2
Is analyzed, and based on this, the two waveforms 1 and 2 are analyzed.
Find spectral characteristics. Next, the spectrum of waveforms 1 and 2
Find the difference between the characteristics. Next, the spectral characteristics of the difference
Then, a process of obtaining a filter coefficient is performed based on this.
Finally, the obtained filter coefficient is stored in the memory. fill
The filter coefficient that realizes the time variation of the
Clock control parameter memory 26 (FIG. 1).
Filter that realizes steady filter characteristics that do not change
The filter coefficient is a parameter in ADF 22 and 22 (FIG. 1).
Store in memory. The spectral characteristics of the difference between the two waveforms described above
The reason for finding the filter coefficient based on
Data 18 (FIG. 1) with one original musical tone waveform (for example, a strong key
Music signal corresponding to the
Filtering according to the spectral characteristics of the difference
By applying it to the other original music waveform (for example,
(Corresponding waveform)
It is. A place to perform filtering according to key touch
Filter coefficients for all key touch intensity levels
Without preparing a set of
Prepare only a set of filter coefficients, not prepared
The filter coefficient corresponding to the key touch strength is the same complement as described above.
It may be determined depending on the interval. Of course, for key touch
Not only the corresponding filter coefficients, but also the pitch (or
Or the tone type or various other factors.
Filter coefficients are prepared in the same manner as described above. (G) Filter operation synchronized with the pitch. For each sample point in the ADFs 21 and 22 (FIG. 1)
The filter operation timing is the pitch synchronization signals PS1 and P
It is set by S2. This means that the filter operation
The unit time delay (see FIG. 4) is the pitch synchronization signal PS.
1, PS2. Sand
That is, the sampling frequency fs in the filter operation is
It is set by the switch synchronization signals PS1 and PS2. Concrete
Specifically, the pitch synchronization signal PS corresponding to each note name G to F #
1 and PS2 are the effective sample shown in Table 1 above.
ADFs 21 and 22 are the same as the
The sampling frequency fs of the filter operation at
As shown in the table, different
Will be. Sampling frequency in filter operation
The number fs corresponds to the frequency response characteristics shown in FIGS.
Ω = 2π. As is clear from here,
When the sampling frequency fs changes according to the note name,
The frequency corresponding to ω = 2π in the wave number response characteristic also
And the resulting filter characteristic is
It becomes a moving formant characteristic. Such a moving forma
Characteristic is very suitable for controlling the timbre of a tone signal.
You. On the other hand, the sampling
If the wave number is constant regardless of the pitch of the input signal,
The filter characteristics obtained are fixed formants. (H) Switching Between Pitch Synchronous / Asynchronous As described above, the filter of the moving formant is used for the tone color of the musical tone.
Suitable for control, but depending on the tone or effect
Sometimes a fixed formant filter is more desirable
is there. Also, operating the pitch vent operator 13 (FIG. 1)
Fixed pitch when sliding the pitch of the generated sound
Olmant filters are preferred. For this,
In the ADFs 21 and 22 of the embodiments, the filter operation is performed
Switch between synchronous and asynchronous
Specifications. In addition, such pitch synchronization / non-
Synchronization switching is not the same for all channels.
It is possible to specify pitch synchronous or asynchronous independently for each file.
I can do it. By the way, during pitch vent operation
Why fixed formant filters are preferred
Is as follows. The pitch vent operator 13
Pitch control is not only a slight pitch shift control, but also several pitches.
Large pitch slide control over
The octave boundaries of note names G to F # shown in Table 1 above
The pitch control may be performed across the. And that
When performing a filter operation synchronized with the pitch,
The coupling frequency fs fluctuates rapidly, and
The toe-off frequency also fluctuates rapidly (moving formant
This causes unnatural tone changes. For example, pitch
Musical notes being produced by venting are changed from F # 5 to G5
, The sampling frequency is 47.3.
The frequency fluctuates rapidly from 59 kHz to 25.088 kHz (see Table 1 above).
See) For moving formants, only the difference
The cut frequency also fluctuates rapidly. Prevent such inconvenience
When moving the pitch form, move the formant (pitch
Fixed formman without using
(Filter operation asynchronous to pitch).
In the case of pitch asynchronous filter operation, ADFs 21 and 2
Fig. 3 shows the sampling frequency of the filter operation in Fig. 2.
In the example, the frequency is 50 kHz. (I) According to dynamic / static
As described above, in the dynamic mode,
In real time, die under the control of microcomputer 14
From the parameter control memory 26 (FIG. 1)
Read the parameter data for natural control, and
The data must be transferred inside the DFs 21 and 22. That
Therefore, the data transfer time is limited,
If the number is large, filter coefficients of all orders within a limited time
There is a possibility that parameter data cannot be transferred. Follow
Therefore, the filter order in the dynamic mode is
Must be of a limited order commensurate with the data transfer time of the
Must. On the other hand, in static mode
It is not necessary to change the filter coefficient
No problem. Also, the higher the filter order, the finer the filter.
This is preferable because the filter characteristics can be realized. Follow
In static mode, the filter order is sufficient
I try to do a lot. For the above reasons, this
In the specification of the embodiment, the dynamic mode or the static
The filter order is switched according to the mode.
You. For example, filter order in static mode
To the 32nd order (however, this is the case of the even order characteristic,
31th order in the case of the next characteristic)
The filter order of the 16th order (the odd order characteristic
In this case, the order is 15). (J) Weight control of filter coefficient The binary digital data format of one filter coefficient is 1
2-bit filter coefficient data part and 3-bit weight
And a data section. 3-bit weight data section
Is 6 of 0, +1, +2, +3, +4, and +5 bits.
This indicates one of the possible shift amounts.
The filter coefficient data part is shifted according to the shift amount,
The weight is given. 12-bit filter coefficient data
Weighting control that can shift the
The dynamic range of the filter coefficients
It is qualitatively expanded to 17 bits. Such weighting system
While maintaining a sufficient dynamic range,
The number of bits of filter coefficients stored in memory is small
To save filter filter memory capacity
One. <Overall Adaptive Digital Filter>
Description> FIG. 10 shows the adapter corresponding to the first to eighth channels.
Internal structure of active digital filter device (ADF) 21
FIG. 4 is a block diagram schematically illustrating an example of ADF2;
2 can be configured in exactly the same way. Input interface
Pace 38 from the tone generator 18 (FIG. 1).
The synchronization signal PS1 is received and the pitch of each channel is
Period signal PS1 conforms to the operation timing inside ADF21
FIG. 11 shows a detailed example.
Is shown in The timing signal generation circuit 39
Generates timing signals to control various operations inside F21
And input from the input interface 38.
Based on the signal corresponding to the pitch synchronization signal of each channel
Various operation timing signals required for filter operation
The detailed example is shown in FIG.
I have. As described later, the filter operation for each channel is
This timing signal generation circuit
Filter performance of each channel at appropriate timing from 39
Timing signals for arithmetic operation control.
ing. The state memories 40 and 42 and the multiplier and
The accumulator sections 41 and 43 are provided for the FIR filter.
This is a digital filter circuit that executes a filter operation. S
Tate memory 40 and multiplier / accumulator unit 41
Digital filter circuit (this is an A-series digital
Tal filter circuit) is the first to fourth channels
(Ch1 to Ch4) filter operation
Memory 42 and the multiplier and accumulator 43.
Digital filter circuit (this is a B-sequence digital
Filter circuits are referred to as fifth to eighth channels (Ch).
5 to Ch8). Each series
Each of the digital filter circuits A and B has four channels.
Filter calculations are performed in a time-sharing manner.
You. The filter operation of the first to eighth channels is performed by two series A,
The reason for dividing into B is that the reason for circuit design is
According to State memories 40 and 42 are tone generators
Digital tone signal sampler given from FIG. 18 (FIG. 1)
The value data TDX in synchronization with the pitch synchronization signal PS1.
The pitch corresponding to the number of stages corresponding to the predetermined filter order.
It is delayed at the timing corresponding to the synchronization signal PS1.
Yes, unit delay in FIR filter basic circuit of FIG.
Element [Equation 4] Corresponding to the set of Multiplier and accumulator unit 41,
Numeral 43 denotes a digital signal delayed by the state memories 40 and 42.
To the delay order for
Multiply the filter coefficients of the corresponding order, and multiply the
The results are cumulatively summed, and are based on the FIR filter shown in FIG.
This corresponds to the multiplication element and the addition element in this circuit. A system
Column state memory 40, multiplier and accumulator unit
A detailed example of 41 is shown in FIG.
Can be similarly configured. The microcomputer interface 44 is a microcomputer interface.
Data and address under the control of the computer 14 (FIG. 1).
Various data provided through the bus 28 are received, and A
This is supplied to each circuit in the DF 21. This interface
The types of data accepted via the face 44 are as follows:
It is on the street. Key code KC: Indicates the key assigned to each channel
You. Key-on pulse KONP: assigned to each channel
The signal becomes "1" only once at the start of the key depression. Touch code TCH: key assigned to each channel
5 shows the strength of the touch when the button is pressed. Tone code VN: A key assigned to each channel
Indicates the tone type (voice) selected. The above KC, KONP, TCH, and VN are predetermined time division timers.
Each channel is time division multiplexed according to the timing
Output from the interface 44 in the
Tapping unit (sometimes called PPU) 4
5 given. Pitch synchronous / asynchronous designation signal PASY:
The digital filter operation in the ADF 21 is
This signal specifies whether to perform synchronization or asynchronous.
You. This signal PASY is also given in time division for each channel.
The pitch of the filter operation
Period / asynchronous control can be performed independently for each channel.
Wear. This signal PASY has a selected tone type.
Or the operation contents of the pitch vent operator 13 (FIG. 1).
Or depending on the operating state of the dedicated or appropriate controls, etc.
And provided to the interface 44 via the bus 28.
You. Pitch synchronization / non-output from interface 44
The synchronization designation signal PASY is given to the input interface 38.
Signal generation corresponding to the pitch synchronization signal PS1.
To control whether force interface 38 should or should not
Used for Dynamic filter parameter DPR: Micro
A parameter for dynamic control under the control of the computer 14
The filter read out from the meter memory 26 (FIG. 1)
Parameter (filter coefficient). As mentioned earlier,
The content of the dynamic mode filter parameter DPR is
It changes with the passage of time during pronunciation. This dynamic
The data format of the mode filter parameter DPR is also described above.
Similarly, the 12-bit filter coefficient data section and 3-bit
And the weighted data part of
Contains identifying data. Also, as mentioned above, this dyna
A set of orders for the filter parameter DPR for the mic mode
Is the 16th (or 15th) order. Furthermore, it is clear from the above
Thus, the symmetry of the filter coefficient in the linear phase characteristic
The actual set of dynamic mode files
The filter parameter DPR need only be for the eighth order. Dynamic / static selection signal D
S: Dynamic / static selection switch 27
This signal is generated in response to the operation shown in FIG.
Data calculation in the dynamic mode described above or static
To perform in the lock mode. The above DPR and DS are in
From the interface 44 to the parameter selector 46.
You. The parameter memory 47 has a static mode
Filter parameters (filter coefficients)
It is. The parameter processing unit 45
From the parameter memory 47 for static mode.
Reads filter parameters. That is,
-When the on-pulse KONP is given, the tone color code V
N, Touch Code TCH, Key Code KC
Calculate the address of the parameter memory 47 to be read
And the filter parameters stored at this address
From the memory 47. The read static
Mode filter parameter SPR
Provided to the rectifier 46. This static mode filter
The data format of the filter parameter SPR is the same as the DPR described above.
It is like. Also, as described above, the static mode
A set of filter parameters SPR is of order 32 (or 3
Primary). Furthermore, as is clear from the above, the linear position
Due to the symmetry of the filter coefficients in the phase characteristics,
A set of static mode filter parameters
The SPR need only be for the 16th order. The parameter selector 46 has a dynamic
/ Dynamic according to the contents of the static selection signal DS
Filter mode or static mode filter parameters.
Data DPR or SPR. Selected para
The meter is a parameter supply circuit 48 for the A and B series,
49 is input. In the A-series parameter supply circuit 48
Are the filter parameters DPR of the first to fourth channels or
Accepts the SPR, stores it, and
The state memory 40, the multiplier and the
It is supplied to the accumulator section 41. Parameter B
In the supply circuit 49, the filter parameters of the fifth to eighth channels are set.
Do the same for the data. For static mode
Filter parameter SPR only once at the beginning of key press
It is read from the parameter memory 47, and
The data is stored in the data supply circuits 48 and 49. Therefore, the status
Filter mode during the sounding period in the
And maintain a constant filter characteristic. On the other hand, Dyna
The filter parameter DPR for the mic mode is new
The content parameters are transmitted via the microcomputer interface 44.
Stored in the parameter supply circuits 48 and 49 until given.
The contents of the parameter DPR are stored in time.
Is rewritten each time it changes. Output from the parameter supply circuits 48 and 49
Of the filter parameters
Odd identification data EOA1 to EOA4, EOB1 to EOB4
Are supplied to the state memories 40 and 42, and the filter coefficients
Data part COEA, COEB and weighting data part WE
IA and WEIB are multipliers and accumulator units 41,
43. It should be noted that the last A
Or, B represents the distinction between the A series and the B series. Data EOA
1 to EOA4, EOB1 to EOB4 are
Are given in parallel, but the data COEA, COE
B, WEIA, and WEIB are time-shared for each channel
Is given. Parameter processing unit 4
5, parameter selector 46, parameter memory 47,
A detailed example of the parameter supply circuits 48 and 49 is shown in FIG.
Have been. The pitch synchronization output circuit 50 includes a multiplier and an
Each channel output from the accumulator units 41 and 43
Input the filtered tone signal sample value data of
These are sampled at the timing synchronized with each pitch.
Circuit. Used here for sampling control
Are provided from the input interface 38. Pi
Switch synchronization signal PS1D, which is the pitch of each channel.
The latch synchronization signal PS1 is delayed for a predetermined time. Pi
Delayed pitch for resampling synchronized to
The reason for using the sync signal PS1D is that the digital
Of the tone signal of each channel in the filter operation
This is to match the delay. In this way, the digital filter
Resamples the output signal in synchronization with the pitch.
Process is to adjust the sampling frequency to the musical pitch.
Therefore, the problem of aliasing noise is solved. Sync to pitch
Digital filter operation
Filter output signal is sampling period synchronized with pitch
The pitch synchronization output circuit 50 is not particularly provided.
Can also achieve pitch synchronization, but the pitch
When digital filter operation is performed asynchronously to the pitch
Pitch synchronization output circuit 50 is required to achieve synchronization
It is. A detailed example of the pitch synchronization output circuit 50 is shown in FIG.
Have been. Next, an adaptive digital filter device
A detailed example of each unit of 21 will be described. Note that each figure
And the number and letter D such as "1D" and "8D"
Circuits marked with are delay circuits or shift registers
Where the preceding number indicates the number of delay stages or stages.
You. In addition, this delay circuit or shift register block
The delay control clock pulse or shift control clock
Those that are not shown that the pulse is input,
Delayed by the master clock pulse φ (see FIG. 2) or
Shift control is performed. <Input Interface 38: FIG. 11> FIG.
1, the pitch synchronization signal PS1 is
2 is input to the shift register 53. Shown in FIG.
As shown, this pitch synchronization signal PS1 has eight time slots.
Is a cycle, eight channels are time-division multiplexed.
The pitch of the key assigned to a channel
One time slot corresponding to the channel
A signal "1" is generated at this point. The output of the shift register 53 is
Returned to the input side via AND circuit 54 and OR circuit 52
The pitch synchronization signal PS1 for eight channels is
The data is cyclically held in the shift register 53. Each Chan
Eight latch circuits 55 corresponding to channels are provided in parallel.
The pitch output from the shift register 53.
The period signal is input in parallel to its data input D. Each la
The latch control input L of the latch circuit 55
Corresponding latch timing signals φFS1 (25), φFS2
(29),..., ΦFS8 (56) are input and left. φF
The number following S indicates the channel number,
The number in parentheses is one operation cycle (64 data shown in FIG. 2).
Time slot) and the time slot number.
Time slot corresponding to the time slot number.
The latch timing signal becomes signal “1”. For example,
The signal φFS1 (25) is a signal “1” in the time slot 25.
Which corresponds to the first channel. Figure 2
As can be seen, the time slot 25 is pitch
Time division time of the first channel in the synchronization signal PS1
Is supported. Therefore, this signal φFS1 (2
5) In the part of the latch circuit 55 that is latched by
Is the content (pitch) of the pitch synchronization signal PS1 of channel 1.
Signal “1” at the timing synchronized with
The signal "0") is latched in the ming. Other channels
The same applies to channels 2 to 8, and the pitch synchronization signal of each channel.
Are connected to the latch circuit 55 in parallel at a predetermined timing.
Is touched. The latch tie corresponding to each channel
The timing signals φFS1 (25) to φFS8 (56) are shown in FIG.
It is generated from two decoders 56. The decoder 56
Counter 57 to decode the output
Generate a reset signal. The counter 57 is a master clock pulse.
Is a modulo 64 counter that counts
Periodically by stem sync pulse SYNC (Fig. 2)
Is reset to Racks corresponding to channels 1 to 8
Timing signals φFS1 (25) to φFS8 (56)
In which time slot is generated from the display of FIG.
It will be obvious. Returning to FIG. 11, each timing signal φF
S1 (25) to φFS8 (56) are multiplexed by the NOR circuit 58.
And inverted. The output of the NOR circuit 58 is the AND circuit 5
4 is input. As a result, the latch circuit 55
Shift register 53 for the channel on which
Is cleared. On the other hand, the pitch synchronization signal PS1 becomes "1".
Latched by the latch circuit 55 corresponding to the
In the next cycle, the signal "1"
Timing signals φFS1 (25) to φFS8 (56) are generated
It is held until you do. Thus, the latch circuit 55 includes
For the channel for which the pitch synchronization signal PS1 is "1",
In response, the signal “1” is held for 64 time slots.
Be held. The output of the latch circuit 55 corresponding to each channel
The force is represented by filter operation request signals φF1 to φF8 in FIG.
To the timing signal generation circuit 39 of FIG. See below
Thus, the filter operation request signals φF1 to φF8
When it becomes “1”, filter operation for one sample point is executed.
Is performed. Only when the pitch synchronization signal PS1 is generated
The filter operation request signals φF1 to φF8 become “1”.
In the end, it synchronizes with the pitch of the tone signal to be filtered
The calculated digital filter operation is performed. An example
For example, as shown in FIG.
Assuming that the pitch synchronization signal PS1 has become "1" (this
In this case, this signal "1" is a pitch synchronization signal of channel 1.
This is cyclically held by the shift register 53, and
The timing signal φFS1 (25) is
When it occurs, it is latched by the latch circuit 55 and the channel
The filter operation request signal φF1 corresponding to 1
It rises to "1" in slot 25. This signal φF1
Is 64 ties until time slot 24 of the next cycle
The signal “1” is maintained for the time width of the time slot. <Timing signal generating circuit 39: FIG. 12>
In FIG. 12, the timing signal generation circuit 39
In addition to the decoder 56 and the counter 57 of FIG.
The filter of each channel provided from the interface 38
Filter operation according to filter operation request signals φF1 to φF8
Operation timing for generating timing signals for operation control
The generation circuits 391 to 398 are connected to each channel (Ch1 to Ch).
8) For each. In the figure, the circuit 391 of channel 1
Only the details are shown, but the circuits 39 of the other channels 2 to 8
2 to 398 have the same configuration, and the
Are different only in the time relationship of the switching signals T (33), T (49),.
You. The timing signals T (33), T (49),.
Generated from 56. As before, the timing signal is
The number in parentheses in the code indicates one operation cycle
Time slot in (64 time slots shown in FIG. 2)
Indicates the number and the time corresponding to the time slot number
The timing signal becomes "1" in the slot
Is shown. Other timing signals generated by decoder 56
The same applies to numbers, and refer to the numbers in parentheses.
The timing signal is assigned to which time slot.
It is easy to determine whether the error occurs (whether it becomes "1"). example
For example, the timing signal T (33) is tied as shown in FIG.
Signal "1" in the system slot 33,
Signal T (3-18) is between time slots 3 and 18
And the signal becomes "1". The generation timing signal of channel 1
The path 391 will be described.
F1 and the timing signal T (33) are supplied to the AND circuit 59.
Can be Therefore, it is necessary to perform the filter operation.
If it is requested,
The output of the AND circuit 59 becomes “1”. This AND circuit 5
9 and the output signal of the delay circuit 60 for one time
The signal delayed by the lot is supplied to OR circuit 61. This
The output of the OR circuit 61 is a filter data sampling clock.
The lock signal RLA1 is supplied to the digital filter circuit.
It is used to control the unit delay in This signal R
LA1 has time slots 33 and 34 as shown in FIG.
It becomes "1" when. The output of the AND circuit 59 is provided to the AND circuit 62.
And even / odd identification data EOA1 of channel 1 (this is shown in FIG.
0 output from the parameter supply circuit 48.
) Is inverted by the inverter 63. This
Data EOA1 is next to the filter characteristic to be realized.
The signal is “1” when the number is even order, and is signal when the number is odd order.
“0”. The output of the AND circuit 62 is a delay circuit 64
, And the inhibit signal INH
Output as A1. Unset when filter order is odd
The output signal of the circuit 62 is "1" in the time slot 33.
And the time slot 35 after two time slots
At this time, the signal INHA1 becomes "1" (see FIG. 16). H
If the filter order is even, the signal INHA1 is always "0".
It is. This in-bit signal INHA1 is a digital
In the arithmetic operation of the filter circuit, the highest order of even order (3
By prohibiting the (second order) operation, the odd-order filter
Is used to achieve sexuality. The timing signals T (3-18) and T (35)
−50) is input to the OR circuit 65, and its output and
The output of the AND circuit 59 is input to the OR circuit 66.
You. The output of the OR circuit 66 is delayed for one time by the delay circuit 67.
The first shift clock signal φFFA1
(See FIG. 16). The output of the OR circuit 66
Signal obtained by inverting the output of the
Signal is added to the AND circuit 69, and its output is delayed.
The signal delayed by one time slot on the path 70 is
It is output as lock signal φFLA1 (see FIG. 16).
See). The signal φFLA1 is a signal if the filter order is even.
It is "1" at the time of the im slot 36, but if it is an odd number,
It is "0". These shift clock signals φFFA
1 and φFLA1 are each a digital filter circuit.
In order to perform the operation for each order in a time-sharing manner,
Tone signal corresponding to each delay stage in the memory 40 (FIG. 10)
Used to sequentially shift sample value data.
The time slot is set according to the timing signal T (35-50).
Multiplication timing signal which becomes "1" between 35 and 50
PDOA1 (see FIG. 16) is a digital filter circuit
Between the tone signal sample value data and the filter coefficient
This indicates the period in which the multiplication should be performed. For the other channels 2 to 4 in the A series,
The corresponding operation timing signal generation circuits 392 to 394
Timing signals T (49) and T (19-
34), T (51-2), ... is the timing of channel 1.
Signal T (33), T (3-18), T (35-50)
16 time slots in order from the timing of
It is. Therefore, the output from the circuit 391 of channel 1
Signal RLA similar to each of the signals RLA1 to PDOA1
2 to PDOA2, ..., RLA4 to PDOA4 are other channels
16 ties from each of the circuits 392 to 394 in the channels 2 to 4
This is generated at the timing shifted by each slot. to this
Based on the A-series digital filter circuit (particularly the multiplier
And one accumulator section 41) in one operation cycle
= Time every 16 time slots between 64 time slots
In the interval, filter operation of four channels 1-4
It can be performed in a time-sharing manner. Performances corresponding to channels 5 to 8 of the B series
Also in the arithmetic timing signal generation circuits 395 to 398,
Predetermined timer offset by 16 time slots between channels
Timing signals T (49) and T (19-3)
4), T (51-2),... Are used.
Seed signals RLB1 to PDOB1,... RLB4 to PDOB4
Is generated. Generation of operation timing signal corresponding to A series
Each signal RLA1-P generated by the raw circuits 391-394
DOA 4 is applied to A-series state memory 40 and B
Each signal generated by the circuits 395 to 398 corresponding to the series
RLB1 to PDOB4 are B-series state memories 42
(FIG. 10). <State memory 40: FIG. 13>
The A-series state memory 40 stores each of the A-series channels.
State memories 401 to 404 corresponding to channels 1 to 4
Are provided in parallel. Channel 1 state memory
Although only the details of 401 are shown, the other channels 2 to 4
Tate memories 402 to 404 have the same configuration.
The input signals are different. Each of the above channels 1
-3 to 3 corresponding to operation timing signal generation circuits 391 to 3
Signals RLA1-PDO generated from signal 94 (FIG. 12)
A1, ... RLA4 ~ PDOA4 are in their own channel
Input to the corresponding state memories 401 to 404, respectively.
You. The state memory 40 shown in FIG.
Before describing the details of the accumulator section 41,
Of basic operation of digital filter circuit composed of
This will be described with reference to the schematic diagrams shown in FIGS. <Even-Order Filter Operation Basic Operation: FIG. 17
FIG. 17 shows an even number in the above digital filter circuit.
F when realizing a filter characteristic consisting of
FIG. 4 is a schematic diagram for explaining a basic operation of an IR type filter operation.
Yes, (a) is a block diagram, (b) is each operation timing
Of the shift registers SR1 and SR2 in FIG.
Music signal signals in the stages Q0 to Q15 and Q16 to Q31
Indicates the state of the pull value. The first shift register SR1 is 1
Digital music with 6 stages to be filtered
The sound signal sample value data xn is transmitted through the selector SEL1.
Is entered. New sump via selector SEL1
As a signal for taking in the value data xn,
Filter data sampling clock signal RLA (chan
In the case of channel 1, RLA1) is used, and the shift register
As the shift clock pulse of SR1, the first shift described above is used.
Clock signal φFFA (φFF for channel 1
A1) is used. Each of the first shift registers SR1
Stages Q0 to Q15 are from sample point n to n-15
16 sample value data xn to xn-15
You. The output of the last stage of this shift register SR1 is
The sampling clock signal R is output via the selector SEL1.
When there is no LA, the process returns to the first stage. This shift
The register SR1 is shifted only to the right. The second shift register SR2 also has 16 stages.
And the output of the first shift register SR1 is selected.
The data is input via the data SEL2. Via selector SEL2
To take the output of SR1 into SR2
The aforementioned filter data sampling clock signal RLA
Is used as the shift clock pulse of the SR2.
The above-described second shift clock signal φFLA (channel 1
In this case, φFLA1) is used. This second shift
Each stage Q16 to Q31 of the register SR2
16 samples from points n to n-16 to n-31
The value data xn-16 to xn-31 are held. Shift Regis
The final stage Q31 of the data SR2 is connected via the selector SEL2.
The first switch when there is no sampling clock signal RLA.
Connected to the stage Q16. This shift register SR2
Is a bidirectional shift type, and a sampling clock signal R
When LA is “1”, the right shift mode is set. When LA is “0”, the left shift mode is set.
Shift mode is activated. The shift registers SR1 and SR2
The outputs of the stages Q15 and Q16 are added by the adder ADD.
The result of the addition is given to the multiplier MUL,
The coefficient COEA is multiplied. The result of the multiplication is
Data ACC, and the multiplication result for all orders
Accumulated in. Thus, accumulator A
The filter operation result for one sample point is output from CC.
It is. Samples for two sample points by adder ADD
Add the value data, and apply the common filter coefficient COEA
Is multiplied by the multiplier MUL.
According to the symmetry of numbers. That is, two symmetrical
Sample value data is multiplied by the same value of filter coefficient.
Therefore, do not multiply them separately, add them once
Multiplies both sampled data simultaneously by coefficient multiplication
To do it. In (b) of FIG.
The axis operation timing is one time according to the master clock.
Progress for each slot. The numbers shown there are for convenience only
One operation cycle (64 time slots)
It does not absolutely indicate the time slot number inside.
In the example of the figure, at the operation timing 1, the shift register
Xn to xn for each of the stages Q0 to Q31 of SR1 and SR2
Contains sample value data of 32 sample points up to -31
I have. In the example shown in FIG.
Assuming that the pulling clock signal RLA becomes "1"
I have. Thereby, shift clock signals φFFA, φF
The shift registers SR1 and SR2 are set to one state according to LA.
At the operation timing 2 as shown in the figure.
It becomes a state. Shift clock signal φFF at this time
A, φFLA is φFFA of FIG. 16 for channel 1
1, as shown in the column of φFLA1,
What happens. As is clear from FIG.
The time slot is the shift clock signal φFFA, φFL
A does not occur, and therefore, the operation timing 3 shown in FIG.
Then, the state of each stage Q0 to Q31 does not change. Only
16 time slots from 3 to 18
In the case of channel 1, the multiplication timing signal PD
Time slots 35 to 50 in which OA1 (FIG. 16) occurs
Multiplication and accumulation are performed during this time.
Will be That is, at the calculation timing 3, the stage Q1
Sample data of xn-14 and xn-15 in Q5 and Q16
The data is added by the adder ADD, and the
The result is multiplied by the accumulator ACC
Is held. Between operation timings 4 and 18, 1
For each time slot, the first shift register SR1
Shift, the second shift register SR2 is shifted left,
The state of each stage Q0 to Q31 changes sequentially as shown
I do. Therefore, at operation timing 4, xn-13 and xn-16 are
Which is then multiplied by a fifteenth filter coefficient,
The result is accumulated in the accumulator ACC. Next performance
At calculation timing 5, the same calculation is performed for xn-12 and xn-17.
Is performed, and thus the two-sample value data at the symmetric position
The same filter coefficient calculation is performed sequentially in time division
At operation timing 18, xn + at the last symmetric position
A similar operation is performed for 1 and xn-30, which gives
Is completed. At the next operation timing 19
Is shifted again, and each stage is
Each sample value data in order of time delayed by Q0 to Q31
xn + 1 to xn-30 are arranged. <Basic Operation of Odd-Order Filter Operation: FIG.
> FIG. 18 shows the filter characteristics of odd-order (31st) order.
Explains basic operation of FIR filter operation when realizing
(A) is a block diagram, (b) is a schematic diagram for
(A) shift register SR at each operation timing
1. Each stage Q0 to Q15, Q16 to Q30 of SR2
3 shows the state of the musical tone signal sample value of FIG. As shown in FIG.
Each block is the same as that shown in FIG.
The difference is that the output of stage Q16
Through the adder ADD. Gate G
T is an inhibit signal INHA (for the first channel, IHA
NHA1) is controlled by the inverted signal.
When the signal INHA is "1", the stage Q1
6 is prohibited from being applied to the adder ADD
You. Also, the sixteenth state of the second shift register SR2
The 15th stage Q30 and the 1st stage are not used.
Page Q16 is connected via the selector SEL2. Figure
At 18 (b), the state of the first shift register SR1
The change is the same as in FIG. Second shift register
The state change of SR2 is slightly different from that in FIG.
Become. Shift clock signal of second shift register SR2
The signal φFLA is in even order mode at the operation timing 4.
Is "1", but becomes "0" in the odd-order mode.
In the case of channel 1, the time in the column of φFLA1 in FIG.
See lot 36). Therefore, in the odd-order mode, FIG.
As shown in (b), the second shift register SR2
The contents are not shifted at the operation timing 4 and the operation time
Are sequentially shifted to the left from ring 5 to ring 19. At the operation timing 3, the shift register S
Each of the stages Q0 to Q30 of R1 and SR2 has the 31st order
Tone signal sample values xn + 1 to xn-29 corresponding to the delay stage
Are placed in the order, and the center order
Contains the sample value xn-14. As shown in FIG.
In the odd-order mode, the center order of symmetry is
A unique filter coefficient is assigned correspondingly.
Therefore, at the operation timing 3, the inhibit signal IN
The output of stage Q16 is inhibited by HA and the central order
Adder ADD outputs only the output signal of stage Q15 corresponding to
In addition, in the multiplier MUL, a fixed value corresponding to the central order is obtained.
Multiplies the available filter coefficients. At operation timing 4,
Only the first shift register SR1 is shifted right and the second
Is not shifted. Therefore,
Xn-13 goes into the cottage Q15 and xn-15 goes into the Q16
ing. Further, the inhibit signal INHA is set to “0”.
And the gate GT is opened. Thus, both central orders
Sample values xn-13 and xn-15 corresponding to the next order are added.
ADD, and are added to each other.
Are multiplied by a common filter coefficient. Calculation timing
From 5 to 18, SR1 is sequentially shifted to the right and SR2 is sequentially shifted to the left.
The sample value at the symmetric position as shown
Enter the cottages Q15 and Q16, add both, and
The filter coefficients are multiplied. <Digital Filter Circuit: FIG. 13> FIG.
State memory 4 corresponding to channel 1 with reference to 3
01 will be described. 16 stage one-way shift lever
The register 71 is the first shift register S shown in FIGS.
R1 and corresponding to channel 1
Shift control by 1 shift clock signal φFFA1
Is done. Supplied from the tone generator 18 (FIG. 1).
The digital tone signal sample value data TDX is latched.
The latch timing signal XLDA1 input to the circuit 73
The sample value data of channel 1 is
It is taken into the road 73. Tone signal sample value data TDX
-Division timing of each channel in (see FIG. 2)
Latch tie corresponding to each channel 1-8
Signals XLDA1 to XLDA4, XLDB1 to XL
DB4 is generated from decoder 56 (FIG. 12). Above
The number in parentheses at the end of each signal display in Figure 12
Indicates a time slot number in which the signal is generated. Each
A latch circuit 7 is provided in the state memory corresponding to the channel.
3 are provided, and the corresponding latch circuits are provided.
Latch timing signals XLDA1 to XLDA4, XL
Musical sounds of each channel 1 to 8 by DB1 to XLDB4
The signal sample value data TDX is separately latched,
And demultiplexed. Channel latched by latch circuit 73
The tone signal sample value data of 1 is input to the A input of the selector 74.
Given to The selector 74 is an operation timing shown in FIG.
Filter data circuit provided from the
A input when the sampling clock signal RLA1 is "1"
Is selected, otherwise the shift register added to the B input is selected.
The output signal of the sixteenth stage of the star 71 is selected. Above
As described above, this signal RLA1 is synchronized with the pitch of the musical tone.
Therefore, a new sample is selected by the selector 74 in synchronization with the pitch.
Select pull value data (A input) and shift it
To the data 71. As is apparent from FIG.
In the time slot 34 where A1 becomes “1”, the shift clock
Since the clock signal φFFA1 becomes “1”, the shift register
Data 71 is the new sample value provided by selector 74
The data is taken into the first stage (Q0). Next Times
In the lot 35, the shift operation is temporarily stopped, and the time
As described above, the right shift is sequentially performed in lots 36 to 51.
is there. The bidirectional shift register 72 is shown in FIGS.
8 corresponding to the second shift register SR2.
You. Each stage Q16 of the bidirectional shift register 72
To Q31 are connected to the selectors SL1 to SL16 as shown.
Switch circuits LC1 to LC16, and a bidirectional shift
Connected as possible. That is, the first
The first shift is applied to the A input of the selector SL1 of the stage Q16.
The output signal of the final stage (Q15) of the register 71 is
Input, and the selector S of each of the other stages Q17 to Q31
Latch of previous stage is connected to A input of L2-SL16
Outputs of the circuits LC1 to LC15 are input. In addition, each step
The next stage is applied to the B inputs of the selectors SL1 to SL16 of the next page.
Output of the latch circuits LC2 to LC16 and LC1
Is forced. Thereby, each of the selectors SL1 to SL16
When the A input is selected, the mode shifts to the right and the B input
When is selected, the mode is the left shift mode. Each selector S
Sampling clock as a selection signal for L1 to SL16
The signal RLA1 is used, and when this signal is "1", the A input selection
Selection, that is, right shift mode. However, odd mode
Stage to disable stage Q31
The selector SL15 of Q30 is somewhat different from the others.
That is, the selector SL15 is provided with the C input.
The output signal of the stage Q16 is added thereto. Cha
Even / odd identification data EOA1 for channel 1 is “1” (one).
(Even mode), the AND circuit 751 is enabled.
When the signal RLA1 is "0", the AND circuit 751
The output becomes a signal “1”, which causes the selector SL15
Selects the B input and the output of stage Q31
30 (shifted left). EOA1
When it is “0” (in the odd-order mode), the AND circuit 761
Is enabled, and when the signal RLA1 is "0", the selector S
L15 selects the C input, and the output of stage Q16 is
Page Q30 (shift left over Q31
Is). With the above configuration, the first and second shift registers
The change states of the contents of the stars 71 and 72 are the even mode and the odd mode.
17 (b) and 18 (b) according to the next mode.
Just like the ones. First stage of second shift register 72
The output signal of Q16 is applied to gate 76 via gate 75.
available. The gate 75 outputs the inhibit signal INHA1.
It is controlled by the inverted signal.
This corresponds to GT. Gate 76 is connected to the first
Output signal of the shift register 71 (output signal of the stage Q15).
) And the second shift register provided through the gate 75
The output signal of the stage 72 (the output signal of the stage Q16) is input.
To the multiplication timing signal PDOA1 (see FIG. 16).
Therefore, it is released. The output of gate 76 is a multiplier and an accumulator.
To the adder 77 of the accumulation section 41, where two
Are added. This adder
77 corresponds to the adder ADD in FIGS. 17 and 18.
is there. The output of the adder 77 is delayed for one time by the delay circuit 78.
, And is input to the multiplier 79. The multiplier 79 is
The tone signal sample value data supplied through the delay circuit 78
Filter coefficient data provided to the data through the delay circuit 80.
Data COEA. Output of multiplier 79
Is delayed by 4 time slots by the delay circuit 81 and the shifter 8
2 given. The shift control input of the shifter 82 has five
Via the delay circuit 83 for setting the delay of the time slot.
Finding data WEIA is provided. This multiplier 79 and
Shifter 82 corresponds to multiplier MUL in FIGS.
Things. That is, as described above, the filter coefficient data
COEA is the effective bit data of the filter coefficient.
In the multiplier 79, the effective bits of the filter coefficient
Is multiplied by the tone signal sample value data. Soshi
Then, the result of this multiplication is
By shifting by the number of bits corresponding to the value of WEIA,
The real number of filter coefficients and the tone signal sample value data
Is completed. The output of the shifter 82 is supplied to an accumulator 84.
Given, multiplication result corresponding to each order for one channel
Is accumulated. The output of accumulator 84 is
The operation end timing signal F
Latched according to ENDA. This signal FENDA
It is generated from the decoder 56 of FIG. Displayed in the figure.
As shown, this signal FENDA
It becomes "1" at 8, 24, 40 and 56. Times
In lot 56, the calculation result of channel 1 is latched, and
Latches the operation result of channel 2 and channel 24
The calculation result of channel 3 is latched, and channel 4
Is latched. From the decoder 56, the
The operation end timing signal FENDB is generated in the same manner.
You. The number of multipliers and accumulate units 41 is four.
Is shared in a time-sharing manner by the channels of That is,
The arithmetic unit 77 stores the channel 1 state memory 401
In addition to the output of gate 76, the status of channels 2-4
Similar devices provided in the remote memory 402 to 404
The output signal of the gate having the function is multiplexed. Each
The output gate 76 of each of the Tate memories 401 to 404 has 1
6 timeslot width multiplication timing signals PDOA1 to PDOA1
Different ties for PDOA4 shifted by 16 time slots
Input each time. Therefore, each channel is added to the adder 77.
The signals of channels 1 to 4 are time-divided every 16 time slots
Multiple inputs. Filter coefficient data COEA and
The weighting data WEIA has four channels.
Time division every 16 time slots at the same timing as above
Multiplexed, 16 ties per channel
In the data slot, the first to 16th data
Divided and multiplexed. B state memory 42
Multiplier and accumulator unit 43 has the same configuration as in FIG.
However, the timing of various signals may be different
You. A sequence and B sequence as shown in FIG.
Digital filter circuit (that is, state memory 4)
0, 42 and multipliers and accumulator units 41, 43)
Of filter operation for each channel 1 to 8 in
FIG. 19 shows the timing. In FIG. 19, shift 1
Column contains the first shift register (7 for channel 1).
1) shows the shift timing, and the shift 2 column shows the second
Shift register (72 for channel 1)
3 shows the timing of the operation. The direction of the arrow is the shift direction
(Right shift or left shift). Each channel
The shift timing of the operation timing signal generation circuit 39
1 to 3 (FIG. 12).
Clock signals φFFA1 to φFFB4, φFLA1
... FLB4. shift
The operation includes shift operation for filter operation and stored data.
And a dummy shift operation for data refresh. An example
For example, in the case of channel 1, time slots 4 to 19
The shift is a dummy shift. In the column for shift 2
The symbol (←) shifts left in the even-order mode,
Indicates that no shift is performed in the numerical mode. In FIG. 19, the column of INH indicates an inhibit.
The generation timing of the signals INHA1 to INHB4.
ing. In the odd mode, the time slot marked with a circle
Inhibit signals INHA1 to INHB4
It becomes “1”. The column of PDO shows the state of each channel.
Multiplier and accumulator unit 4 from memories 40 and 42
Tie input of tone signal sample value data to 1, 43
Ming. This is the multiplication timing for each channel
With respect to the generation timing of the signaling signals PDOA1 to PDOB4.
I am responding. The SUM column is the output of the accumulator 84
The timing is shown. PDO and SUM timing
There is a delay of 6 timeslots between
Accumulation with 5 timeslot delay by 8,81
Due to the delay of one time slot due to the event 84. Accumulate
At the last time slot of the output timing of the
Indicates that the operation end timing signal FENDA is
The output of the mullator 84 is taken into the latch circuit 85. <Parameter Memory 47: FIG. 20> FIG.
Shows an example of the storage format of the parameter memory 47.
Key group table, touch group table
Table, parameter address table and parameter bank
Consists of The actual filter parameters are
Parameter address table stored in the
Contains the parameters to be read from the parameter bank.
Address data is stored. Key group table
Stores information that groups the keys for each key.
doing. As an example, the number of keys is 88, the number of groups is 44
In the key group table, the address corresponding to each key
Relative to the key group to which the key belongs
Address data (called a key group address)
I have. Therefore, the key group table stores the key code KC
Is addressed by This key group table
A predetermined absolute address (offset) of the parameter memory 47
Address OADS).
I'm worried. The touch group table stores key data for each tone color.
Group the touch intensity corresponding to each stage of touch intensity.
The information to be converted is stored. As an example, the number of tones is 32
There is a touch group table for the tone code VN.
Includes 32 timbre-specific areas corresponding to values 0 to 31
Touch that can be expressed by the touch code TCH
The intensity stage is 64 as an example, and each tone color area is
There are 64 address positions corresponding to touch 0 to 63
doing. The address position corresponding to each touch intensity is
Relative ad for touch group to which touch intensity belongs
Address data (called a touch group address) is stored.
Have been. As an example, the number of touch groups is 16.
Therefore, the touch group table stores the tone code VN and the
Address by the switch code TCH. This touch
The group table has a predetermined absolute value in the parameter memory 47.
Address (this is called offset address OAD1)
Occupies the storage area starting with. This touch glue
The absolute address data for reading the table is 6
5-bit tone code at the top of the bit touch code TCH
11 bits of relative address data by combining code VN
(The address that sets the offset address OAD1 to 0)
Create and add this to the offset address OAD1
Created by The parameter address table stores each key
Supports each touch group for each loop and for each tone
Relative to the address that stores the filter parameter to be
Stores address data (called parameter address)
ing. This parameter address table is
44 key group areas corresponding to loops 0 to 43
This key group area contains the key group described above.
To the key group address read from the loop table
Therefore, it is addressed. Each key group area has tone 0
Each of the 32 timbre-specific areas corresponding to
This tone-specific area is addressed by the tone code VN.
Is performed. Each tone area is assigned to touch group 0-15
It has 16 corresponding address locations, each address
Location read from the touch group table above
Addressed by touch group address. What
Note that a 2-byte storage location is assigned to one address location.
Where the parameter address data is 12
Stored in bits. This parameter address table
Is a predetermined absolute address (this
This is called offset address OAD2).
Occupies the storage area. This parameter address table
The absolute address data for reading the
Bit is set to “0” or “1” (this is one address
Because the position occupies 2 bytes, or 2 absolute addresses)
4-bit touch group address data on the upper
And further place a 5-bit tone color code VN
And a 6-bit key group code
Address, and a total of 16 bits of relative address data
(The address that sets the offset address OAD2 to 0)
Create and add this to the offset address OAD2
Created by As an example, there are 2620 parameter banks.
Types of filter parameters are stored.
2620 parameters corresponding to dresses 0 to 2619
Data storage area. One parameter storage area
Is a 32-byte storage location (32 absolute address locations)
), And a set of filter coefficients for the 16th order
The corresponding parameters are stored. First order fill
The coefficient is stored in a 2-byte storage location, of which
As described above, the 12-bit filter coefficient data
(COE) and 3-bit weighting data (WEI) and 1
It consists of bit even / odd identification data (EO). However, weight
Data (WEI) and even / odd identification data (EO)
Since the parameters are common among the orders, the first
It is stored only in the next storage location, and is stored in the other storage locations.
I do not remember. However, the weighting data (WEI) is
It is also possible to store them independently for each. this
Parameter bank is the parameter address table described above
Address by parameter address read from
Is done. The parameter bank is located in the parameter memory 47.
Fixed absolute address (this is the offset address OAD3
). This para
The absolute address data for reading the meter bank is
The 12-bit parameter address data is
Relative address data (set offset address OAD3 to 0
Address) in the upper 12 bits of
Create the relative address data and offset it
It is created by adding to the address OAD3. This
The lower 5 bits of the absolute address data in 32 steps
By changing sequentially, depending on the parameter address
For the 16th order in one parameter storage area specified by
A set of filter parameters is sequentially read. The hierarchical parameters as shown in FIG.
Data memory structure can save memory capacity
This is advantageous. Without doing this, 44 key glue
All of the combinations of 16 tones, 16 touch groups
(22528 patterns) corresponding to individual filter parameters
Data is stored, the storage of 22528 x 32 bytes
Although the capacity is required, the parameters shown in FIG.
1408 (= 44 × 32) × 32 bytes in the address table
And the parameter bank of 2620 x 32 bytes
Only the required storage capacity of 4028 x 32 bytes
No. In other words, a key group, tone, and touch group
Filter parameters are the same even if they are different
In some cases, 2252 can be used.
Share 2620 parameters for 8 combinations
To save memory capacity.
ing. <Parameter processing unit 45,
Parameter selector 46, parameter memory 47, parameter
Meter supply circuits 48, 49: FIG. 14> Parameter processing
The singing unit 45 operates in the static mode described above.
In order to read the parameter memory 47 as described above,
Is controlled. In the program memory 451,
The read control of the parameter memory 47 as described above is executed.
The program to be executed is stored. Program counsel
The program 452 is a program for reading the program memory 451.
A program step signal PC is generated.
Shift register 86, adder 87, gates 88, 8
9, including the end detection circuit 90, for eight channels
Is performed in a time-division manner. Key-on pulse KO
NP is inverted by the inverter 91 and the control input of the gate 88 is input.
Join forces. This key-on pulse KONP is a key press.
The signal becomes “1” at the beginning, and corresponds to each channel.
Are time division multiplexed. Adder 87 shifts
The output of register 86 is provided from gate 89
"1" is added, and the addition result is output to the gate 88.
The data is supplied to the shift register 86 via End detection times
The path 90 is used when the value of the output of the shift register 86 is
Detects whether the last step has been reached.
If the step is not reached, signal “0” is output.
A signal "1" is applied to the control input of the gate 89 via the
The signal "1" instructing 1 count-up is added to the adder 8
7 to be given to the final step
In this case, a signal “1” is output, and the
The signal "0" is given to the gate 89, the gate 89 is closed and
Prevent uncounting. With the above configuration, the program counter 4
52, that is, the step signal PC is a key-on pulse
It is reset to "0" when KONP occurs, and
Every time the shift register 86 makes a round (every 8 time slots)
2) Count up by 1 and finally reach the final step
Then, the counting is stopped. Programs as an example
The number of steps is 37 and is output from the counter 452.
The step signal PC changes from “0” to “36” (final step).
). The step signal PC is
The output of the star 86 is 8 channels for time division multiplexing.
It is heavy. The program memory 451 is input
The selection control signal SE according to the step of the step signal PC
LC1 to SELC4 are read and the offset address
Address data for reading the memory 453
put out. The offset address memory 453 stores the offset described above.
In this case, the values of the set addresses OADS to OAD3 are stored.
Off read from offset address memory 453
Set address data ADOF (of OADS to OAD3)
) Is input to the adder 454. Adder 454
Is relative address data R provided from selector 455.
Add ADD and offset address data ADOF
And outputs the output as address data PRAD as a parameter.
Of the data memory 47. The key group address register 456,
Switch group address register 457, parameter add
Less register 458 is an 8-stage shift register
Key group address data KEYG,
Group address data TCHG, parameter address
Data PAD is stored in a time-division manner for each channel.
Things. Select on the input side of each register 456-458.
Are provided, and the parameter memory 4
Data read from 7 is input to one input of each selector
Join. The other inputs of the selectors 93 to 95 are connected to the respective registers.
The outputs of the stars 456 to 458 are added. Selectors 93-9
5, the selection control signals SELC2 to SELC4 are programmed.
It is provided from the memory 451, and the program
Read the parameter memory 47 according to the step of the RAM.
Fetch output data into registers 456-458
Or once in registers 456-458
Controls whether data is kept cyclically. As obvious
The key group address described above is stored in the parameter memory 47.
When the address data is read out,
To the touch group described above.
When address data is read, this is
To the address register 457.
When the address data is read,
Select control signal to take in address register 458
SELC2 to SELC4 are generated. Each register 45
Address data KEYG, T stored in 6 to 458
CHG and PAD are input to the selector 455. sector
455 has key code KC, tone code VN and touch
Output from code TCH and program counter 452
Least significant bit PCLSB of the step signal PC
From this step signal PC, "4" (binary "100")
Is also input. Selector 4
At 55, a selection system given from the program memory 451
Input data in a predetermined combination according to the control signal SELC1
Select and select the selected data with relative address data RAD
D at the bit position corresponding to the predetermined weight.
And thus create and output the relative address data RADD
I do. This parameter processing unit 45
The processing contents of the 37 steps executed in
It is. When PC = 0: Key code KC is selected by key group table read processing selection control signal SELC1
And the key address as offset address data ADOF
Reads offset address OADS of loop table
You. Also, the parameter control is performed by the selection control signal SELC2.
Output data of memory 47 to key group address register
456. Thereby, the parameter memory 47
Corresponding to the key code KC from the key group table of
The key group address is read, and this is
56. When PC = 1: Tone code VN and touch code T by touch group table read processing signal SELC1
CH, select TCH as the least significant bit, and V
N to create relative address data RADD
You. Touching as offset address data ADOF
Reads the offset address OAD1 of the loop table
You. In addition, the parameter memory 47 is generated by the signal SELC3.
Output data of the touch group address register 457
Take in. This allows the parameter memory 47 to be touched.
Tone code VN and touch code
Read out the touch group address corresponding to the TCH
This is stored in the register 457. When PC = 2,3: Parameter address
The key group address data KE is output by the stable read processing signal SELC1.
YG, tone code VN, touch group address data
TCHG, the least significant bit PCLSB of the step signal PC
And PCLSB, TCHG, V
N, KEYG and the relative address data RA
Create a DD. Parameter add as data ADOF
Reads the offset address OAD2 of the rest table
You. In addition, the parameter memory 47 is output by the signal SELC4.
Is output to the parameter address register 458.
Embed. Thereby, the parameters in the parameter memory 47 are
Read the appropriate parameter address from the data address table.
And this is stored in register 458. Above
As shown, one parameter address data is 12 bits
2 is stored in a 2-byte storage location (FIG. 2).
0). When bit PCLSB is “0” (PC = 2
Step), lower 8 bits of parameter address data
Data is read out and PCLSB is "1" (PC = 3
Step), the upper 4 bits of the parameter address
Data is read. In the selector 95, this parameter
Data address data is parallelized to 12-bit data
The bit positions and store them in register 458
You. When PC = 4 to 35: Parameter van
Parameter address data PAD according to the read processing signal SELC1.
And the step signal PC-4 obtained by subtracting 4 is selected, and the least significant video
Relative to the PC-4 and PAD in this order.
Create data RADD. Also, data ADOF and
The offset address OAD3 of the parameter bank
read out. The signal PC-4 has 32 steps of PC = 4 to 35.
Value changes from "0" to "31"
You. Therefore, 3 specified by the parameter address
A set of filter parameters consisting of 2 bytes (see FIG. 20)
1) from the parameter bank of the parameter memory 47
They are read out byte by byte. When PC = 36: Program counter 4
52 is stopped and the filter parameter readout
End Kens. Read from parameter memory 47
The obtained filter parameters are output to the timing synchronization circuit 459.
Is input to This circuit 459 has a program step signal.
Signal PC and decoder 56 of timing signal generation circuit 39
(FIG. 12).
Based on these signals, filter parameters of each order
The data is output in synchronization with the predetermined timing. This same
The output of the initialization circuit 459 is a filter for static mode.
A of the parameter selector 46 as the parameter SPR
Given to the input. To B input of parameter selector 46
Is output from the microcomputer interface 44 (FIG. 10).
The dynamic mode filter parameter DPR
Given. The selection control input SB of the selector 46 is
Dynamic /
The static selection signal DS is provided, and the dynamic mode
In the load mode, select the B input parameter DPR and
In the lock mode, the parameter SPR of the A input is selected. The output of the selector 46 is a parameter for each of the A and B systems.
The signals are input to the meter supply circuits 48 and 49. A series circuit
Although only a detailed example is shown in FIG.
It is good. In the parameter supply circuit 49, a distribution circuit
485 is a parameter serially given from the selector 46.
Regarding channels A to 4 of A series in meter data
Capture data and parallelize it for each channel
Together with the filter coefficient data (COE for channel 1)
A1), weighted data (WEIA in channel 1)
1) of even / odd identification data (EOA1 in channel 1)
Separately parallelize them and store them for each channel.
It distributes to roads 481-484. Such distribution control
For this purpose, an appropriate timing signal TS2 is
The signal generated by the decoder 56 of the raw circuit 39 (FIG. 12)
It is provided to the distribution circuit 485. The storage circuits 481 to 484 correspond to channel 1
A detailed example is given below, but the same applies to other channels.
It is. The 12-bit filter coefficient data COEA1 is
16-stage shift register 9 via selector 96
7 is input. This filter coefficient data COEA1 is
Data of 16th order in 16 time slots
Divided and multiplexed, this 16th order data is shifted
The data is taken into each stage of the register 97. Shift cash register
The contents of the star 97 are circulated and held through the selector 96.
You. The 3-bit weight data WEIA1 is a latch circuit
98. 1-bit even / odd identification data EOA1
Is input to the latch circuit 99. Selector 96 and
The control of the switch circuits 98 and 99 is performed by an appropriate control signal (not shown).
Is performed at an appropriate timing. That is,
In the tick mode, the parameter responds to the start of the key press.
Parameters for the 16th order read from the meter memory 47
Data is synchronized with the timing synchronization circuit 459 and the selector.
46, input to the storage circuit 481 via the distribution circuit 485
The selector 96 sets the 16th order in synchronization with the timing
The filter coefficient data COEA1 for the shift register 9
7 and the latch circuits 98 and 99 store the weighted data.
WEIA1 latches even / odd identification data EOA1. Less than
Later, a new press key is assigned to that channel.
Until the shift register 97 and the latch circuits 98 and 99
The memory is kept. On the other hand, when in dynamic mode
Is selected from the microcomputer interface 44 (FIG. 10).
8 and the 8th order dynamics via the distribution circuit 485
Timing to which the parameter data DPR for
Of the parameter data DPR in synchronization with the
Shift register for several minutes of filter coefficient data COEA1
97, and the weighting data WEIA1 is latched
Path 98 to latch the even / odd identification data EOA1
Latch on road 99. Later, for new dynamic control
Until the parameter data DPR is given, the shift register
The storage of the star 97 and the latch circuits 98 and 99 is retained.
In the dynamic mode, the shift register
Corresponds to 9th to 16th out of 97 16 stages
Dynamic control parameters for the 8th order in 8 stages
Store the filter coefficient data of
The contents of the eight stages are set to 0. Shift register of each of storage circuits 481 to 484
The filter coefficient data output from the
86, where according to the timing signal TS3
Each channel is sequentially selected and time-division multiplexed.
You. Thus, the filter coefficients for channels 1-4
The data is time-division multiplexed and the A-series filter coefficient data
A-sequence multiplier and accumulator as COEA
41 (FIG. 13). Each storage circuit 481-48
4 is output from the latch circuit 98 of FIG.
The timing signal TS4
Are sequentially selected in accordance with
Weighted. Channel 1 thus time-division multiplexed
WEIA are weighted data WEIA of A series
It is supplied to the accumulator section 41 (FIG. 13). Each memory times
Each latch latched by the latch circuit 99 of the paths 481 to 484.
Even / odd identification data EOA1 to EOA4 of channels 1 to 4 are
State memories 401 to 404 of corresponding channels
(FIG. 13). <Pitch synchronization output circuit 50: FIG. 15>
In 5, the B input of the selector 501 is multiplied by the A sequence.
From the vessel and accumulator section 41 (FIGS. 10 and 13).
The filtered tone signal samples of channels 1-4
Pull value data SMA is given in a time-division multiplexed manner. FIG.
In the latch circuit 85 of FIG.
The timing at which the filtered output is captured is as shown in SU of FIG.
The last accumulated time slot in the column of M (shaded area)
As a result, the filtered
The channel timing of the sample value data SMA is
As shown in FIG. B input to C input of selector 501
Output from the column multiplier and accumulator unit 43 (FIG. 10).
The filtered tone signal of channels 5 to 8
Pull value data SMB is given in a time-division multiplexed manner. this
The channel timing of the data SMB is as shown in FIG.
is there. The A input of the selector 501 has eight stages.
The output of the shift register 502 is provided, and the selector 5
01 is input to the shift register 502. This
Selector 501 and shift register 502
The filtered sample value data of channels 1 to 8 is
One time slot as shown in the channel timing of S1
Time-division multiplexing according to high-speed time-division timing per unit
It is to make it. The decoder 56 of FIG.
"1" at the im slots 57, 13, 26, 46
Timing signal 1 REGLDA and time slot 1
Timing at which "1" is set at 1, 31, 44, and 64
A signal 1REGDB is generated, which is selected in FIG.
B selection control input SB and C selection control input SC
Given. As a result, the data S given to the B input
In MA, data of channel 1 is in time slot 5
7 (this is the channel timing of PS1 shown in FIG. 2)
(Corresponding to the timing of channel 1)
The data of channel 2 is stored in time slot 13 (FIG. 2).
At the timing of channel 2 of PS1).
The data of channel 3 is stored in time slot 26 (PS in FIG. 2).
1 channel 3 timing)
The data of the file 4 is stored in the time slot 46 (PS1 of FIG. 2).
(Timing of channel 4). Also, C input
Out of the data SMB given to
Is time slot 11 (channel 5 of PS1 in FIG. 2).
Timing), and the data of channel 6 is
Im slot 31 (tie of channel 6 of PS1 in FIG. 2)
), And the data of channel 7 is
Lot 44 (timing of channel 7 of PS1 in FIG. 2)
The data of channel 8 is selected in the time slot.
At 64 (timing of channel 8 of PS1 in FIG. 2)
Selected. Timing signals 1REGLDA, 1REG
A signal obtained by inverting the LDB by the NOR circuit 503 is output from the selector 50.
1 A selection control input SA. Therefore,
At each timing, each
The filtered sample value data for the channel
At the outside timing, the shift register 502 keeps the data in a circular manner.
Is done. The output of the shift register 502 is the selector 504
A input of The output of the selector 504 has eight stages.
Is input to the shift register 505 of the page. Shift cash register
The output of the star 505 is input through the B input of the selector 504.
It is returned to the force side. Selector 504 and shift register 5
Reference numeral 05 denotes the tone signal output from the digital filter.
This is for resampling in synchronization with the switch. C
Input selector SA of the selector 504 has an input interface
Source 38 (FIG. 11).
Period signal PS1D is transmitted through a delay circuit 506 of 8 time slots.
Is entered via In FIG. 11, the pitch synchronization signal PS1 is
64 stage shift register 1 via OR circuit 51
00 is input. This shift register 100
The pitch synchronization signal delayed by the time slot is AND circuit 1
01 and delayed for 40 time slots
48 time slot delay input to AND circuit 102
The result is input to the AND circuit 103, and 64 times
The signal delayed by the slot is input to the AND circuit 104.
You. The other inputs of the AND circuits 101 to 104 are shown in FIG.
Timing signal PSS generated from the second decoder 56
1 to PSS4 are respectively input. Each AND circuit 101-
The output of 104 is applied to OR circuit 105 and delayed
The pitch synchronization signal PS1D is obtained. Each signal PSS1
The generation timing of PSS4 is shown in parentheses in FIG.
As you did. There, for example, "1y8"
Display is the first time slot in 8 time slot cycle
Indicates that the signal "1" is generated. Therefore, Taimin
Is "1y8, 3y8" in the case of the switching signal PSS1?
The first and third time slots in an eight time slot cycle
A signal "1" is generated for each lot. Each signal in FIG.
The display in parentheses of PSS1 to PSS4 and the display of PS1 in FIG.
As you can see from the channel timing,
The signal PSS1 is the tie between channels 1 and 3 in PS1.
And PSS2 is the channel in PS1.
It becomes “1” at the timing of channels 2 and 6, and PSS3 becomes
"1" at the timing of channels 3 and 7 in PS1
And PSS4 is the channel 4 and 8 of PS1
It becomes "1" at the timing. Thus, channel 1
And 5 pitch synchronization signals PS1 are 24 time slots, 2
PS1 of and 6 is 40 time slots, PS1 of 3 and 7 is
48 time slots, PS1 of 4 and 8 are 64 time slots
, The pitch synchronization signal P delayed from the delay
S1D. Thus the delay time depending on the channel
The reason is that the adaptive digital filter device
21 (FIG. 10) of each channel 1-4, 5-8
This is because the calculation timing is adjusted. Referring back to FIG. 15, the delayed pitch synchronization signal
PS1D is further delayed by 8 time slots by the delay circuit 506
Then, it is supplied to the input SA of the selector 504. SEREC
Data 504 is a signal that the signal PS1D of a certain channel is "1".
The filtered sampled value data for that channel.
From the shift register 502 and the shift register 50
Enter 5 Otherwise, shift register 50
5 is cyclically held via the B input of the selector 504.
It is. Thus, the selector 504 and the shift register 5
In the circuit 05, the filtered sun
The pull value data is the pitch of the musical tone that should be generated on that channel.
Resampled in synchronization with the switch. <Pitch Synchronous / Asynchronous Off of Filter Operation
Change> from microcomputer interface 44 (FIG. 10) to FIG.
Pitch synchronous / asynchronous designation signal given to the OR circuit 51
No. PASY is always used when performing a filter operation in pitch synchronization.
And the input interface 38 is pitch-synchronized.
Filter operation request signals φF1 to φF1 in response to signal PS1
F8 and generate a delayed pitch synchronization signal PS1D
You. Therefore, when the pitch synchronization signal PS1 is generated,
Synchronized with the pitch of the tone signal to be filtered
Digital filter operation is performed in the sampling cycle.
You. As a result, the obtained filter characteristics
Be a point. Perform filter operation without synchronizing to pitch
In this case, always specify the pitch synchronous / asynchronous designation signal PASY.
Set to “1”. Therefore, the output of the OR circuit 51 in FIG.
Always "1" regardless of the presence or absence of the pitch synchronization signal PS1
Becomes Therefore, the input interface 38
At regular intervals every operation cycle (64 time slots)
Filter operation request signals φF1 to φF8 and signal PS1D.
Occur. Therefore, the support in digital filter operation
The sampling frequency is constant regardless of the pitch (for example, 50
kHz), and the obtained filter characteristics are fixed
Be a point. <Modification> Pitch synchronization output shown in FIG.
The circuit 50 uses the shift registers 502 and 505
Pitch synchronization processing is performed by channel time division.
Not limited to this, storage circuits are provided in parallel for each channel,
The pitch synchronization processing may be performed in a row. The above
In the example, the coefficient shows symmetry as a digital filter.
Although an FIR filter is used, the present invention is not limited to this.
A number of FIR filters may be used. Also, filter type
The formula is not limited to FIR, but IIR (infinite impulse response) and so on.
May be used. As shown in FIG.
The storage format of the parameter memory is limited to this.
Various changes are possible. Also, parameter memory
The method of addressing is not limited to the procedure shown in the above embodiment,
Various changes are possible. For example, in the embodiment,
Access the touch table first, then touch group
Cable, but this may be reversed.
No. In FIG. 14, the data is read out to the program memory 451.
The microprogramming method that stores the procedure in advance is adopted.
Reading the parameter memory 47.
The micro program method
Regardless of the formula, a completely hard-wired circuit or a complete
Read control by all software programs
You may make it. In the above embodiment, the parameter determining factor
Are three types: pitch / range, key touch, and tone type
However, it is not limited to this. For example, parameter determination of elapsed time
Factors that change with the passage of time
The filter parameter may be read. On the spot
In this case, the parameter processing unit 45 in FIG.
It shall be appropriately designed so that it can operate even during sound production.
In addition, operation of appropriate manual controls such as brilliance controls
The output according to the quantity may be used as a parameter determinant.
No. In the above-described embodiment, the present invention is applied to a double tone electronic musical instrument.
Is applied to the single-tone electronic musical instrument.
Of course, it can be applied. In addition, a dedicated
Not only for musical instruments, but also for musical signal generation or processing
In general, the present invention can be applied. The above
In the example, the adaptive digital
Digital music signal signal input to the
The pull value data itself is sampled in synchronization with the pitch
It is assumed that the state has been
Absent. For example, with a fixed sampling cycle that is asynchronous in pitch
Digitally sampled digital tone signal
Even when inputting to the filter device, the pitch synchronization signal
Do not resample the input digital tone signal.
To perform the filter operation synchronized with the pitch.
Just do it. In the above embodiment, the pitch synchronization signal
The path is contained within the tone generator and occurs there
Adaptive digital filter
It is introduced into the device, but is not limited to this. An example
For example, a digit with a sampling period synchronized with the pitch
When inputting a musical tone signal to a digital filter,
Of change in sample value data of digital tone signal
To generate a pitch synchronization signal,
Filter operation is controlled by the pitch synchronization signal
You may make it. As described above, according to the present invention, the timbre
And the total number of combinations of the first and second parameter determinants
Parameters to be compared and stored in parameter storage means
Saves memory capacity by reducing the number of sets
can do. In particular, key touch, range or time
For various combinations of various types of parameter determinants such as progress
Therefore, when trying to perform delicate tone control,
Such sound without grandchild by parameter memory configuration
This is advantageous because color control can be performed. Also this
According to the invention, the first and second group address storage means are provided.
Hierarchical including stages and parameter address storage means
Adopt addressing configuration and use parameter storage
And read the parameters from the
Here, the first group address storage means
Group the values of the first parameter determinant for each timbre.
The first group related to the group for each tone
Because the address data is stored, it is optimal for the tone
Grouping is possible, and the optimal parameters
Meter generation can be performed with a simple configuration.
The effect is excellent. Also, group
This reduces the overall data volume and simplifies the configuration.
Can be abbreviated. Furthermore, parameter address storage
The means comprises a timbre, a first parameter determinant and a second parameter determinant.
Parameter corresponding to the combination of parameter determinants of
The parameter to be read from the data storage means
Parameter address indicating the address in the storage means
Data is stored, but the stored
Each of the parameter address data includes the tone color,
The first parameter determinant group and the second parameter
Data for different combinations of groups of data determinants.
Pointing to the same address in parameter storage means
Therefore, even if the combinations are various,
Without increasing the amount of storage parameters
It is possible to supply appropriate parameters according to various combinations.
It has an excellent effect.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the overall configuration of an electronic musical instrument according to one embodiment of the present invention. FIG. 2 is a timing chart showing timings of main signals in the embodiment. FIG. 3 is a block diagram showing an example of a pitch synchronization signal generation circuit included in the tone generator of FIG. 1; FIG. 4 is a block diagram showing a basic configuration of an FIR filter. FIG. 5 is a graph showing an example of the symmetry of the impulse response in the linear phase FIR filter when the order N is an odd number. FIG. 6 is a graph showing an example of the symmetry of an impulse response in a linear phase FIR filter when the order N is an even number. FIG. 7 is a graph showing an example of a frequency response characteristic of a linear phase FIR filter when an order N is an odd number. FIG. 8 is a graph showing an example of a frequency response characteristic of the linear phase FIR filter when the order N is an even number. FIG. 9 is a flowchart illustrating an example of a procedure for obtaining a filter coefficient. FIG. 10 is a block diagram showing an example of the adaptive digital filter device in FIG. 1; FIG. 11 is a block diagram showing an example of an input interface in FIG. 10; FIG. 12 is a block diagram illustrating an example of a timing signal generation circuit in FIG. 10; 13 is a block diagram showing an example of a state memory, a multiplier, and an accumulator unit in FIG. 10 (that is, an example of an FIR digital filter circuit). FIG. 14 is a block diagram showing an example of a parameter processing unit and a parameter supply circuit in FIG. 10; FIG. 15 is a block diagram showing an example of a pitch synchronization output circuit in FIG. 10; FIG. 16 is a timing chart showing an example of generation of various signals for controlling filter operation timing. FIG. 17 is a schematic diagram for explaining a basic operation of an FIR type filter operation in a case where filter characteristics of an even order (32 order) are realized in the digital filter circuit shown in FIG. 13; FIG. 18 is a diagram showing a case in which an odd-order (31st-order) filter characteristic is realized in the same digital filter circuit.
5 is a schematic diagram for explaining a basic operation of an IR-type filter operation. FIG. 19 is a diagram showing filter operation timings for eight channels in the digital filter circuits of the A and B2 series as shown in FIG. 13; FIG. 20 is a diagram showing an example of a storage format in the parameter memory shown in FIGS. 10 and 14. DESCRIPTION OF SYMBOLS 10 keyboard 11 key touch detector 18 tone generator 19 pitch synchronizing signal generating circuit 21, 22 adaptive digital filter device 40, 42 state memory 41, 43 multiplier and accumulator unit 45 parameter processing unit 47 parameter memory 50 pitch Synchronous output circuit

Claims (1)

(57) [Claims] Parameter storage means for storing a plurality of sets of parameters, timbre information, first parameter determinant information, and second
An input unit for inputting parameter determinant information; and a group of values of the first parameter determinant for each timbre.
The first group related to the group for each tone
First group address storage storing address data
Means and grouping each value of the second parameter determinant
And second group address data related to the group.
A second group address storing means for storing the timbre, the first parameter determining factor, and the second parameter.
It is one that each store parameters address data indicating the address in the parameter of the parameter memory means to correspond to a combination of data determinants read from the parameter storage unit, the stored the respective para
The tone color and the first parameter are included in the meter address data.
Determinant group and second parameter determinant
A parameter address storage means for designating the same address in the parameter storage means for different combinations of child groups ; and input of the timbre information and the first parameter determinant information.
The timbre specified by the input and the
A specific first corresponding to one parameter determinant combination
Group address data of the first group address.
Read out from the storage means, and read the second parameter
Data corresponding to the input of the determinant information,
2 group address data in the second group address.
The first and second readouts from the
A specific parameter corresponding to the combination of group addresses
Reads over data address data from said parameter address memory means, the read parameter address comprising a read means for reading a set of parameters from said parameter memory means in accordance with the data, for the read-out parameter settings or control of the tone A parameter supply device for an electronic musical instrument adapted to be supplied to the electronic musical instrument. 2. It said first and second parameter determining factors, parameter supply device for an electronic musical instrument according to claim 1 in which each corresponding to the pitch or tone range information and touch information tone to be generated.