JPS61151347U - - Google Patents
Info
- Publication number
- JPS61151347U JPS61151347U JP3599985U JP3599985U JPS61151347U JP S61151347 U JPS61151347 U JP S61151347U JP 3599985 U JP3599985 U JP 3599985U JP 3599985 U JP3599985 U JP 3599985U JP S61151347 U JPS61151347 U JP S61151347U
- Authority
- JP
- Japan
- Prior art keywords
- ground
- ground terminal
- dielectric substrate
- noise transistor
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Microwave Amplifiers (AREA)
- Networks Using Active Elements (AREA)
Description
第１図は、本考案の高周波低雑音トランジスタ
の取付構造の一実施例の断面図であり、第２図は
、第１図の平面図であり、第３図は、第１図の等
価回路図であり、第４図は、本考案の高周波低雑
音トランジスタの取付構造の他の実施例の断面図
であり、第５図は、第４図の平面図であり、第６
図は、第４図の等価回路図であり、第７図は、従
来の高周波低雑音トランジスタの取付構造の一例
の断面図であり、第８図は、第７図の平面図であ
り、第９図は、第７図の等価回路図である。
１：高周波低雑音トランジスタ、４：ソース端
子、５：接地電極、６：誘電体基板、７：スルー
ホール。
FIG. 1 is a sectional view of an embodiment of the mounting structure for a high frequency low noise transistor of the present invention, FIG. 2 is a plan view of FIG. 1, and FIG. 3 is an equivalent circuit of FIG. 1. 4 is a sectional view of another embodiment of the mounting structure for a high frequency low noise transistor of the present invention, FIG. 5 is a plan view of FIG. 4, and FIG.
4 is an equivalent circuit diagram of FIG. 4, FIG. 7 is a sectional view of an example of the mounting structure of a conventional high frequency low noise transistor, and FIG. 8 is a plan view of FIG. FIG. 9 is an equivalent circuit diagram of FIG. 7. 1: High frequency low noise transistor, 4: Source terminal, 5: Ground electrode, 6: Dielectric substrate, 7: Through hole.
Claims (1)
に、２個の接地端子を有する高周波低雑音トラン
ジスタを配設し、この高周波低雑音トランジスタ
の一方の接地端子を前記誘電体基板に設けられた
スルーホールにより前記接地電極と電気的に接続
し、他方の接地端子を遊端状として、この他方の
接地端子と前記接地電極との間に前記誘電体基板
を介在させた容量が形成されるように構成したこ
とを特徴とする高周波低雑音トランジスタの取付
構造。 A high frequency low noise transistor having two ground terminals is disposed on the upper surface of a dielectric substrate having a ground electrode provided on the lower surface, and one ground terminal of the high frequency low noise transistor is provided on the dielectric substrate. The other ground terminal is electrically connected to the ground electrode through a through hole, and the other ground terminal is in a free end shape, so that a capacitance is formed between the other ground terminal and the ground electrode with the dielectric substrate interposed therebetween. A mounting structure for a high-frequency, low-noise transistor characterized by being configured as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3599985U JPH0441616Y2 (en) | 1985-03-12 | 1985-03-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3599985U JPH0441616Y2 (en) | 1985-03-12 | 1985-03-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61151347U true JPS61151347U (en) | 1986-09-18 |
| JPH0441616Y2 JPH0441616Y2 (en) | 1992-09-30 |
Family
ID=30540793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3599985U Expired JPH0441616Y2 (en) | 1985-03-12 | 1985-03-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0441616Y2 (en) |
-
1985
- 1985-03-12 JP JP3599985U patent/JPH0441616Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0441616Y2 (en) | 1992-09-30 |
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