JPS6114665B2 - - Google Patents
Info
- Publication number
- JPS6114665B2 JPS6114665B2 JP2123177A JP2123177A JPS6114665B2 JP S6114665 B2 JPS6114665 B2 JP S6114665B2 JP 2123177 A JP2123177 A JP 2123177A JP 2123177 A JP2123177 A JP 2123177A JP S6114665 B2 JPS6114665 B2 JP S6114665B2
- Authority
- JP
- Japan
- Prior art keywords
- pellet
- bump
- internal wiring
- bumps
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2123177A JPS53105967A (en) | 1977-02-28 | 1977-02-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2123177A JPS53105967A (en) | 1977-02-28 | 1977-02-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53105967A JPS53105967A (en) | 1978-09-14 |
| JPS6114665B2 true JPS6114665B2 (pm) | 1986-04-19 |
Family
ID=12049246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2123177A Granted JPS53105967A (en) | 1977-02-28 | 1977-02-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53105967A (pm) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5572062A (en) * | 1978-11-27 | 1980-05-30 | Nec Corp | Semiconductor device and preparation thereof |
-
1977
- 1977-02-28 JP JP2123177A patent/JPS53105967A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53105967A (en) | 1978-09-14 |
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