JPS61145893A - Substrate for electronic component carrier - Google Patents
Substrate for electronic component carrierInfo
- Publication number
- JPS61145893A JPS61145893A JP26978184A JP26978184A JPS61145893A JP S61145893 A JPS61145893 A JP S61145893A JP 26978184 A JP26978184 A JP 26978184A JP 26978184 A JP26978184 A JP 26978184A JP S61145893 A JPS61145893 A JP S61145893A
- Authority
- JP
- Japan
- Prior art keywords
- component carrier
- substrate
- soldering
- carrier
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、電子部品搭載用キャリヤに関する。[Detailed description of the invention] Industrial applications The present invention relates to a carrier for mounting electronic components.
従来の技術
半導体チップを搭載した印刷配線キャリヤーとしては、
基板の上下すなわち、両面に電極を付して、上部を半導
体チップのダイ及びワイアポンディングによる接続用に
用い、基板の側面あるいはスルーホールによって下部の
はんだ付は電極に電気的に連絡する構造が一般的である
。As a printed wiring carrier equipped with conventional technology semiconductor chips,
Electrodes are attached to the upper and lower sides of the board, that is, both sides, and the upper part is used for connection by die and wire bonding of the semiconductor chip, and the lower part is electrically connected to the electrodes by soldering through the side of the board or through holes. Common.
発明が解決しようとする問題点
従来の印刷配線キャリヤーには、次に述べる構造的問題
点がある。すなわち、下面の電極をはんだ付けするに当
って、前記キャリヤーを接続する印刷配線板の導体との
間が密着するために、はんだ付けをおこなう隙間がなく
、周囲を囲うようなはんだ付けを行なっていた。また、
はんだめ・つき、はんだクリームの印刷のようにはんだ
を前もってはんだ付は面に供給しておいても、印刷配線
キャリヤーの自重又は接続時の加圧のため、はんだがは
み出し、適切な厚さを保つ事ができないが、流出はんだ
による印刷導体間の短絡事故の原因となっていた。Problems to be Solved by the Invention Conventional printed wiring carriers have the following structural problems. That is, when soldering the electrodes on the bottom surface, the carrier is in close contact with the conductor of the printed wiring board to which it is connected, so there is no gap for soldering, and the soldering is done in a way that encloses the periphery. Ta. Also,
Even if solder is supplied to the soldering surface in advance, such as when printing solder cream, the solder may bulge out due to the weight of the printed wiring carrier or the pressure applied during connection, making it difficult to obtain the appropriate thickness. However, leaked solder caused short circuits between printed conductors.
問題点を解決するだめの手段
本発明は、スルーホール接続孔の下面に、はんだ処理耐
熱性レジストによる微小突起を形成した電子部品キャリ
ヤ用基板である。Means for Solving the Problems The present invention is a substrate for an electronic component carrier in which minute protrusions made of a soldering heat-resistant resist are formed on the lower surfaces of through-hole connection holes.
作 用
電子部品キャリヤ用基板のスルーホール接続孔の下面に
、回礼を埋め、一部が周辺ランド部にまたがるような耐
熱性レジストによる微小突起を設けると、このキャリヤ
用基板を支持する印刷配線板の表面導体との間に適切な
ギャップを形成してはんだ接合（はんだペーストの印刷
でもディップソルダー液の侵入でもよい）部を形成する
のに好都合である。Function: If a small protrusion made of heat-resistant resist is provided on the bottom surface of the through-hole connection hole of the electronic component carrier substrate by filling the circuit and partially extending over the peripheral land portion, the printed wiring board supporting this carrier substrate can be formed. It is convenient to form a solder joint (which may be printed with solder paste or penetrated by dip solder liquid) by forming an appropriate gap between the surface conductor and the surface conductor of the solder.
実施例 本発明の実施例を第１図の断面図により詳しくのべる。Example An embodiment of the present invention will be described in detail with reference to the sectional view of FIG.
キャリヤ用基板１の両面に導体層２を有し、キャリヤ用
基板１を貫通する孔を埋めて、導電ペイント３によるス
ルーホール接続体によって、両面の導体層２を互いに接
続する。そして、導電ペイント３０表面は、必要に応じ
て、銀めっき層４を形成し、十分な導電性を確保する。A carrier substrate 1 has conductor layers 2 on both sides, and holes penetrating through the carrier substrate 1 are filled, and the conductor layers 2 on both sides are connected to each other by a through-hole connector made of conductive paint 3. A silver plating layer 4 is formed on the surface of the conductive paint 30, if necessary, to ensure sufficient conductivity.
次に、基板１の表面側導体層２上に半導体チップ６を載
置し、ポンディングワイア６で接続する。Next, a semiconductor chip 6 is placed on the surface-side conductor layer 2 of the substrate 1 and connected with bonding wires 6.
される。このとき、スルーホール接続孔の下面に、耐熱
性レジストによる微小突起１ｏを設けると、はんだ層９
の厚みを確保する間隙が得られる。be done. At this time, if a minute protrusion 1o made of a heat-resistant resist is provided on the bottom surface of the through-hole connection hole, the solder layer 9
A gap is obtained to ensure the thickness of .
微小突起１ｏの形成は、孔の下面にレジスト印刷後、熱
又は光硬化を行なう。第２図に下面各層の厚さの関係を
示す。キャリヤ下面のスルーホールランドの厚さＨ２に
スルーホールめっき又はスルーホール導電ペイントの厚
さＨ３に対して、絶縁性の樹脂厚さＨ４の印刷付加層が
得られる。こうして部品キャリヤー裏面の導体からの突
出高さとしてＨ２＋Ｈ３＋Ｈ４が厚さ７６μｍとして得
られる。本発明においては、このレジスト印刷が、部品
キャリヤ１のスルーホール孔の物理的閉鎖を兼用してい
るのが特徴であり、下面はんだ付けの際に生ずる。はん
だ粒、はんだ付は用フラックスの侵入を防ぐと共に、湿
気・水分の侵入も防いでいる。なお、はんだ接合後、外
囲樹脂１１で封止される。耐熱性レジストとしては、エ
ポキシ又はポリイミド樹脂の□熱硬化型のものもしくは
光硬化性を賦与したエポキシアクリレイトを用いる。特
に無溶剤型としたものが作業し易い、なお印刷は部品キ
ャリヤの底部電極面を上面として、下面の突出部を治具
によシ平面化し、金属マスクによる厚目の印刷を行なう
、こうしてスルーホール接続孔が閉鎖され、その下面ラ
ンド上に耐熱性レジスト層を追加した部品キャリヤを得
る部品キャリヤと印刷配線板とのはんだ接合は、はんだ
ディップでおこなう事ができる。勿論はんだペーストの
印刷とり７０ウソルダリングでおこなってもよく、実施
態様例によれば、導体層２と配線導体８との面同志のは
んだ付は層が厚さ７６〜１２６μに形成できる。The microprotrusions 1o are formed by printing a resist on the lower surface of the hole and then thermally or photocuring. FIG. 2 shows the relationship between the thicknesses of each layer on the bottom surface. A printed additional layer of insulating resin having a thickness H4 is obtained with respect to the thickness H2 of the through-hole land on the lower surface of the carrier and the thickness H3 of the through-hole plating or through-hole conductive paint. In this way, the protrusion height from the conductor on the back surface of the component carrier is obtained as H2+H3+H4 with a thickness of 76 μm. The present invention is characterized in that this resist printing also serves as the physical closure of the through-holes of the component carrier 1, which occurs during bottom-side soldering. Solder grains and soldering joints prevent the intrusion of flux as well as moisture and moisture. Note that after soldering, it is sealed with the surrounding resin 11. As the heat-resistant resist, a thermosetting type of epoxy or polyimide resin or epoxy acrylate imparted with photocurability is used. The solvent-free type is especially easy to work with.For printing, use the bottom electrode surface of the component carrier as the top surface, flatten the protrusion on the bottom surface with a jig, and print thickly using a metal mask. Soldering of the component carrier and the printed wiring board to obtain a component carrier with the hole connection holes closed and a heat-resistant resist layer added on its lower surface land can be performed by soldering dip. Of course, printing of the solder paste may be performed by 70 soldering, and according to the embodiment, the conductor layer 2 and the wiring conductor 8 can be soldered face to face to form a layer having a thickness of 76 to 126 μm.
発明の効果
部品キャリヤの製造プロセスを増加することなく、キャ
リヤ下部に樹脂層によるスルーホール部の閉鎖形成をす
ることができ、従来問題であったはんだ付けを樹脂層の
脚を用いてキャリヤの下面導体と印刷配線板導体の平行
面間に、はんだ層を通常のディップ又はリフロウソルダ
リング工程で形成できる。Effects of the invention: Without increasing the manufacturing process of the component carrier, the through-hole portion can be closed with a resin layer at the bottom of the carrier, and the conventional problem of soldering can be solved by using the legs of the resin layer on the bottom surface of the carrier. A solder layer can be formed between the parallel surfaces of the conductor and the printed wiring board conductor using a conventional dip or reflow soldering process.
第１図は本発明の実施例を示す断面図、第２図は同要部
断面図である。
１・・・・・・部品キャリヤ、２・・・・・・キャリヤ
ー面の導体、３・・・・・・導電ペイント、４・川・・
銀めっき層、６・・・・・・半導体チップ、６・・・・
・・ボンディングワイア、７・・・・・・印刷配線板、
８・・・・・・印刷配線板の上面導体、９・・・・・・
はんだ層、１０・・・・・・レジスト微小突起、１１・
・・・・・部品キャリヤの封じ樹脂。FIG. 1 is a cross-sectional view showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of essential parts thereof. 1...Parts carrier, 2...Conductor on carrier surface, 3...Conductive paint, 4. River...
Silver plating layer, 6... Semiconductor chip, 6...
...Bonding wire, 7...Printed wiring board,
8...Top conductor of printed wiring board, 9...
Solder layer, 10...Resist microprotrusions, 11.
...Sealing resin for parts carrier.
Claims (1)
トによる微小突起を形成した電子部品キャリヤ用基板。A substrate for electronic component carriers with minute protrusions made of soldering heat-resistant resist formed on the bottom surface of through-hole connection holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26978184A JPS61145893A (en) | 1984-12-20 | 1984-12-20 | Substrate for electronic component carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26978184A JPS61145893A (en) | 1984-12-20 | 1984-12-20 | Substrate for electronic component carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61145893A true JPS61145893A (en) | 1986-07-03 |
| JPH0482079B2 JPH0482079B2 (en) | 1992-12-25 |
Family
ID=17477065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26978184A Granted JPS61145893A (en) | 1984-12-20 | 1984-12-20 | Substrate for electronic component carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61145893A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7650688B2 (en) * | 2003-12-31 | 2010-01-26 | Chippac, Inc. | Bonding tool for mounting semiconductor chips |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4942624A (en) * | 1972-08-23 | 1974-04-22 | ||
| JPS5779652A (en) * | 1980-11-05 | 1982-05-18 | Nec Corp | Resin-sealed semiconductor device |
| JPS57166095A (en) * | 1981-04-07 | 1982-10-13 | Sharp Kk | Circuit board and method of producing same |
| JPS58120662U (en) * | 1982-02-12 | 1983-08-17 | 株式会社日立製作所 | Chippukiyariya |
| JPS59182975U (en) * | 1983-05-20 | 1984-12-06 | 松下電器産業株式会社 | printed wiring board |
-
1984
- 1984-12-20 JP JP26978184A patent/JPS61145893A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4942624A (en) * | 1972-08-23 | 1974-04-22 | ||
| JPS5779652A (en) * | 1980-11-05 | 1982-05-18 | Nec Corp | Resin-sealed semiconductor device |
| JPS57166095A (en) * | 1981-04-07 | 1982-10-13 | Sharp Kk | Circuit board and method of producing same |
| JPS58120662U (en) * | 1982-02-12 | 1983-08-17 | 株式会社日立製作所 | Chippukiyariya |
| JPS59182975U (en) * | 1983-05-20 | 1984-12-06 | 松下電器産業株式会社 | printed wiring board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7650688B2 (en) * | 2003-12-31 | 2010-01-26 | Chippac, Inc. | Bonding tool for mounting semiconductor chips |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0482079B2 (en) | 1992-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2595909B2 (en) | Semiconductor device | |
| JP3060896B2 (en) | Structure of bump electrode | |
| JPH11297889A (en) | Semiconductor package, mounting board and mounting method by use of them | |
| JP3695458B2 (en) | Semiconductor device, circuit board and electronic equipment | |
| JP2870533B1 (en) | Semiconductor device and manufacturing method thereof | |
| US20050074924A1 (en) | Circuitized substrate, method of making same and information handling system using same | |
| JPS61145893A (en) | Substrate for electronic component carrier | |
| JPS622587A (en) | Hybryd integrated circuit for high power | |
| JP2651608B2 (en) | Substrate for mounting electronic components | |
| JP2926902B2 (en) | Printed wiring board | |
| JP2756094B2 (en) | Bump electrodes and components with bump electrodes | |
| JPH01225196A (en) | Manufacture of laminated hybrid integrated circuit | |
| JP4174407B2 (en) | Electronic component storage package | |
| JP2674788B2 (en) | Semiconductor package terminal pins | |
| JPH11163197A (en) | Semiconductor mounting board | |
| JP2830221B2 (en) | Mounting structure of hybrid integrated circuit | |
| KR19990002341A (en) | Printed circuit board for mixing heterogeneous chip parts and manufacturing method | |
| JP2779843B2 (en) | Electronic component mounting board and electronic component package | |
| JP2842013B2 (en) | Hybrid integrated circuit device | |
| JP2564487B2 (en) | Circuit board and hybrid integrated circuit thereof | |
| JPS6272133A (en) | Chip carrier | |
| JPH0513011Y2 (en) | ||
| JPH11243114A (en) | Mounting system for surface-mounting component | |
| JP2797995B2 (en) | Semiconductor device | |
| JPH03269962A (en) | Electrical connecting member |