JPS61145789A - Address allocating circuit - Google Patents

Abstract

PURPOSE:To obtain a general-purpose address allocating circuit by adding the 3rd address decoder which contains the address input terminals connected to the remaining decoding output terminals of the 1st address decoder and the decoding output terminals connected to the remaining address input terminals of the 2nd address decoder respectively. CONSTITUTION:The decoding output lines L1-L3 of a programmable decoder 10 are used as address data buses together with lines L4-L7 used as chip selection lines respectively. Then the output data is changed with change of the memory address. Thus the head address of each chip memory can be changed freely or the easy displacement is possible among memory chips of different capacities as long as the pin distribution is equal just by changing the program of the decoder 10 with no change of the wiring. Furthermore the chip selecting bit of the decoder 10 can be used effectively owing to addition of the 3rd address decoder 12.

Description

DETAILED DESCRIPTION OF THE INVENTION 1L1 The present invention relates to an address allocation circuit, and particularly to an address allocation circuit for allocating an address to select one of a plurality of memory elements or a plurality of input/output elements. .

BACKGROUND ART FIG. 1 shows an example of an addressing circuit for addressing a memory including, for example, a plurality of memory elements. In the figure, for example, two address decoders 1.
2 is provided. The storage contents of these address decoders 1.2 are fixed. Central processing unit (hereinafter referred to as CP)
For example, an 8-bit data bus 8085A (manufactured by Intel Corporation) is used as U)3.

In this CPU 3, data and addresses are transmitted in a time-division manner, so the lower byte of the address (Ao''-A7
) is provided with an address latch circuit 4 for latching the address.

Among the plurality of memory elements U1 to U16, U1 to U8 are 2
It is a byte ROM (read only memory) and U9
~U16 is 2 bytes of RAM (random access memory). These memories have 2 bytes, so the address bits Ao to A+.

up to the address decoder 1.2 is directly supplied to the address input terminal of the memory. Address bits A n
~AIs are each supplied to and decoded by an address decoder 1.2 to select a 2-byte memory chip. The 10/M signal output from CPLI3 is a selection signal for identifying whether to select memory or l10 (input/output) element (not shown), and becomes a low level signal when memory is selected. . In this circuit example, the memory map of the memory elements U1 to L116 is configured as shown in FIG.

Next, the operation when the CPLI 3 reads data stored, for example, at address 1000 in the memory will be described.

First, the CPU 3 sends address information 1000H to the memory via the address bus. At this time, data as shown in FIG. 3 is loaded onto the address bus. Address bits A11-Al1 are supplied to address decoder 1.2, but since the AI4 bit is “0”, address decoder 1 is enabled, and A M bit information is supplied to address decoder 2 via inverter 5. Therefore, the decoder 2 is disabled. Also, since the memory is selected, the low level 1
Since the 0/M signal is outputted, inverted by the inverter 6, and then supplied to the chip selection terminal G+ of each decoder 1, 2, each decoder 1.2 is enabled.

As a result, memory chip U3 is selected based on the function of address decoder 1.2 (see the function table in FIG. 4). Also,
Since address bits Ao=A+o are all 1101+,
The starting address of memory chip U3 is designated. At this time C
When a τ (continuation) signal is output from the PU 3 and input to the memory, the stored contents are read from the specified address and taken into the CPLJ 3 as data information.

In the addressing circuit configured in this way, conventionally, an address decoder 1 provided for chip selection is used.
, 2 are fixed, so if you want to change the address, for example, if you want to change the start address of memory chip U9 from "4000H" to "8000H", use the input terminals of address decoders 1 and 2. It was necessary to change the address bit supplied to G2 from AI4 to A+s, and accordingly, the wiring of the address line had to be changed. Also, when changing the memory capacity using chips with the same bin arrangement! Similar wiring changes were made here as well. This is because, for example, when changing the ROM of U1 to U8 from a 2-byte ROM to a 4-byte ROM, it is necessary to input the address bits A12 to A14 to the address input terminal of the address decoder 1.

As is clear from the above, conventional address allocation circuits are specialized and lack versatility.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a versatile address allocation circuit that can freely allocate memory addresses and easily change memory capacity. do.

The address allocation circuit according to the present invention includes a first address decoder whose address input terminal is supplied with a decoded address signal from the central processing unit, and a part of the address input terminal which is supplied with the decoded address signal from the central processing unit. The remaining part of the address input terminal is connected to a part of the decode output terminal of the first address decoder, and one of the plurality of memory elements or the plurality of input/output elements is connected to each of the plurality of decode output terminals. a plurality of second address decoders that select one of the plurality of second address decoders, and an address input terminal is connected to the remaining decode output terminals of the first address decoder, and each of the plurality of decode output terminals selects one of the plurality of second address decoders. a third address decoder connected to the remainder of the address input terminals of the address decoder;
The first and second address decoders are programmable decoders, and the first and second address decoders are programmable decoders.

A selection signal for selecting the plurality of memory elements or the plurality of input/output elements is supplied to the chip selection input terminal.

@ Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 5 is a block diagram showing one embodiment of the present invention, and FIG. 6 is a circuit diagram embodying it. In FIGS. 5 and 6, decoded address signals A I2-A21 output from CPtJ (not shown) are supplied to address input terminals of a programmable decoder 10 as a first address decoder, and decoded address signals A u is a part A of each address input terminal of the plurality of programmable decoders 111 to 1116 as the second address decoder.
Supplied to O. Programmable decoder 11+~11
A plurality of memory elements or I10 elements (both not shown) are connected to each of the 16 decode output terminals, as in the conventional example shown in FIG. Programmable decoders 10 and 111 to 1116 are composed of ROM or PAL (programmable array logic). PAL uses NAND and NOR, which are the simplest logic circuits, as basic gates, and these are arranged in an orderly manner on a chip.By electrically interconnecting the basic gates, a customer-specific random logic LSI can be constructed. It is.

Chip selection input terminal G of programmable decoder 10 is grounded. Some of the decode output lines L1 to L3 of the programmable decoder 10 are commonly connected as address data buses to the address input terminals Al-A3 of the remaining part of the programmable decoders 111 to 1116, and the remaining decode output lines L4 to L7 are It is connected to an address input terminal of a decoder 12 provided as an address decoder of No. 3. A plurality of decode output terminals of this decoder 12 are connected to programmable decoders 111 to 1116.
are respectively connected to the remaining address input terminals A4.

Each chip selection input terminal of the programmable decoders 111 to 1116 receives a selection signal (1) output from the CPU.
0/M signal) is supplied. In this embodiment, a plurality of memory elements are connected to each decode output terminal of programmable decoders 111 to 1116, and the IO/M signal in this case becomes a memory selection signal.

In this embodiment, the memory decode address is A n to A
20, but this means that for the 8085A CPU, the address bits are Ao''A+5 (64 bytes of memory space), for the 8086, AO~A+s (1M byte of memory space), and for the 80286, the address bits are AO~A23 (16M bytes of memory space). This is because it is (memory space).

In the address allocation circuit having such a configuration, the memory decode address A n is assigned to the programmable decoders 111 to 111.
1116 address input, memory decode address A
Since I2 to A 20 are the address inputs of the programmable decoder 10, 2 is a byte block of 2M.
You can get decoded output up to bytes. In addition, the decode output lines L1~ of the programmable decoder 10
L3 is used as address data bus and 4 to L7
Since the output data is changed by changing the memory address using the chip selection line, you can freely change the start address of each memory chip or change the same bin by simply changing the program of the programmable decoder 10 without changing the wiring. With this arrangement, memory chips with different memory capacities can be easily replaced. Furthermore, by using the third address decoder 12, the chip selection bits of the programmable decoder 10 can be used effectively. Furthermore, the programmable decoder 11
Since some of the address input terminals 1 to 1116 are used as input terminals for memory decode addresses from the CPU, the memory capacity of programmable decoders 11+ to 1116 can be used effectively, and the overall memory area can be expanded. .

In addition, each memory chip has a memory capacity of 2 bytes AO to A 10 4 bytes Ao”-An 8 bytes AO to A I2 16 bytes A o -A 1332 bytes In this case, it is natural to connect the address lines so that the address pits Ao to AI4 are supplied.

Furthermore, in the programmable decoders 111 to 1116, it is of course possible to change the start address of each memory for each decoder, and to connect memory chips with different memory capacities (byte to 2, byte to 4, etc.). However, by changing the program of the programmable decoder 10, the start address of the memory can be changed for each memory chip in a single programmable decoder, or memory chips with different memory capacities (2 bytes, 4 bytes) can be changed. ...) can also be connected.

FIG. 7 is a block diagram showing another embodiment of the present invention. In this embodiment, a programmable decoder 10 is added, and these programmable decoders 10+ to Ion
The configuration is such that a plurality of third address decoders 121 to 12n and programmable decoders (111 to In+6) to (151 to 1n16) are connected to each of the above-mentioned embodiments. The memory area can be expanded and used. Also, in Figure 7, “
By further providing a decoder before the programmable decoders 101 to Ion, the memory area can be further expanded. The storage contents of the decoder in this case may be either fixed or variable.

In each of the above embodiments, the case where memory chips are mainly selected has been described, but the same applies to the case where 110 chips are selected. However, the memory chip and I10
Regarding the discrimination between chips, the 10 output from the CPU
The judgment is made based on whether the /M signal (selection signal) is OII or 1". In the present invention, since the 8085A is used as the CPtJ as in the conventional example shown in FIG. Memory chip 1" selects the I10 chip, but when using an 8086 as the CPU, the selection signal is "0" selects the I10 chip and "1" selects the memory chip, contrary to the case of 8085A. Become. There are some differences in these logics depending on the CPU chip, but the idea is the same for all.

As described in detail, the address allocation circuit according to the present invention allows memory addresses to be freely allocated by simply changing the program of the programmable decoder without changing the wiring, and it is possible to use memories with different memory capacities. Since it can be shared, it can be used as a general-purpose board assembly. Also, the memory capacity is 2 bytes → 4 with the same chip shape.
Due to technological advances, larger capacity memories are being commercialized, such as 1 byte, 8 bytes → 16 bytes → 32 bytes, but according to the present invention, it is possible to easily support new memories at low cost. It is.

It goes without saying that the address allocation circuit according to the present invention can be applied to various applications as a programmable address allocation circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an address circuit, FIG. 2 is a diagram showing a memory map of memory elements U1 to U16 in FIG. 1, and FIG. 3 is a diagram showing data on the address bus when address 1000 is specified. Figure 4 is the first
5 is a block diagram of an embodiment of the present invention, FIG. 6 is a circuit diagram embodying FIG. 5, and FIG. 7 is another embodiment of the present invention. FIG. 2 is a block diagram illustrating an example. Explanation of symbols of main parts

Claims (1)

[Claims] a first address decoder whose address input terminal is supplied with a decoded address signal from the central processing unit; a part of the address input terminal is supplied with the decoded address signal from the central processing unit; and the remaining part of the address input terminal is supplied with the decoded address signal from the central processing unit; is connected to a part of the decode output terminals of the first address decoder and selects any one of the plurality of memory elements or the plurality of input/output elements connected to each of the plurality of decode output terminals. An address input terminal is connected to a second address decoder and the remaining decode output terminals of the first address decoder, and each of the plurality of decode output terminals is connected to the remaining address input terminals of the plurality of second address decoders. the first and second address decoders are programmable decoders, and the chip selection input terminal of the second address decoder is connected to the plurality of memory elements or the plurality of inputs. An address allocation circuit characterized in that a selection signal for selecting an output element is supplied.