JPS61233489A - Address assigning circuit - Google Patents

Abstract

PURPOSE:To assign freely a memory address and to use in common memories with different memory capacities by using a programmable decoder for an address decoder. CONSTITUTION:Since memory decode addresses A11, A12 are address inputs of programmable decoders 111-1116 and memory decode addresses A13-A21 are address inputs to a programmable decoder 10, a decode output up to 4M bytes is obtained by a 2k byte blocks. Further, decode output lines L1-L3 of the programmable decoder 10 are used as address data buses and L4-L7 are used as chip selection lines via the 3rd address decoder 12, then the head address of each memory chip is changed freely or the memory chip is replaced easily with a memory chip having different memory capacity when the same pin arrangement is adopted by only changing the program of the decoder 10 without changing wiring.

Description

Detailed Description of the Invention [111] The present invention relates to an address allocation circuit, and in particular to an address allocation circuit for allocating addresses to select any one of a plurality of memory elements or a plurality of input/output elements. Regarding.

LLIL FIG. 1 shows an example of an addressing circuit for addressing a memory including, for example, a plurality of memory elements. In the figure, one element (hereinafter referred to as a chip) out of a plurality of memory elements U1 to L116 is selected (for example, two address decoders 1.
2 is provided. The storage contents of these address decoders 1 and 2 are fixed. central processing unit (hereinafter referred to as cP)
An 8-bit data bus such as 8085A (manufactured by Intel Corporation) is used as U)3.

In this CPU 3, data and addresses are transmitted in a time-division manner, so the lower byte of the address (Ao=A7
) is provided with an address latch circuit 4 for latching the address.

Among the plurality of memory elements U1 to U16, U1 to U8 are 2
It is a byte ROM (read only memory) and U9
~L116 is a 2 byte RAM (random access memory). Since these memories are 2 bytes, address bits AO to Ale are address decoder 1.
, 2, and is directly supplied to the address input terminal of the memory. The address bits A n to A + s are each used by the address decoder 1 to select a 2-byte memory chip.
．． 2 and decoded. The 10/M signal output from the CPU 3 is a selection signal for identifying whether to select a memory or an l10 (input/output) element (not shown), and is a low level signal when selecting a memory. Become. In this circuit example, the memory map of the memory elements U1 to U16 is configured as shown in FIG.

Next, the operation when the CPL 13 reads data stored, for example, at address 1000 in the memory will be described.

First, the CPU 3 sends address information 1000H to the memory via the address bus. At this time, data as shown in FIG. 3 is loaded onto the address bus. Address bit An-Al1 is supplied to address decoders 1 and 2, but since the AI4 bit is “0”, address decoder 1 is enabled and address decoder 2 is
Since the M-bit information is supplied via the inverter 5, the decoder 2 is disabled. Also, since the memory is selected, the low level 10/
Since the M signal is outputted, inverted by the inverter 6, and then supplied to the chip selection terminal G1 of each decoder 1, 2, each decoder 1.2 is enabled.

As a result, memory chip U3 is selected based on the function of address decoder 1.2 (see the function table in FIG. 4). Also,
Address bits Ao to A +o are all -10'', so
The starting address of memory chip U3 is designated. At this time C
When an RD (read) signal is output from the PU 3 and input to the memory, the stored contents are read from the specified address and taken into the CPU 3 as data information.

In the addressing circuit configured in this way, conventionally, an address decoder 1 provided for chip selection is used.
, 2 has been fixed, so if you want to change the address, for example, if you want to change the start address of memory chip U9 from ``4000H'' to ``8000H'', input the address decoder 1.2. Terminal G2
It was necessary to change the address bit supplied to A1 from Al1 to A+s, and accordingly, the wiring of the address line had to be changed.

Furthermore, when changing the memory capacity using chips with the same bin arrangement, wiring changes similarly occurred.

This can be done, for example, by changing the ROMs of U1 to U8 from 2 to 4 bytes.
When changing to byte ROM, address decoder 1
Address bits A12 to AI4 are input to the address input terminals of
This is because it is necessary to input

As is clear from the above, conventional address allocation circuits are specialized and lack versatility.

Shellfish! IU [The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a versatile address allocation circuit that can freely allocate memory addresses and easily change memory capacity. .

The address allocation circuit according to the present invention includes a first address decoder whose address input terminal is supplied with a decoded address signal from the central processing unit, and a part of the address input terminal which is supplied with the decoded address signal from the central processing unit. Any one of a plurality of memory elements or a plurality of input/output elements, in which the remainder of the address input terminals are connected to a part of the decode output terminals of the first address decoder, and each of the plurality of decode output terminals is connected to the plurality of memory elements or the plurality of input/output elements. a plurality of second address decoders that select a second address decoder, and an address input terminal is connected to the remaining decode output terminals of the first address decoder, and each of the plurality of decode output terminals selects a second address decoder of the plurality of second address decoders. a third address decoder connected to a chip selection input terminal, the first and second address decoders are programmable decoders, and the chip selection input terminal of the first address decoder is connected to the plurality of memory elements. Alternatively, a selection signal for selecting a plurality of input/output elements is supplied.

衷-JjL Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 5 is a block diagram showing one embodiment of the present invention, and FIG. 6 is a circuit diagram embodying the same. 5 and 6, decode address signals A I3 to A21 output from a CPU (not shown) are supplied to an address input terminal of a programmable decoder 10 as a first address decoder, and a decode address signal An , A+t are part Ao of each address input terminal of the plurality of programmable decoders 111 to 1116 as the second address decoder.

A1 is supplied. These programmable decoders 11
A plurality of memory elements or I10 elements (both not shown) are connected to each of the decode output terminals 1 to 1116, as in the conventional example shown in FIG. Programmable decoders 10 and 111 to 1116 are ROM or PAL
(Programmable Array Logic). PAL uses NAND and NOR, which are the simplest logic circuits, as basic gates, and these are arranged in an orderly manner on a chip.By electrically interconnecting the basic gates, a customer-specific random logic LSI can be constructed. It is.

The chip selection input terminal G of the programmable decoder 10 receives a selection signal (IO/M signal) output from the CPLJ.
is supplied. In this embodiment, a plurality of memory elements are connected to each decode output terminal of programmable decoders 111 to 1116, and the IO/M signal in this case becomes a memory selection signal. Programmable decoder 10
Some of the decode output lines 1 to L3 are programmable decoders 111 to 1116 as address data buses.
are commonly connected to the remaining address input terminals A2 to A4 of
The remaining decode output lines 14 to L7 are connected to address input terminals of a decoder 12 provided as a third address decoder. A plurality of decode output terminals of this decoder 12 are connected to programmable decoders 111 to 111.
6 chip selection input terminals G, respectively.

In this embodiment, the memory decode address is A u to A2
+, but this means that for the 8085A CPU, the address bits are Ao~A+5 (64 bytes of memory space), for the 8086, the address bits are Ao''-A+s (1MB of memory space), and for the 80286, the address bits are Ao~A23 (16MB of memory space). This is because the memory space of

In the address allocation circuit with such a configuration, the memory decode address All1Al2 is the address input of the programmable decoders 111 to 1116, and the memory decode address A I3 to A21 is the address input of the programmable decoder 10. You can get decoded output up to bytes. In addition, decode output lines L1 to L3 of the programmable decoder 10 are used as address data buses, and
Since L7 is used as a chip selection line via the third address decoder 12, by simply changing the program of the programmable decoder 10 without changing the wiring, you can freely change the start address of each memory chip or arrange the same bin. If so, you can easily replace the memory chip with a different memory capacity. Furthermore, by using the third address decoder 12, the chip selection bits of the programmable decoder 10 can be used effectively.

Furthermore, since some of the address input terminals of the programmable decoders 111 to 11 6 are used as input terminals for memory decode addresses from the CPU, the memory capacity of the programmable decoders 111 to 1116 can be used effectively, and the overall This allows the memory area to be expanded. In addition, each memory chip has a memory capacity of 2 bytes Ao~A 10 4 bytes Ao~A n 8 bytes Ao~A +2 16 bytes Ao~A13 32 bytes It is natural to connect the address lines so that the address bits of the case Ao -Al1 are supplied.

Furthermore, in the programmable decoders 11+ to 1116, it is of course possible to change the start address of each memory for each decoder, and to connect memory chips with different memory capacities (byte to 2, byte to 4, etc.). However, by changing the program of the programmable decoder 10, the start address of the memory can be changed for each memory chip in a single programmable decoder, or memory chips with different memory capacities (2 bytes, 4 bytes) can be changed. ...) can also be connected.

FIG. 7 is a block diagram showing another embodiment of the present invention. In this embodiment, a programmable decoder 10 is added, and these programmable decoders 101 to 10n
The configuration is such that a plurality of third address decoders 121 to 12n and programmable decoders (111 to 11 +s) to (1n1 to 1n+6) are connected to each of the above-mentioned embodiments. The memory area can be expanded and used. Further, by providing a further decoder before the programmable decoders 10+ to 10n in FIG. 7, the memory area can be further expanded. The storage contents of the decoder in this case may be either fixed or variable.

In each of the above embodiments, the case where a memory chip is mainly selected has been described, but the same applies to the case where an I10 chip is selected. However, the memory chip and I10
Regarding the discrimination between chips, the 10 output from the CPU
The determination is made based on whether the /M signal (selection signal) is "0" or "1". In the present invention, an 8085A is used as the CPU, as in the conventional example shown in FIG. When the selection signal is "0", the I10 chip is selected, and when it is "1", the memory chip is selected, which is the opposite of the case of the 8085A. These logics may differ somewhat depending on the CPU chip, but the idea is the same for all.

As explained above, according to the address allocation circuit according to the present invention, memory addresses can be freely allocated by simply changing the program of the programmable decoder without changing the wiring, and memories with different memory capacities can be allocated. Since it can be shared, it can be used as a general-purpose board assembly. In addition, with the same chip shape, memories with larger capacities are increasingly being commercialized, such as 2 bytes, 1 bytes, 4 bytes, 8 bytes, 16 bytes, and 32 bytes. For example, new memories can be easily accommodated at low cost.

It goes without saying that the address allocation circuit according to the present invention can be applied to various applications as a programmable address allocation circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an address circuit, FIG. 2 is a diagram showing a memory map of memory nodes U1 to U16 in FIG. 1, and FIG. 3 shows data on the address bus when address 1000 is specified. Figure 4 is the first
5 is a block diagram showing an embodiment of the present invention, FIG. 6 is a circuit diagram embodying FIG. 5, and FIGS. 7 to 9 are each in accordance with the present invention. It is a block diagram showing other examples of. Explanation of symbols of main parts

Claims (1)

[Claims] a first address decoder whose address input terminal is supplied with a decoded address signal from the central processing unit; a part of the address input terminal is supplied with the decoded address signal from the central processing unit; a plurality of second address decoders connected to some of the decode output terminals of the first address decoder and selecting any one of the plurality of memory elements or the plurality of input/output elements connected to each of the plurality of decode output terminals; an address input terminal is connected to an address decoder and the remaining decode output terminals of the first address decoder, and each of the plurality of decode output terminals is connected to a chip selection input terminal of the plurality of second address decoders. a third address decoder, the first and second address decoders are programmable decoders, and the chip selection input terminal of the first address decoder selects the plurality of memory elements or the plurality of input/output elements. An address allocation circuit characterized in that a selection signal for the address allocation circuit is supplied.