KR890003234Y1 - Memory bank selecting modulation circuit - Google Patents

Abstract

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Description

Memory bank selection conversion circuit according to the type of dynamic ram

1 is a circuit diagram according to the present invention.

2 is a memory table programmed in the program ROM of FIG.

3 (a) and (b) are diagrams of a memory map according to the memory table of FIG.

* Explanation of symbols for main parts of the drawings

100: decoder circuit 200: latch circuit

300: pyrom (P-ROM)

The present invention relates to a dynamic rank bank selection circuit of a computer, and more particularly, to a memory bank selection conversion circuit according to a type of a dynamic RAM.

In a system composed of a central processing unit using 8 bits of data, eight 64K DRAMs have been used to configure a dynamic RAM area of about 64 kilobytes (1 bank).

In addition, for memory expansion of dynamic RAM, the memory bank has been expanded by using 8 units of 64K DRAM memory, which increases the area of component occupancy on the board due to the increase of components. It was used as a replacement.

However, when the type of the dynamic RAM used in the existing system is changed as described above, there is a problem that the memory bank selection circuit must be changed together.

Accordingly, an object of the present invention is to provide a memory bank selection change circuit that outputs a corresponding memory bank selection signal even if the dynamic ram type is replaced to expand the memory.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram according to the present invention, a decoder circuit 100 for inputting and decoding an input / output address signal of a central processing unit input to the address bus 10 and outputting a predetermined state logic signal, and The predetermined state logic signal output from the decoder circuit 100 and the predetermined data output from the central processing unit and input to the terminal 20 are inputted to the clock terminal CLK and the input terminal D, respectively. A latch circuit 200 for latching and outputting a predetermined logic device in accordance with a clock signal. Address of the allocated address signal inputted by inputting the address allocation signal An… An + 3 of the central processing unit inputted to the address bus 10 and the predetermined logic signal outputted from the latch circuit 200 as a selector signal. And a designated name (P-ROM, hereinafter referred to as P-ROM) for outputting specified data by a selector signal.

(At this time, PROM can be used as Programable Array Logic (PAL))

On the other hand, in FIG. 2, when a port of a memory bank is a bank (A) or a bank (B), it is assumed that 64K bytes (64K bits x 8) or 256K bytes (256K bits x 8) of memory are connected to each bank. Memory table programmed in P-OM of 1 degree. 3A and 3B are diagrams of memory maps in which memory banks A and B are accessed by the program of FIG.

Hereinafter, the operation of FIG. 1 according to the present invention will be described in detail with reference to the memory table of FIG. 2 and the memory maps of FIGS. 3A and 3B.

Now, when the input / output address signal of the central processing unit is input to the decoder circuit 100 via the address bus 10, the input address signal is decoded and the output terminal Y is " low " or " high " The state logic signal is output to the clock terminal CLK of the latch circuit 200.

In addition, the latch circuit 200 which inputs a predetermined relative signal as a clock signal has a logic " high " Alternatively, the signal of "low" is input to the selector terminal SEL of the PROM 300.

On the other hand, when the central processing unit input / output address signal An ... An + 3 is input as the address signal of the pyrom 300 through the data bus 10, the input signal is inputted by the selector signal output from the latch circuit 200. Output the specified data of the address signal.

That is, when the memory data as shown in FIG. 2 is programmed in the name or Programmable Array Logic 300, the signal of the input / output allocation address (An ... An + 3) of the central processing unit is "". If the selector (SEL) signal input to 0 "and output from the latch circuit 200 is" low "(" 0 "), the output terminal QA of the pyrom 300 may be" a "as shown in FIG. When the high "state signal is output and the memory bank A of 64K Byte is selected and accessed, the selector signal from the latch circuit 200 outputs to" King "when the memory bank A is 64K byte as shown in FIG. The memory banks (A) and (B) are continuously extruded to access a total of 128 K bytes of memory continuously.

On the other hand, when the output of the latch circuit 200 is output to the "high" state with the memory banks A and B configured as, the input / output allocation address signal An ... An + 3 output from the central processing unit is " When 0 "is input, the output terminal QA outputs a" high "status signal as shown in (b-1) of FIG. 2 to select and access the memory bank A of 64K bytes.

In addition, when the selector signal is input in the logic " high " state, the memory bank A is similarly selected when the signal of the address signal (An ... An + 3) input to the address bus 10 is input in the 0001-0011 state. This results in overlapping four banks, but it is easy to see that the memory mounted by the read / write rest of the memory is only one bank as in the third wing (a).

Therefore, when the selector signal is input in the "high" state, the selection of the memory bank B of 64K bytes is equivalent to that in FIG. 2 (d-2) when the address signal (An ... An + 3) is input to "100". In the same manner, the memory bank B is selected and accessed.

At this time, when the signal of the address An ... An + 3 is input in the upper address (0101-0111) state, the output terminal QB of the name 300 is "high" as shown in FIG. The memory bank B is selected to access the memory bank B and the four banks overlap, but only one bank is mounted by the read / write test of the memory.

On the other hand, if the memory banks (A) and (B) each having 64K bytes of memory are exchanged into the banks (A) and (B) each having 256K bytes of memory capacity for dynamic RAM expansion, the operation of the memory bank selection conversion circuit You can select it as follows.

The decoder 100 inputs an input / output address (An ... An + 3) of the central processing unit output from the address bus 10, decodes it into a predetermined state logic signal, and then clocks the signal to the latch circuit 200. Will output

In addition, when the latch circuit 200 inputs one data bit of the central processing unit input to the terminal 20 as a data input terminal, a predetermined state signal is generated by a signal output from the decoder 100, that is, a clock signal. Outputs

At this time, if the predetermined state signal output from the latch circuit 200 is "low" and the input / output allocation address signal An ... An + 3 of the central processing unit is "0", as shown in FIG. A high " state is output to access memory bank A for selection.

However, since the memory capacity of memory bank A is 256K bytes, only the 4K byte memory area is accessed. (When the address of memory of 256K byte is 0-3FFFF H, only access to 0-FFFF H address)

Therefore, the selection of the memory bank B is outputted as "high" as shown in FIG. 2C when the address signal An ... An + 3 is "1" as stated above, and thus 1/1 of the capacity of 256K bytes. The memory corresponding to 4 is accessed.

On the other hand, the "high" state logic signal is output from the latch circuit 200 and is input to the selector terminal of the PROM 300, and the address signal output from the address bus 10 is "0"-"11". As shown in the second table memory table b, which is input to the address terminal of the pyrom 300 as a signal, a "high" state is output from the output terminal QA of the pyrom 300.

In other words, when the address signal (An ... An + 3) assigned from the input / output port of the central processing unit is "0" to "11", as shown in Fig. 2 (b), high-state logic outputs a memory bank of 256K bytes. Select (A) to access the "100" to "111", as shown in Fig. 2 (d), the high-state logic outputs the memory bank (B) of 256K Byte can be selected to access the memory map (MAP) ) Is shown in FIG. 3 (b).

Therefore, memory banks (A) and (B) each consisting of 256K bytes are successively accessed, thereby continuously accessing 512K bytes of memory.

In general, computer systems use consecutive memory weaknesses. When selecting banks (A) and (B) each consisting of 64K bytes, the selector signal of the Pyrom 300 is " low " for a total of 128K bytes as continuous memory. If the selector signal of the Pyrom 300 is " high " when each bank A or B composed of 256K DRAM is selected, the memory area of 512K bytes in total is used continuously.

Meanwhile, in the arc diagram of FIG. 1 according to the present invention, a portion shown by a dotted line is used to select a memory bank by using the decoder circuit 400 and the latch circuit 500 illustrated by a dotted line when the memory bank is expanded. As the selector input is extended, the decoder circuit 400 decodes the input / output address of the central processing unit input to the address bus 10 and outputs a predetermined state logic signal to the latch circuit 500.

At this time, the latch circuit 500 inputs the data bits of the central processing unit input to the terminal 30, and the state logic of "high" or "low" by the state logic output from the decoder circuit 400. The selector terminal SEL ₁ of the pyrom 300 is output.

Therefore, when the memory table is programmed in the pyrom 300 in the same manner as in FIG. 2, it is possible to select several memory banks.

As described above, the present invention may output the selection signal of the extended memory bank when the memory area is expanded in the computer system, and thus the memory bank selection signal may not be replaced even if the dynamic ram type is changed in the system. There is a cost savings effect due to the reduction of city man-hours.

Claims (1)

In the memory bank selection change circuit according to the dynamic ram type, a decoder circuit 100 for inputting and decoding an input / output address signal of a central processing unit and outputting a state logic signal, and a predetermined output from the central processing unit. And a latch circuit 200 for outputting a "low" or "high" state logic signal according to the state logic output from the decoder circuit 100 by inputting the data of Memory bank selection conversion circuit according to the dynamic RAM type, characterized in that it comprises a pyrom (300) for inputting an address signal and the state logic signal output from the latch circuit (200) to output a memory bank selection signal.