JPS61141054A - 情報処理装置 - Google Patents

情報処理装置

Info

Publication number
JPS61141054A
JPS61141054A JP59264230A JP26423084A JPS61141054A JP S61141054 A JPS61141054 A JP S61141054A JP 59264230 A JP59264230 A JP 59264230A JP 26423084 A JP26423084 A JP 26423084A JP S61141054 A JPS61141054 A JP S61141054A
Authority
JP
Japan
Prior art keywords
address
circuit
scalar
data processing
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59264230A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0211931B2 (enrdf_load_stackoverflow
Inventor
Hiroyuki Nishimura
西村 弘行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59264230A priority Critical patent/JPS61141054A/ja
Publication of JPS61141054A publication Critical patent/JPS61141054A/ja
Publication of JPH0211931B2 publication Critical patent/JPH0211931B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Complex Calculations (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP59264230A 1984-12-14 1984-12-14 情報処理装置 Granted JPS61141054A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59264230A JPS61141054A (ja) 1984-12-14 1984-12-14 情報処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59264230A JPS61141054A (ja) 1984-12-14 1984-12-14 情報処理装置

Publications (2)

Publication Number Publication Date
JPS61141054A true JPS61141054A (ja) 1986-06-28
JPH0211931B2 JPH0211931B2 (enrdf_load_stackoverflow) 1990-03-16

Family

ID=17400298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59264230A Granted JPS61141054A (ja) 1984-12-14 1984-12-14 情報処理装置

Country Status (1)

Country Link
JP (1) JPS61141054A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01228039A (ja) * 1988-02-10 1989-09-12 Internatl Business Mach Corp <Ibm> コンピユータ・システム
JPH02141845A (ja) * 1988-09-16 1990-05-31 Digital Equip Corp <Dec> マルチプロセッサシステムにおいて中央処理ユニットにより主メモリからデータブロックを読み取る方法
JPH02238534A (ja) * 1989-03-13 1990-09-20 Nippon I B M Kk マルチプロセツサ・システム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797168A (en) * 1980-12-06 1982-06-16 Fujitsu Ltd Buffer nullification control system
JPS57208685A (en) * 1981-06-18 1982-12-21 Nec Corp Information processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5797168A (en) * 1980-12-06 1982-06-16 Fujitsu Ltd Buffer nullification control system
JPS57208685A (en) * 1981-06-18 1982-12-21 Nec Corp Information processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01228039A (ja) * 1988-02-10 1989-09-12 Internatl Business Mach Corp <Ibm> コンピユータ・システム
JPH02141845A (ja) * 1988-09-16 1990-05-31 Digital Equip Corp <Dec> マルチプロセッサシステムにおいて中央処理ユニットにより主メモリからデータブロックを読み取る方法
JPH02238534A (ja) * 1989-03-13 1990-09-20 Nippon I B M Kk マルチプロセツサ・システム

Also Published As

Publication number Publication date
JPH0211931B2 (enrdf_load_stackoverflow) 1990-03-16

Similar Documents

Publication Publication Date Title
US3761881A (en) Translation storage scheme for virtual memory system
US5388247A (en) History buffer control to reduce unnecessary allocations in a memory stream buffer
US4493026A (en) Set associative sector cache
US4378591A (en) Memory management unit for developing multiple physical addresses in parallel for use in a cache memory
KR880000299B1 (ko) 캐쉬장치
US4424561A (en) Odd/even bank structure for a cache memory
US4445172A (en) Data steering logic for the output of a cache memory having an odd/even bank structure
JPS59180767A (ja) 直列化装置
US4392201A (en) Diagnostic subsystem for a cache memory
US4363095A (en) Hit/miss logic for a cache memory
US6463514B1 (en) Method to arbitrate for a cache block
US5339397A (en) Hardware primary directory lock
JP2768503B2 (ja) 仮想記憶アドレス空間アクセス制御方式
EP0531123A1 (en) A dynamic address translation processing apparatus in a data processing system
US5165028A (en) Cache memory having pseudo virtual addressing
US6704820B1 (en) Unified cache port consolidation
US6374334B1 (en) Data processing apparatus with a cache controlling device
JPS61141054A (ja) 情報処理装置
JP2008511882A (ja) 一意のタスク識別子を用いてデータを共用する仮想アドレス・キャッシュ及び方法
US5960456A (en) Method and apparatus for providing a readable and writable cache tag memory
EP0549219A1 (en) A cache controller
GB2037466A (en) Computer with cache memory
JPS5821352B2 (ja) バツフア・メモリ制御方式
JPH0336648A (ja) 電子計算機及びtlb装置とマイクロプロセッサチップ
JPS61237145A (ja) ストアバツフアの制御方式

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees