JPS61139140A - フレ−ム同期回路 - Google Patents

フレ−ム同期回路

Info

Publication number
JPS61139140A
JPS61139140A JP59260567A JP26056784A JPS61139140A JP S61139140 A JPS61139140 A JP S61139140A JP 59260567 A JP59260567 A JP 59260567A JP 26056784 A JP26056784 A JP 26056784A JP S61139140 A JPS61139140 A JP S61139140A
Authority
JP
Japan
Prior art keywords
output
input
bit
frame synchronization
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59260567A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0535618B2 (enExample
Inventor
Hidehiko Suzuki
秀彦 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59260567A priority Critical patent/JPS61139140A/ja
Publication of JPS61139140A publication Critical patent/JPS61139140A/ja
Publication of JPH0535618B2 publication Critical patent/JPH0535618B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59260567A 1984-12-10 1984-12-10 フレ−ム同期回路 Granted JPS61139140A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59260567A JPS61139140A (ja) 1984-12-10 1984-12-10 フレ−ム同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59260567A JPS61139140A (ja) 1984-12-10 1984-12-10 フレ−ム同期回路

Publications (2)

Publication Number Publication Date
JPS61139140A true JPS61139140A (ja) 1986-06-26
JPH0535618B2 JPH0535618B2 (enExample) 1993-05-27

Family

ID=17349741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59260567A Granted JPS61139140A (ja) 1984-12-10 1984-12-10 フレ−ム同期回路

Country Status (1)

Country Link
JP (1) JPS61139140A (enExample)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553265A (en) * 1978-06-22 1980-01-11 Nec Corp Reception timing device for digital code

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553265A (en) * 1978-06-22 1980-01-11 Nec Corp Reception timing device for digital code

Also Published As

Publication number Publication date
JPH0535618B2 (enExample) 1993-05-27

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