JPS61138033U - - Google Patents
Info
- Publication number
- JPS61138033U JPS61138033U JP2098985U JP2098985U JPS61138033U JP S61138033 U JPS61138033 U JP S61138033U JP 2098985 U JP2098985 U JP 2098985U JP 2098985 U JP2098985 U JP 2098985U JP S61138033 U JPS61138033 U JP S61138033U
- Authority
- JP
- Japan
- Prior art keywords
- key
- output
- terminals
- signals
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Input From Keyboards Or The Like (AREA)
Description
第１図及び第３図は夫々本考案になるキー・マ
トリツクス回路の第１及び第２実施例を示す回路
図、第２図及び第４図は夫々第１及び第３図示回
路の動作説明用波形図及び第６図は夫々従来のキ
ー・マトリツクス回路の一例を示す回路図及び動
作説明用波形図である。
１…制御装置、２，３，５，９…ダイオード、
４…ＮＯＲ回路、６，８…抵抗、７…トランジス
タ、Ｓ１１〜Ｓ１４，Ｓ２１〜Ｓ２４，Ｓ３１〜
Ｓ３４…スイツチ。
1 and 3 are circuit diagrams showing the first and second embodiments of the key matrix circuit according to the present invention, respectively, and FIGS. 2 and 4 are for explaining the operation of the first and third illustrated circuits, respectively. The waveform diagram and FIG. 6 are a circuit diagram showing an example of a conventional key matrix circuit and a waveform diagram for explaining the operation, respectively. 1...Control device, 2, 3, 5, 9...Diode,
4...NOR circuit, 6, 8...Resistor, 7...Transistor, S11 - S14 , S21 - S24 , S31-
S34 ...Switch.
Claims (1)
入力端子に接続されたｍ本の入力線と該制御装置
のｎ個（但し、ｎは１以上の整数）の出力端子に
接続されたｎ本の出力線との間にマトリツクス状
に配列接続された複数個のキースイツチに対して
、該ｎ個の出力端子より該ｎ本の出力線へ順次時
分割的に２値のキースキヤン用信号を出力し、該
複数個のキースイツチのうちオン又はオフ状態に
あるキースイツチを該ｍ個の入力端子への信号の
入来の有無によつて検出するキー・マトリツクス
回路において、該制御装置を該ｎ個の出力端子よ
りの該ｎ個のキースキヤン用信号による論理レベ
ルの組合わせが少なくとも（ｎ＋１）通りあるよ
うに該キースキヤン用信号を順次時分割的に出力
するよう構成すると共に、該ｎ個のキースキヤン
用信号が夫々供給され、該ｎ本の出力線に夫々同
一論理レベルのキースキヤン用信号が供給される
期間に、これらの信号をＮＯＲ（否定論理和）処
理して作り出したキースキヤン用信号を新たに付
加した１本の出力線に出力する論理回路を設けて
なり、該新たに付加した１本の出力線と前記ｍ本
の入力線との交叉点に接続された最大ｍ×（ｎ＋
１）個のスイツチのオン又はオフ状態を検出する
よう構成したキー・マトリツクス回路。 m input lines connected to m input terminals (where m is an integer of 2 or more) of the control device and n output terminals (where n is an integer of 1 or more) of the control device. For a plurality of key switches arranged and connected in a matrix between the output terminals and the n output lines, a binary key scanning signal is sequentially transmitted from the n output terminals to the n output lines in a time-sharing manner. In a key matrix circuit that outputs a key switch that is in an on or off state among the plurality of key switches based on the presence or absence of a signal to the m input terminals, the control device is connected to the n The key scanning signal is sequentially output in a time-division manner so that there are at least (n+1) combinations of logic levels of the n key scanning signals from the n output terminals, and the n key scanning signals are During the period when key scan signals of the same logic level are supplied to the n output lines, a new key scan signal is generated by performing NOR (NOR) processing on these signals. A logic circuit that outputs an output is provided to one added output line, and a maximum of m×(n+
1) A key matrix circuit configured to detect the on or off state of individual switches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2098985U JPS61138033U (en) | 1985-02-16 | 1985-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2098985U JPS61138033U (en) | 1985-02-16 | 1985-02-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61138033U true JPS61138033U (en) | 1986-08-27 |
Family
ID=30511984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2098985U Pending JPS61138033U (en) | 1985-02-16 | 1985-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61138033U (en) |
-
1985
- 1985-02-16 JP JP2098985U patent/JPS61138033U/ja active Pending
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