JPS61196333U

JPS61196333U -

Info

Publication number: JPS61196333U
Application number: JP8027785U
Authority: JP
Priority date: 1985-05-29
Filing date: 1985-05-29
Publication date: 1986-12-08

Description

[Brief explanation of the drawing]

第１図及び第２図は夫々本考案になるキー・マ
トリツクス回路の第１及び第２実施例を示す回路
図、第３図は第１図及び第２図図示回路の動作説
明用信号波形図、第４図及第５図は夫々従来のキ
ー・マトリツクス回路の一例を示す回路図及び動
作説明用信号波形図である。１，２……制御装置、ｉ_１〜ｉ_３……入力端子
、ｏ_１〜ｏ_３……出力端子、ｉｌ_１〜ｉｌ_９……
入力線、ｏｌ_１〜ｏｌ_４……出力線、Ｄ_１〜Ｄ_６……ダイオード、Ｓ_１１〜Ｓ_１３，Ｓ_２１〜Ｓ_２
３，Ｓ_３１〜Ｓ_３３，Ｓ_４１〜Ｓ_４６……スイツ
チ。 1 and 2 are circuit diagrams showing the first and second embodiments of the key matrix circuit according to the present invention, respectively, and FIG. 3 is a signal waveform diagram for explaining the operation of the circuit shown in FIGS. 1 and 2. , 4 and 5 are a circuit diagram showing an example of a conventional key matrix circuit and a signal waveform diagram for explaining the operation, respectively. 1, 2...Control device, _i1 - _i3 ...Input terminal, _o1 - _o3 ...Output terminal, _il1 - _il9 ...
Input lines, ol ₁ to ol ₄ ... Output lines, D ₁ to _{D 6} ...Diode, S ₁₁ to S ₁₃ , S ₂₁ to _{S 2
3} , _S31 to _S33 , _S41 to _S46 ...Switch.

Claims

[Claims for Utility Model Registration] (1) m first input lines connected to m (where m is an integer of 2 or more) input terminals of a control device and n (where m is an integer of 2 or more) input terminals of the control device; , n is an integer greater than or equal to 1), and n first output lines connected to the output terminals (n is an integer greater than or equal to 1) are connected to a plurality of key switches arranged in a matrix. Binary key scanning signals are sequentially time-divisionally outputted to the n first output lines, and the key switches in the on or off state among the plurality of key switches are
In a key matrix circuit that detects the presence or absence of signals to input terminals, the control device is controlled by at least a combination of logic levels by the n key scanning signals from the n output terminals. Means configured to sequentially output the key scanning signal in a time-divisional manner so that there are (n+1) signals, and constantly supplying the key scanning signal at the first logic level to a newly added second output line. and switch extension means connecting at least m switches to the intersections of the second output line and the m second input lines connected to the at least m input terminals. , a key configured to detect the on or off state of a switch added by the switch addition means during a period in which key scanning signals of a second logic level are simultaneously supplied to the n first output lines respectively.・Matrix circuit. (2) The switch extension means includes a maximum of 2 m diodes each having one end connected to the m second input lines, and a pair of diodes connected to adjacent input lines among the diodes. Consists of a maximum of m third input lines commonly connected to the other end, and a maximum of 2m switches connected to the intersection of the second output line and the second and third input lines. A key matrix circuit according to claim 1 of the utility model registration claim.