JPS61137369A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a preferable double diffused structure by forming a gate electrode of a MOS transistor, then forming a film which contains an impurity of high diffusion coefficient on a drain forming region, heat treating it to diffuse the impurity, then implanting the impurity ions of low diffused coefficient into the surface, and then activating it, thereby eliminating a shadowing of the implanting angle. CONSTITUTION:A thick field insulating film 2 is formed on the periphery of a P type Si substrate 1, a polycrystalline Si gate electrode 4 is formed through a thin gate insulating film 3 at the center on the surface of the substrate 1 surrounded by the film 2, and the entire surface is coated by an SiO2 film 6 which contains P. Then, a heat treatment is executed to diffuse P in the film 6, N<-> type source and drain regions 7 are formed at both sides of the electrode 4, the film 6 is removed, a thin SiO2 film 8 is coated between the films 2, As ions are implanted obliquely at approx. 7 deg. through the film 8 to form an ion implanted layer 9 into the surface layer of the region 7. Then, a heat treatment is executed to activate the layer 9 to obtain a double diffused structure having the activated layer 10 on the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an MO5 type semiconductor device with a double drain structure.

[Background technology]

In order to suppress the generation of hot carriers (mainly hot electrons) in MO8 type semiconductor devices and improve the voltage resistance and reliability of the device, the source/drain regions of MOS transistors, especially the drain regions to which the socket voltage is applied, are 2
It is known to create a heavy diffusion structure. For example, as described in "Nikkei Electronics (Special Issue Micro Devices) J, January 23, 1980 issue, p. 83," published by Nikkei McGraw-Hill, the source and drain regions of an N-type MoS transistor are covered with a low concentration P (phosphorous) expanded W1 layer. and high concentration of As
It has a double structure with the (arsenic) diffusion layer, and the electric field relaxation effect of this P diffusion layer suppresses the generation of hot electrons.

By the way, when manufacturing the above-mentioned double diffusion structure, P and As are ion-implanted by the self-line method using a gate electrode formed of polysilicon, and then diffused (activated) by heat treatment to form P and As. A method has been adopted in which a double structure is formed based on the difference in diffusion rate. However, the P.

In A5 ion implantation, the ion implantation is normally performed at an angle of about 7 degrees from the direction perpendicular to the substrate surface in order to enhance the ion implantation effect on the surface of the silicon substrate.
An effective double expanded WI structure may not be formed.

That is, as shown in FIG.
As shown in the figure, when A5 ions 21a are implanted from 7'' to the left, while P ions 21b are implanted from 7° to the right, P ions are implanted at the left end of the gate electrode 20. A diffusion layer 22.2 of IAs, P which takes shape in 21b and thus diffuses them.
Even if 3 is formed, an effective double diffusion structure cannot be obtained. Particularly in recent years, as semiconductor devices have become more highly integrated, elements have become smaller and the gate length relative to the gate electrode thickness has become smaller, increasing the incidence of such defects. ing.

A countermeasure against this problem is to always keep the substrate installation direction constant with respect to the ion implantation direction, but this may complicate the work, such as requiring highly accurate positioning using the orientation flat of the substrate (wafer). A decrease in processing efficiency occurs.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device which can easily and efficiently form a normal double diffusion structure, and in particular can form impurities with a high diffusion coefficient without the influence of shadowing to obtain a good MOSQ structure. The purpose is to provide a manufacturing method.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.9 That is, a process of forming a film containing impurities with a high diffusion coefficient and thermally diffusing the impurities into a substrate , followed by a step of dosing and activating an impurity with a low diffusion coefficient by ion implantation, it is possible to form an impurity diffusion layer with a particularly high diffusion coefficient isotropically with respect to the gate electrode. can eliminate the effects of shadowing caused by
This makes it possible to manufacture a normal double diffusion structure.

〔Example〕

FIG. 1 (A, i) to (E) show the present invention as an N-channel ζM○
``An example applied to an S transistor is shown in the manufacturing process.

First, as shown in FIG. 2A, a field insulating film 2 and a gate insulating film 3 are formed on the main surface of a P-type silicon substrate 1, and then a polysilicon gate 1? is formed by a conventional method. ! pole 4
to form a pattern. At this time, the silicon surface of the regions 5.5 forming the source and drain on both sides of the gate @pA4 is exposed.

Next, as shown in FIG. 2B, a SiO2 film 6 containing P (phosphorus) is deposited over the entire surface. This SiO2 film 6 is formed by, for example, a sputtering method, and the film thickness is determined by P contained in SiO2.
Adjust as appropriate depending on the concentration. Then, the entire substrate 1 is subjected to heat treatment, whereby the P in the 5102 film 6 is thermally diffused to the main surface of the substrate 1, and due to the concentration of P and its high diffusivity, it becomes N type (N-) with low purulence. Diffusion layers 7, 7 are formed isotropically in regions 5, 5.

Next, after removing the SiO2 film 7 by etching, the surface of the substrate 1 is thoroughly oxidized to form a thin SiO2 film as shown in FIG.
A film 8 is formed, and then As ions are implanted over the entire surface, and the self-alignment method using the gate electrode 4 is used to form a film 8. Ion implantation layer 9, 9 on A5゜5
is formed. The SiO2 film 8 is for protecting the main surface of the substrate 1 from damage caused by ion implantation. Also,
The ion implantation has an inclination of about 7'' with respect to the vertical direction of the substrate 1.

In this state, there is some shadowing g (dispersion between the left and right ion implantation layers) in the ion implantation layers 9, 9.

Then, if the substrate 1 is heat-treated to activate the ion implantation layer 99, a high concentration of N is created in the region 5.5 as shown in FIG.
Type (No) diffusion MIto,to is formed. At this time, due to the difference in diffusion speed between P and ΔS, As diffuses! 1
0.10 does not protrude outside of the P diffusion layer 7.7, and as shown in the figure, there are two layers: an outer low concentration diffusion layer (7, 7) and an inner high concentration diffusion layer (10, 10). A diffusion structure is formed. Moreover, by this activation process, the ion implantation layer 9,
Variations between 9 are corrected.

Then, as shown in the same figure (E), if a layer such as PSG and an A film 11 are formed by a conventional method, and an A1 wiring 13.13 is formed after forming a contact hole 12, the N of the so-called double drain structure is formed. A type MOS transistor will be completed.

Therefore, according to the above manufacturing method, P with a high diffusion coefficient
Since the diffusion layers 7 and 7 are formed by the thermal diffusion method (solid diffusion method), there is no shadowing effect due to the ion implantation angle, and the diffusion layers 7, 7 are isotropically diffused toward the inside of both ends of the gate electrode!@4. Therefore, even if the As diffusion layer 10.10 is formed by the ion implantation method and some shadowing effects exist (remain), the double expansion W14fJ structure It is possible to obtain source/drain regions that do not affect the characteristics in any way, and it is possible to obtain a MoS transistor with excellent characteristics against hot carriers.

Also, the P diffusion layers 7, 7 are formed isotropically to prevent As from spreading. i
1. By eliminating the influence of the ion implantation direction (angle) in layer 10.10, settings such as orientation flat alignment of the substrate (wafer) l in the ion implantation device can be made easier, and the ion implantation work can be simplified. .

〔effect〕

(1) When forming an impurity wave MMI with a high diffusion coefficient such as P, a film containing impurities is formed and this is heat-treated to be thermally diffused into the substrate. An isotropic diffusion layer can be formed without the influence of shadowing, and therefore a good double diffusion structure can be formed even if the impurity diffusion layer with a low diffusion coefficient is formed by ion implantation.

(2) When forming an impurity diffusion layer such as P, we use a thermal diffusion method from the film containing the impurity to the substrate, so depending on the concentration of the impurity contained in the film, the thickness of the film, and the heating temperature,
The impurity concentration of the impurity diffusion layer can be easily controlled.

(3) Since the impurity diffusion layer with a high diffusion coefficient is formed isotropically, it is possible to eliminate the influence of the ion implantation angle during ion implantation of the impurity diffusion layer with a low diffusion coefficient. The position and direction of the machine can be easily set, and work efficiency can be improved.

Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.

For example, the film containing impurities such as P is the SiO
2, that is, SOG may be used instead of PSG. S
If OG is used, it is easy to form a thin film, so it is easy to control the temperature of 21 M degrees, and the film can also be left as it is after thermal diffusion and used as a damage prevention film during ion implantation.

[Application field]

In the above explanation, the invention made by the present inventor is applied to an N-channel MOS transistor, which is the background field of application, but the invention is not limited to this, and can be applied to CMO3 elements, etc. .

[Brief explanation of the drawing]

FIGS. 1A to 1E are cross-sectional views showing an embodiment of the method of the present invention in the order of manufacturing steps. FIG. 2 is a sectional view showing a problem with the conventional method. ■...Silicon substrate, 4...Gate, 6...SiO2 containing P, 7...Expanded Vi of P! ! layer, 9.
...As ion implantation layer. 10-As expanded Fl1MI, 11-PSG (interlayer insulating film), 13...A1 arrangement S. Figure 1 (A) Figure 1 (E) Figure 2

Claims (1)

[Claims] 1. After forming the gate electrode of the MOS transistor, forming a film containing an impurity with a high diffusion coefficient on at least the drain formation region of the substrate, and heat-treating the film to remove the impurity from the substrate. A semiconductor device comprising a step of diffusing into a main surface, and a step of ion-implanting an impurity with a low diffusion coefficient into the substrate and activating it, forming a double diffusion structure at least in the drain region. Production method. 2. When forming an N-type MOS transistor, P is contained in the film and thermally diffused into the silicon substrate to form a low concentration layer, and later As is ion-implanted and activated to form a high concentration layer. A method for manufacturing a semiconductor device according to claim 1. 3. A method for manufacturing a semiconductor device according to claim 1, in which a film is formed by incorporating an impurity with a high diffusion coefficient into SiO_2 or the like.