JPS61133982A - Pattern expansion/reduction circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Field of Use in Children's Business The present invention relates to a circuit for enlarging/reducing digitally stored character and graphic patterns to a free size. Enlargement/reduction is performed by determining pixel by pixel using software, or characters and figures are stored as coordinate information, and each coordinate value is multiplied by a coefficient to be used for enlargement or reduction.

Problems to be Solved by the Invention These conventional methods have the disadvantage that they are implemented by software or require complex circuitry, and are slow or expensive.

The present invention has been made in consideration of these points, and an object of the present invention is to provide a simple configuration and a high-speed, free size expansion/reduction.

Means for Solving the Problems The present invention provides an apparatus for digitally displaying or outputting characters, figures, etc., which includes means for making the clock frequency variable according to instructions from a control section, means for controlling the number of clocks, and the control section. a means for writing or reading according to an instruction from the shift register; a means for outputting information according to a predetermined rule based on output information from the shift register; and a shift register for reading this information. It is a circuit.

By using two types of clocks with variable operating frequencies, reading and writing at different speeds, and reading the results as parallel information, the ratio between the write clock and the read clock can be expanded or reduced. Do the following.

Embodiment FIG. 1 is a block diagram showing an embodiment of the enlarged finger and hand circuit of the present invention. In Figure 1, 1 is a reference clock generator, 2 and 3 are PLLs, 4 and 6 are variable frequency oscillators, 6 and 7
is a frequency divider, 8 is a clock controller, 9 is a pattern memory,
1o is a central controller, 11, 12, and 14 are shift registers, and 113 is a pattern converter. Further, in the figure, 21 indicates write information from the central controller, and 22 indicates read information to the central controller 10.

Figure 2 is a waveform diagram of each part to show the present invention in detail (-
) is the clock to the shift registers 1 and 2, Φ) is the output signal from the pattern converter 13, (c) is the clock to the shift register 3, (d) is the data written to the shift register by the clock (C), (e) shows the same data as (d) expanded to the same scale as (b).

FIG. 3 is a block diagram for explaining the present invention in detail,
This is a detailed view of the portions 11, 12, and 13 in FIG. (a) is a clock for driving the shift register, 11 and 12 are shift registers, 13 is a pattern converter, [Yes]) is an output signal, 21 is write data, and 23 is data read from the shift register. Figure 4 shows an example (b) in which the original pattern (a) is enlarged by 5/4 times using the present invention.

In FIG. 1, the reference clocks are PLL1 and PLL2.
The output of oscillator 1 or oscillator 2 is applied to splitter 1.
Alternatively, the phase is compared with the signal frequency-divided by the divider 2 to control the oscillator 1 and the oscillation frequency of the oscillator. For example, if the frequency divider 1 is set to 1/4 and the frequency divider 2 is set to 1A according to instructions from the central controller 20, 1 oscillator 2 will obtain a frequency 5/4 times that of oscillator 1. Next, the clock controller 8 is controlled by the central controller 10 and is opened only for a certain period of time (for example, a period during which the clock from the oscillator 1 passes through 16 cycles). At this time, when 16 clocks from the oscillator 1 pass, 16×5/4=20 clocks from the oscillator 2 pass. Before this, shift registers 1 and 2 must already have been written with information from the pattern memory. For example, information (f) for the first one horizontal period in FIG. 4 is written in the shift register 1, and information (q) for the second one horizontal period is written in the shift register 2.

Here, when the shift clock is input to the shift register, each piece of information is shifted, and the information is added to the pattern converter. The pattern converter performs the exchange according to a predetermined rule based on the added information of ) to obtain the output signal (b). This signal is written into the shift register 3 by the clock (C) from the oscillator 2.

During the same period, 20 clocks are added 5μ times, and the first 16 bits of information are expanded to 20 bits of information and stored in the shift register 3. This information is generated based on information having a difference of -1,000 periods between the shift registers 1 and 2, and it is possible to correct slanted portions, etc.

The information stored in the shift register 3 in this way is 6
The information is read out in parallel from the shift register 3 as information enlarged by /4 times. This can be easily done if the input clock to this shift register is stopped at 6/4 times 20 clocks. By repeating this operation, the image is enlarged 574 times in the horizontal direction, as shown in FIG. At this time, the ratio of the oscillation frequencies allows free expansion in the horizontal direction. Then this expanded information vertically.

By setting in shift registers 1 and 2 and doing the same thing, it is possible to perform vertical expansion.0 Effects of the Invention As described above, according to the present invention, with a simple circuit configuration, horizontal expansion can be performed. , vertical expansion can be performed at high speed, and since necessary information is created based on information of two horizontal periods or two vertical periods, smoothing correction can be performed. At the same time, the ratio can be freely expanded or reduced depending on the oscillation frequency ratio.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pattern enlarging/reducing circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of the circuit, and FIG.
The figure is a detailed view of the main part of FIG. 1, and FIG. 4 is an example of enlarged display of characters by the same circuit. 4.5...Variable frequency oscillator, 6,7...
...Frequency divider, 8...Clock controller, 9...
... pattern memory, 10 ... central controller,
11.12,14...Shift register, 13.
...Pattern converter. Name of agent: Patent attorney Toshio Nakao and one other person

Claims (1)

[Claims] In a device that digitally displays or outputs characters, figures, etc., means that can vary the clock frequency according to instructions from a control section, means that can control the number of clocks, and means that can write or read according to instructions from the control section; It has a means for outputting information according to a predetermined rule based on the output information from the shift register, and a shift register for reading this information, and a read clock and a write clock to these shift registers. A pattern enlarging/reducing circuit characterized by enlarging or reducing information such as characters or figures by changing the pattern.