JPS60159896A - Method and apparatus for generating analog voice signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a sound generating device, and more particularly to a sound generating device used in a computer system including a rask scan display device and a disk speed control device.

[Prior art]

There are countless well-known techniques for generating audio signals from digital signals. These techniques range from more straightforward techniques where a digital signal is used to provide the instantaneous amplitude of the audio signal to more complex vocoders where a transfer function is used to represent the audio signal.
It even includes technology.

As will be seen, although the present invention converts digital signals to analog (audio) signals, the conversion is only one aspect of the invention.

Computer Systems Small computer systems (eg, personal computers) often use scanned display devices. A computer generates video information and sounds and stores it in random access memory (RA).
M). A counter synchronized to the horizontal and vertical synchronization signals addresses the memory and obtains data from the memory that is synchronized to the display device. These signals are converted into audio signals, for example through shift registers. In some cases, the memory is "pitched" and the output from the memory is used directly to generate the audio signal. In other cases, the output from memory contains characters. The character is scanned to provide a video signal.

Generating a video display, especially in dynamic graphics (non-document) mode, requires a significant amount of data from the RAIV. In the field of personal computers, where microprocessors are used with dynamic RAM, or in the field of small business computers, generating a video display consumes a relatively large amount of processing unit time and memory time.

Therefore, it is difficult to obtain an audio signal, especially a complex audio signal, in the display mode.

〔overview〕

The present invention has a 4t microprocessor and seven RAMs in order to generate a back door signal simultaneously with the generation of a video signal.
Device? This is what we provide. The audio signal is generated without interfering with the video display or computer operation and, importantly, with minimal hardware and very short processing time.

In floppy disk drives, some type of mechanism is generally used to drive the motor at a constant speed. When a floppy disk drive is manufactured,
A calibration process is often performed to ensure that a floppy disk drive operates at a certain predetermined rotational speed. In addition to a calibration process, it requires a relatively expensive speed control mechanism. As will be seen later, in the present invention, a computer is used to detect the rotational speed of the floppy disk drive and provide control signals to adjust the rotational speed of the floppy disk drive. x, to do this! l11 Conventional calibration steps and speed control mechanisms are eliminated.

Floppy disk or other disk if uniform flux density transition is used? It has been suggested in the prior art that it can be better utilized. For that, 70
It is necessary to make the rotational speed of the Tubi disk a function of the radius of the foot track being accessed. The present invention also provides such features.

The present invention provides an apparatus including a microprocessor and 7 m of random access memory (RAM) for use in a computer system, particularly where a raster scanned display is used. In particular, during the horizontal erasure period, R
Addressing means are used to directly access all predetermined locations within the AM. By means of addressing,
The data stored in those same sWrs may also be updated during the horizontal erase period. The data stored in those locations is converted from digital format to analog signals. A pulse is initiated when data from memory is loaded into the counter. The pulse is initiated when the counter is loaded. The pulse is terminated at six o'clock when the color/return is overflowed, and the pulses thus obtained are integrated to form the entire audio signal.

The processor adds a predetermined number to the stored number and gives a data signal for a single note to the RAIV1. The topmost pit of the sum identifies the location in the lookup table, and the resulting (digital) signal is stored in RAM.

A predetermined number is repeatedly added to the stored number nine times to provide each data signal for the RAM. For more complex sounds, several predetermined numbers and stored numbers are used with multiple lookup tables.

The present invention also provides a device for fully controlling the rotational speed of the disk. Addressing means used with the sound generator are used as part of the disk controller.

[LOL example]

Hereinafter, the present invention will be described in detail with reference to the drawings.

In the following, an apparatus for generating audio signals, particularly signals for raster scanned display devices, and for generating motor speed control signals in connection with a computer system will be described.

DEFINITIONS In the following description, "speech or audio data signal"
Or in the term "acoustic data", analog (audio)
A digital signal that is converted into a signal.

used to indicate Furthermore, the term "motor speed control" refers to control of the rotational speed of a motor or a disk driven by the motor.

OVERALL ARCHITECTURE The present invention can be implemented as part of a complete computer system (personal computer or commercial computer) using a part number 68000 microprocessor 10. The address lines and data for this microprocessor 10 are lines are shown in FIG. 1. Other known lines coupled to this microprocessor are not shown in FIG. Access memory (RAM)
11 is coupled to microprocessor 10 . Data lines DO to D15 connect the microprocessor 10 and the RAM 11 to each other so that data can flow from the microprocessor 10 to the RAM 11.

Data from the RAM is coupled to the microprocessor 10 through a RAM data buffer 13.

The data i, gAhill are also coupled to the disk motor speed controller 27, the video shift register 28, and the audio counter 30. The acoustic counter 30 will be explained in detail by Shun with reference to FIG. Read-only memory (ROM) 17 is enabled (ROME
N/), microprocessor 10 also receives data from its ROM 17. Similarly, data is transferred to and from disk controller 18 when disk controller 1B is enabled by a signal provided on line 35. The i and RoMEN/ signals are generated within the PALS 23. Ru.

The address from the microprocessor 10 is stored in the ROM 17.
, PAL 823 , and RAM address multiplexer 20 . As shown, some of the address signals are sent to the disk controller 1B and to the serial communication controller 14.
It is also connected to the Inter7Ace adapter 15.

A RAM address multiplexer 20 allows RAM'ik addressing by the microprocessor 10 and directly by the count stored in the video counter 22. While the video signal is "displayed" on the screen, the multiplexer 20 outputs the video counter 22.
, so that the counter can directly address ROM 11'. (A signal from PALS 23 controls that selection.) At other times, RAM address multiplexer 20 indicates that microprocessor 10 is
11t - Allow direct access. A second 7-dress multiplexer 21, like multiplexer 20, is controlled by a signal from PALS 23.

As will be explained later with reference to FIG. 2, during the last portion of the horizontal erase signal, multiplexer 21 selects the top seven bits from counter 22 to bring the memory to that address. It includes sound quality data and disk speed data kRA.
M requires storage in a dedicated contiguous location so that this data can be easily accessed by the microprocessor when updated. A latch (not shown) provides an additional bit input to the address line of multiplexer 21 to provide direct access to the second page of audio data in RAM II.

A video counter 22 consisting of two 74LS393' counters provides a digital video count corresponding to the position of the beam on the raster-scanned display and a horizontal return (
(erase) period and additional bits for the vertical return (erase) period. A timing signal is generated by PALS 23 to operate the counter along with a reset signal.

PALS 23 is composed of three program array logic chips. These chips receive a crystal-controlled 16 MHz oscillation signal from an oscillator 31. From that signal, PALS 23 U, the well-known timing signals used by microprocessors and RAS/, CAS/ and other standard memory signals are output. The PALS23 outputs a horizontal synchronization signal (H8YNC/) and a vertical synchronization signal (VSYNC/).
/) is also given. Those signals are coupled to the display via line 32.

Other clock signals used throughout the memory are generated in PALS 23, such as the 8 MHz clock signal used by the counter shown in FIG. 3 and the clock signal used by the disk motor speed controller.

In the example described here, two 32KX
8 ROMs 17 are used. Those ROMs are
Storage for diagnostic functions, initialization functions and other functions not related to the present invention? conduct.

Disk controller 18 provides an interface to the floppy disk drive. Details of the disk controller are described in pending U.S. patent application Ser.

An interface adapter communicates with the key board 24. The mouse 25 receives cursor input and switching information t.
1 communication controller 14 and interface adapter 15. A volume control knob is drawn on the graphics screen and is controlled by the mouse to provide a full line of 3-bit binary data 3T. These three bits provide static volume adjustment of the audio signal, as will be explained later with reference to the 6th Ni.

Image timing In the example described here, the horizontal scan is 22.25
This is done at a rate of 6.84398 Hz. Each frame consists of 370 scan lines, with 704 scan lines per scan line.
There are 2 pixels and straddle dots. This is tD,
It corresponds to 44 16-bit words in RAM11a-etc. Therefore, oscillator 3 shown as 16MHz
Main clock speed from 1 to 15.6672M to be exact
Hz is ruru.

Refer now to FIG. The screen of the illustrated display has 512 "active" pixels horizontally and 342 scan lines. The remaining 192 bits during each horizontal scan are filled in during the horizontal erase period. This horizontal erase period is also referred to as a "flyback" period. During this horizontal erasing period, the beam current in the cathode ray tube changes to /
J - The beam is cut to one side of the screen 11111
be moved from one side to the other. In the vertical M71 direction, in addition to the 342 lines on the screen, there are 28 additional periods. During the addition period, the vertical erase period slows down.

During the vertical erase period, the beam current is reduced and the beam moves from the lower part of the screen to the upper part.

In FIG. 2, time is indicated from left to right, for example by dashed line 39. In the first scan, 512
After the bit has been displayed, the time represented by line 40 is reached and erasure occurs.

During the erase period, RAM 11 does not need to supply data for display. Before time 40, referring to FIG. 1, the count from counter 22 is routed through RAM address multiplexer 20 to access RAMI 1'. This is done for each line in the display. (Counter 22
retains both horizontal and vertical counts. )
During the horizontal erase period, the counter does not increment in the normal direction.

Rather, the four bits of the video counter are used again to count during the horizontal erase period. This eliminates address gaps for acoustic data. When time 40 is reached for each scan line, PALS23
A timing signal from the microprocessor 10
The multiplexer 20 receives the current address. During the next 192 counts of the 16 MHz clock (excluding the last count), the microprocessor is free to access the RAM 'fir' and thus perform non-display related tasks. When the last count in each scan line is reached, a signal from PALS23 causes the power to be
``111vi--directly accessed.At this time, R
The 16-bit word from AM11 (time 41 in FIG. 2) is read from memory, 8 bits of the 16-bit word are provided to disk motor speed controller 27, and the remaining 9 8 bits are provided to disk motor speed controller 27.
bit words are applied to the acoustic counter 29 (as will be explained later, only 6 bits are applied to the disk motor speed controller 29).
(Used from 7Vc). During the "screen time" shown in the second section, the 16-bit word from memory is placed in shift register 28 and the video signal! used to obtain As mentioned above, the PALS 23 provides the t-line 32 with a horizontal synchronization signal and a vertical synchronization signal, which are used together with the signals from the shift register 28 to fully control the video display.

The 342nd scan line: (labeled as scan line 43 in FIG. 2) is reached and along that scan line at time 40.
, the multiplexer 20 determines whether the microprocessor 10 accesses the RAM 11? Forgive again. However, at the end of scan line 43, during the remaining 90 periods of vertical erase, multiplexer 21 still causes 9 bits of the address to be inverted to RAIVll at time 41 and 16
Bit words for disk motor speed controller 27 and counter 2
9. (In order to obtain their address signals, lines RAO-RA6 are time multiplexed.) During the vertical erase period, microprocessor 10fl:
, RAM 11 can be accessed except for the last count of 6 scan lines. As will be explained later, it is during this period that the disk motor speed control data and audio data stored in RAM 11 are updated.

Multiflex 21 allows all acoustic data and all motor speed control data to be more easily accessed and updated by microprocessor 10 by locating its 9-bit address in the memory IJ. The acoustic data and speed control data are R
Note that the location where the AM11 is stored is different from the location where the screen data is stored.

With current technology, while the image is actually being displayed,
The microprocessor and the video display device use the data bus alternately and in a time-sharing manner to transfer signals. During the horizontal elimination period (
(for words 32-42), only the microprocessor has full access to the data bus. At time 41 (43rd word) shown in FIG. 2, the transfer of acoustic data/velocity data to the microprocessor is performed by full time division multiplexing on the data bus.

It is possible for the audio data, speed control data, and Y microprocessor to be updated while the video is being displayed. In reality, the data is updated during the erase period. Currently, and preferably, the vertical synchronization signal (return signal) initiates an update of the acoustic data.Using this signal, and by updating already accessed locations, (Starting from the location used at scan line 39, time 41, for example), the update operation does not interfere with the readout of the acoustic data.
Therefore, it is possible to ensure that the update operation is always performed prior to reading out the audio data. Assuming that the microprocessor updates all the acoustic data without being synchronized with the display,
Data can be exchanged before being used. Additionally, with this configuration, the software is burdened by the requirement to synchronize with audio in order to update data.

Acoustic Signal Generation The acoustic data bits representing the acoustic signal are shifted in parallel into two 4-bit cucunters 46, 47 (FIG. 3). A commercially available counter (part number 161) is available for these counters. The other counters are clocked by an 8 MHz clock signal provided over line 48. The counters continue counting until a ripple is detected on line 49. Therefore, if the counts of those counters are all set to 0, it takes a long time (approximately 32 μs) for the disturbance to occur, and when the counts of those counters are all set to 1, the disturbance occurs at 1 of 8 MHz.
It happens quickly in cycles.

19 acoustic waveforms are generated by first generating pulses with pulse widths as a function of time between the loading of the 8 bits into counters 46, 47 and the deflection. For example, as shown in FIG. 4, the leading edge 52 of the pulse occurs when acoustic data is loaded into the counter. When all zeros are loaded, a delay of about 32 μS occurs and the pulse ends, as indicated by the trailing edge 54 of the pulse. Since one 8-pit acoustic data word is loaded into the counter during each sweep, one pulse is generated during each horizontal sweep. Therefore, pulses are generated at a frequency of approximately 22,000 Hz, which theoretically corresponds to approximately 11,0
Gives a bandwidth of 00Hz. FIG. 4 shows a pulse 56 with a sufficiently narrow width. This pulse, of course, occurs when a larger number is placed in the counter 46,47.

The width of the pulse 57 occurring during the third sweep has the full width halfway between the first and second pulses.

To obtain an analog signal, the pulses are integrated using a conventional integrator. The integrator shown in FIG. 6 receives the load signal and the deflection signal. The waveform shown in FIG. 4 is generated within integrator 60. A waveform 61 represents the result of integrating the pulse shown in FIG.

Using three bits (bits 37a, 37b, 3'7c) of information from the interface adapter 15, the user can statically control the volume. Amplifier G3, 64.65, provides full amplitude control of the output on line 68.
is switched (on or off).

Calculation of the acoustic data signal The acoustic data from the memory defined by the acoustic data signal 2 is calculated by the microprocessor 10. Specifically, these acoustic data are generated in a microprocessor.

Using a high-level language such as PASCAL, a user can more easily construct all of the flowcharts described below.

Generally, the acoustic data generation process utilizes the full rapid addition capability of the 68,000 microprocessor, so the acoustic data is generated extremely quickly.

Reference is now made to FIG. 5 in its entirety. First, assume that one "pure" tone is generated. First, a lookup table is stored in memory. In the practical example described here, the lookup table is 256 x 8 bits. Therefore, an 8-bit output is produced for each 8-bit address in the lookup table. For pure tones, the lookup table contains points corresponding to sine waves.

This is shown in the search table 70 in FIG. The process of generating addresses for subsequent tables of values consists of repeatedly adding a predetermined number, shown in block 74 as Δφ0, to the number stored in register 72. At first,
The 32-bit word stored in register 72 can have any value, such as all zeros. To this is added an incremental value φO. The sum thereof is stored again in register 72. Next, the upper eight bits are extracted from the sum and used as the address for the lookup table TO, as shown in block T6.

For purposes of explanation, assume that Δφ0 is small. Each time this relatively small binary number is added to the number stored in register 72, their high order bits do not change - it takes many additions for those bits to change. Therefore, each of the 256 locations in lookup table 70 is addressed many times, and the 8 bits of data from lookup table stored in RAM 11 are gradually changed 111.
．． do. This of course corresponds to a low wave number. on the other hand,
If the increment Δφ0 is relatively large, the results from the lookup table will change more quickly, so that successive %8-bit data words from lookup table 70, stored in RAMI 1, for example, will be different. This corresponds to high frequencies. To block T4! Each addition represented by l1 yields a new 8-pit acoustic tape.

Therefore, by changing the increment of power output for each cycle, the frequency of the sound is changed. All acoustic data used during each frame can be easily calculated during several scan lines of the vertical cancellation period.

A set of tables can be used to provide envelope control or amplitude modulation. For example, the six tables through Serra 1-0-7 contain sine waves with maximum peak-to-peak values of 2 sets. Envelope control is performed by passing a predetermined number of frame periods before switching between each set.

Next, refer to Part 7. In the example described here, up to four 256.times.8 lookup tables can be used in microprocessor 10.

The contents of each search table can be programmed by the user and can be made different. For example, lookup table 80 in FIG. 7 is shown as containing a sine wave association;
Lookup table 81 is shown as containing a triangular waveform, lookup table 82 is shown as containing a square waveform, and lookup table 83 is shown as containing a ramp waveform. The process described with reference to FIG. 5 is used again. However, in this case (four types of sounds are generated simultaneously)
, 24 bits are used instead of 32 pits. (This is shown in block 85 of FIG. 7.) An increment, shown as Δφ1, is also added to the previously obtained sum (block 86). The high order bits are taken from the sum (block 87) and used as the address for the corresponding 8-bit word in lookup table 80. The same process is repeated for the numbers shown in block 87 and the cumulative (or same) increments Δφ
2 is added (block 88) and again the high order bits of the sum are used to address lookup table 81. Similarly, various stored values and increments are generated to enable searching in lookup tables 82.83.

The resulting 8 bits from the 6 tables are matched as shown in blocks 89, 90, and 91, and the top 8 bits are extracted from the sum (block 92) and stored in memory. 11. This process consists of 4
It is repeated for each sound data word stored in RAM 11 as the type of sound is generated. Once again,
The fundamental isofrequency of each of the four tones is determined by the increments that are added together, as in block 86.88. The overtone content is determined by the "waveform" stored in the search table.

Attached Table 1 is a program written in 68000 assembly language to implement the flowchart shown in FIG.

The sound generator described above allows excellent tone control, including: 1) "same wave number control" of up to 24 bits within the KHz band (for % tones); This results in
It can generate a total of almost 17 million different tones within a band that is roughly equal to (even better than) the human ear's best discrimination.

The process described above is particularly suitable for providing periodic functional associations whose properties vary with overtones, and which provides a sound quality that enhances melody and the like. For sounds such as voice, a j search buffer extended by 1 can be used to initially store waveforms representing speech, for example.

This is shown as buffer 93 in FIG. The buffer can actually be in URAMII, and when long waveforms have to be stored, it must be included in RAM 11 for practical reasons. Increment Δφo'ff
: By changing the 32-bit word stored in register 96, the 08-bit value is again obtained, and the high order bits of the sum are used to address the location in node 93.

The results of the searches in the expanded buffer are stored and selected during the horizontal erase period, as described with reference to FIGS. 5 and 7 in full.

The attached Table 2 contains a program written in 68000 assembly language to implement the flowchart shown in FIG.

Most typically, 70-inch disk drives and other disk drives operate at a predetermined constant rotational speed of the disk. ]l-Includes a machine drawing for driving.

When a disk drive is manufactured, the speed control mechanism is calibrated to record and retrieve data at rapid speeds.

For the present invention, the motor speed is controlled by a computer, and the motor speed is varied as a function of the track being accessed to provide a uniform magnetic flux density. That is, when the outer tracks (larger radius) are used, the motor rotates slower, and when the inner tracks (smaller radius) are used, the motor rotates faster.

In FIG. 9, the computer of FIG. 1 is shown as computer 97. Also shown is a disk drive, such as a floppy disk drive, and specifically a disk drive motor 98.

Line 99 shows the motor speed pulse total computer 9T
give to In the embodiment described herein, standard index pulses from the motor are used. Since the 70 disk drive used is keyed to the motor hub, no slippage occurs. Therefore, the index pulse itself represents the full actual rotational speed of the floppy disk. Given that slippage may occur, markers or bits from the floppy disk itself can be used to accurately indicate the speed of the floppy disk. A speed control signal provided via line 100 controls the motor speed. A predetermined signal level is used on line 100 and motor speed is detected on line 99. This allows the computer 97 to record the motor characteristics of the motor 98. That is, the computer knows the rotational speed of each motor connected to it for a particular speed control signal. In this manner, there is no need to calibrate the disk drive motor 98 itself during manufacture, and furthermore, since speed control is provided by the computer 98, speed control mechanisms normally included in disk drives are not required. As can be seen in Figure 9, since the microcomputer 97 detects the actual motor speed sound at line 99, closed loop operation is performed.

In this example? computer 97 as described
examines pulse 951 and determines the initial characteristics of motor 98 when, in fact, a new disk is placed in the disk drive, before data is written, or when a read or write error occurs. Obviously, other configurations can be used. For example, indicators can be inspected periodically or continuously.

In the embodiment described herein, the motor operates at speeds from 350 rpm for the innermost track to 70 Orpm for the outer track. It will be appreciated that the selected rotational speed range is a function of the radius of the disk and will vary depending on the particular magnetic properties of the 1,7'' disk drive and the dimensions of the disk.

As previously explained, during each horizontal erase period eight bits of data are provided to the acoustic counter 29 of FIG. 1 and the other eight bits are provided to the rate controller 27. In the embodiment described herein, only six of the bits on the frame 108 (FIG. 10) are used for speed control. 6 lines from bus 108 or shift register 1020
It is shown connected to six stages. When the audio data signal is loaded into audio counter 29, six bits from bus 10B are loaded into the six stages of shift register 102.

FIG. 1O shows a multistage counter.

The data placed in the six stages of the shift register 102 is
shifted under the control of a clock signal.

The effective shift speed is IMHz. Due to the various standby states contained in the shift register, an 8 MHz clock signal is actually provided to the shift register. Output cover for the final stage of the shift register 1. It is coupled via line 103 to one input terminal of exclusive-OR gate 104. The output of the first stage of the shift register is coupled via line 105 to the other input terminal of exclusive-OR gate 104. This arrangement provides for counting in a "multi-stage counter" in a manner known in the art. Each stage of shift register 102 is also coupled to a status detector 106.

This state detector determines when the associated binary state within the shift register is reached. Once that binary state is reached,
A signal is applied via line 109 to stop the shifting in shift register 102. The signal is measured at the end of the pulse in the same manner as used for the acoustic signal.
- used to generate

Next, refer to FIG. At the beginning of each horizontal lift,
A counting operation is started in the shift register 102. At this time, the edge 1 of the pulse shown in FIG.
A leading edge of a pulse such as 15 is generated. When the condition detector 106 detects the associated condition, the end of the pulse is generated as indicated by the trailing edge 116 of the pulse in FIG. These pulses are integrated by an integrator 114 and the resulting signal (line 10θ) is used to control the speed of the motor in a conventional manner.

The fC6 bit placed in shift register 102 always reaches the state detected by state detector 106 before the end of each horizontal sweep. In fact, for each horizontal sweep f
The condition is detected during the first 40 μs of approximately 44 μB to CJIi.

A horizontal sweep is used for each speed control signal.

This was chosen because the embodiment described here employs a total of 370 scan lines, evenly distributed in groups of 10. However, a pulse is generated every t1 valley horizontal sweep.

(The integrator 1140 time constant shown in FIG. 11 is long enough for a continuous signal to appear on line 100.) To obtain accurate values, the 1140 time constant used to define each speed control value is
The width of the pulse generated on each zero sweep is "oscillated". For example, if a value corresponding to 6.5 is 10
Assume that it is set at 0. Referring now to FIG. 12, for the 10 sweeps used to determine the value, the first has a value of 6, the second has a value of 7, and thus 10 Increase the value until the first sweep. The trailing edge 116 of the pulse is thereby varied between values 6 and 7. However, after being integrated, the value at line 100 is 6.5
will match.

By distributing the values during the 10 sweeps used to define each speed control value and creating a pulsed oscillation, very precise control can be achieved. Control precision of more than 6 bits loaded into the shift register is obtained. In the example described here, a unique level of 400 groups, i.e. log(400)/log(2)
bit is achieved.

Attached Table 3 shows a program for speed control written in 68000 assembly language.

What has been described above is an improved system for sound generation and motor speed control in a 70 tsupi disk drive or the like.

Table 1: This code is executed every 16 seconds in the direct retrace interrupt. This code is for the following sweep.

Calculate all 370 values.

MO■M, L (A6), D2-07/AU-A5:
Place in the acoustic parameter register M) VE, L 5oundBase, A6: ADD to the buffer, W #370, A6; At the moment, turn half to it M) VE, L [0OFFOOOO, DiCDI) Full mask setting for the high level part MOVE $2, - (SP): Outer loop counter start 8l0VE #185. -(SP): Circulate 185 times (buffer portion) Circulate once for each portion of 2370 values, and calculate the sum of waveform values for each audio 5-round loop.

CLR, W Di: Clear addition register (not mask) ADD, L D2. D3: Audio l full calculation ADD, L
D4. D5: Calculate audio 2 ADD, LD6. D7
;Voice 3? ! -Calculation ADD, L AO, Al: Audio 4
Calculate; MOVE to map audio 1 to Dl, LD5. DO N, L Di, D (1: Mask high order bits) DO; Use bits 16-23 MO ■, B 0 (A3.IXI), Examine DOS waveform light ADD, W DO, DI: It Kinryoku's mouth; audio 3
Add to Dl λ[VE, L D7. ■ to DO, L DI, DO: 5WAP DO to mask high order bit; use bits 16-23 MOVE, B
0(A4.D[)), DO: Adjust waveform light ADD,
W DO, DI: Cut it out; Move audio 4 to DI, MOVE, L Al, DO AND, L DI, DO: 5 WAP DO: Use hit 16-23 MOVE, B
0 (A5.DO), DO: Adjust waveform light ADD, W
DO, DI: Punish it: LSR, W that updates the DMA simulator with a new value #2. DI: Divide by 4 (use upper bits) MOVE, B DI, (A6): Place it in the buffer ADDQ s2. Ats; Bump the buffer pointer; Full cycle half of the value 5UBQ #11 (SP): Decrease the counter count full BNE, S 5oundLoop: Cycle until executed; Now execute the second half of the buffer hio ■, L 5oundBase, A6: Point IVIOVE to start of buffer #185. (SP): Counter t reset 5UBQ #1 + 2 (sP); 2nd
G') Decrease count BNE, S So Saragai L100p; Cycle until executed; OK, all rows, update acoustic table, restore register and return to caller ADDQ
#4. SP; Pop-on loop counter t MOVE-L 5ounclPtr, A6: Get table address ADDQ 62. A6 MOVEM, L D2-D7/AU→, 1. (A6)
: Save all acoustic registers, save pulse W ■L (mouse) + JD-D7/AO-AB : Restore caller's register 82 table ■■, L 5oundBaae, A2 : Get acoustic base address ADD, W #64. A2: Start of 32 bytes in LEA 676 (A2), A4; Calculate end address CLR, W (SP); Set path l flag MOvE#337. D2; 338 Hyde moves to 1,000 minutes; OK, everything is set now. Start raw loop to fill buffer M:) VE, B (Al), (A2): all DMA
/(tsu7ahe move ADDQ #2.A2: Bump ADD to the next location, L
DI, D3: Cumulative index total bump 5WAP D3; High partial gold gain in low territory M°C, W D3. Al: Bump to next entry (maybe) ADD, WD3. DO: Execute cumulative number CLR, W D3: Reset integer part 5LAP D3: Restore D3; Has our request been met? CMP, L Al, A3: Have we passed the end of the battle? DBLE D2. InterpOlate: Stop it if so Table 3 Nir-Tin: 5etSpeed, 5otASp, ee
d; Argument: D6. W (input), -) Rack number speed must be increased by 7 Drive (input) - Current disk drive TrkSpeedTbl (in) - Speed code table for current drive Wait (output) -- 0, or CutS
If speed changes, secure registers other than Spd ChgTime, AU-A2, DO-()2; Cold-by: (SetSpeed): 5ee
k+EWPower(SetASpeed): 'M
&kespdThl;Function: This routine determines the correct speed value for the track and sets the PWM memory buffer to produce the desired output. If the speed is changed, the value of Wait is set to SpdChgTime. Otherwise, the TrkSpeedThl for the current drive is used.

In memory (y) Just like the PR'M buffer,
Drive enable cannot be changed.

5etASpeed is pwm buffer full D full circle 2 -
Simply set another entry point according to the code.

Fast melon foot BSR-8GetDrvl: DI, AI'c
Set MOvE-W DO, D2; Speed 5 Suha exactly? Rack number LSR, W #4. D2: LSL divided by 16,
W #3. D2; Adjust double word index ADD, W Di, D2; Add drive specific offset MOVE, W TrkSpeedTbl (AI, D2)
, D2 S ADD to get the required speed, W 0ffS
peed (AI, DI), 2: Add in adjustment (
Maximum and minimum anvil) BSL, S @2 Not less than S0 M) VEQ #
0, D 2 @2 CMP, W #399. D2 BLE, S @3 Shu IVE, W #399. D2: Do not exceed 399 @3 MOVE-W F%MValue, DO: Do you want to set that speed? BPL, S @4; If the speed is invalid, what is the power-on time? Wait MOVE, W PwrOnTime (AlhaT) OBR
A, S @6 @4 SUB,'W D2. DO BEQ, S GetDrvl: If so, just use the BPL, S @5 cutting blade, w no: Positive speed difference @5 LSL, W s5. Do: CMP, W SpdChgTime (AI), IXI multiplied by 32 to obtain speed stabilization time
; Minimum waiting time for speed change BG'l', S @6 MoVE -W SpdChgTime (Al)
, D) @6 ADD, W Wait(AI), Do
: Add to current standby time QvlN), W PtvrOnTime(AI), DO
BLT, S @7 Il/1) VE, W PwrOnTime (AI),
D (J07 kDVE, W DO, Wait (
Al): 5etASpeed is another entry point that simply sets the speed code in D2. L D3-D6/A2. -(SP)
: A2-A7. D3-D7 all retained SUB, W $399. D2: (sony)
Reverse it N decoy, W D2 EXT, L D2: Make the meeting longer...Salary DIVU
#lO,D2 ; Remainder 1ulOVEQ in high-level word
all, I) 0 @l M) VE, B Do, Di: King speed [(ifI
VX) VE, B DO, D3: Pit uH holding LSI
<, B #1, DO mi also, B DO, D3 LSR, B $1. D3;: i-ishi pit 5-cy
BCC, S@2 BSgT #5. DO Di Feng D2. @1 &WAP D2: Remainder is vibration full decision MOVE, B DitherTbl (D2), D5:
From the vibration table, lO bit required ASL #8. D5 1i[)VE, B DitherThl+1(D2),
D5: Obtain 2 bits from the following LoadP9i/MBuf M) ■, Q #36. D3: Perform large loop all 37 times LEA PWM Buffer, AU; Fill PWM buffer (37Xlα=370 bytes) M) VE, L PWM Buf2. A2: For another buffer @IM) VE, Q #9. D2; MOVE performed in inner loop 'iio times, WD5. D4: Vibration pattern @2 LSL
, W #1. D4 ; The digit is hit = li, [use for quotient 1'? f: Meaning BCC, S @3 M (J ■, BDO, D6; BRA for high value group, S
@4 03M0■;, B Di, D6: Main 1 [all use @4 pulse 'E, B D6. (A2) ADDQ #2. AO: All other bytes are sound staff AI) DQ $2, A2 DBRA D2. @12 DBRA D3. @I MOVEM, L(SP)+, D3-D6/A2: Check reg retention rules 5etSpdExit BRA GetDrvlDit
herTbl: Used to oscillate speed values evenly, BVte f1i00J20. IFi2i, fB24
．． ! l194,B)'te f11AAJB5JB7,
51i7BJP”FJ40.$00

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer system illustrating address multiplexing used in connection with the present invention;
Figure 3 shows the timing diagram used to describe the times when digital signals representing sound are accessed from RAM 7) and the times they are updated in RAM; Figure 3 shows the counters used to generate the audio signals; 4 is a waveform diagram of the signal generated by the counter shown in FIG. 3, FIG. 5 is a flowchart used to describe the entire method of generating the data signal, and FIG. 6 is a diagram of the audio signal and volume. Figure 7 is a flowchart showing how to generate the data signals for the four types of tones; Figure 8 is a flowchart showing how to generate all the 'non-harmonic' audio signals; 9 is a block diagram showing the overall interconnection between the computer shown in FIG. 1 and the disk drive motor; FIG. 1O is a circuit used to generate all speed control signals for the disk drive; The part? Block diagram shown,
FIG. 11 is a block diagram showing additional portions of the circuitry used to generate speed control signals for disk drives;
FIG. 12 is a graph used to describe the surface of the present invention. 1o--Microprocessor, 11. Random access memory, 13.e data buffer, 14
...-Serial communication controller, 15...Interface adapter, 17.φ...Read-only memory, 1
8...-disk controller, 22...Φ-video counter, 27@-...disk speed controller, 28...-video shift register, 29...-audio counter, 97-Φ
・・Computer, 98・・Disc drive motor,
102·e@-shift register, 106···state detector, 112···pulse generator. Patent applicant Azul Computer Ken Inc. Agent Masaki Yamakawa (and 2 others)

Claims (1)

[Claims] <1) Microprocessor and random access memory (
RAM) In a computer system that provides all video signals to a display device that is scanned, the RA is used during a horizontal erase period to obtain a data signal representative of the audio signal.
M'ir access, converting the data signal into the audio signal, and updating the data signal representing the audio signal during the vertical erasure period, thereby disturbing the video signal. A method for generating an analog audio signal t-, characterized in that said audio signal is provided without interruption. (2. In the method recited in claim 1, the microprocessor (a) in addition to a predetermined number of stored numbers, Il\?
Yi 枦噌+1allNo1μ,No-1,,a,,++
+---Use Leri as heron a# book+--+, Ra141shi11kin2:'I-+, (c) Store the sum as the stored number in process (a). , (d) all the data signals from the lookup table in the RAM
the data signal representing the entire audio signal by placing it in the gold;
Thereby, the method is characterized in that the fundamental frequency of the audio signal is a function of the predetermined number and the harmonic components of the audio signal are an integral number of the contents of the lookup table. (3) In the method described in claim 2, a predetermined number is added to N stored numbers, and the resulting sum of N or the location in the search table of N1@ , wherein the most significant pit of the sum of data from the N search tables provides the data signal representing the entire audio signal. (4) Microprocessor and random access memory (
It includes RAMJe and sends the video signal to the raster scanned display device to the J5J stone computer. coupled to the RAM, directly accessing a predetermined location in the RAM when the video signal enters a horizontal erase period;
addressing means for enabling said microprocessor to write new data to said location when said video signal enters a vertical erase period; and converting data accessed from said location by said addressing means into said analog audio signal. What waveform means? Apparatus for generating an analog audio signal, wherein the audio signal is provided to the computer device in an efficient manner. (5) The apparatus of claim 4, wherein the waveform means includes a counter for counting the data loaded from the location of the RAM at a predetermined rate; Apparatus according to claim 1, further comprising a pulse generator that starts the pulse when a counter is loaded and ends the pulse when the counter reaches a predetermined count. (6) The apparatus according to claim 5, characterized in that the termination of the pulse occurs when the counter has run out. (7) Is the device according to claim 6 an integrator for integrating the pulses from the pulse generator? A device comprising: 8. The apparatus of claim 4 or 7, wherein the horizontal cancellation occurs at a frequency of about 22,000) Iz. 9. The apparatus of claim 8, wherein said vertical cancellation occurs at a frequency of about 60)Iz. 10. Apparatus according to claim 4, including additional waveform means for converting data from said location by said addressing means into a speed control signal for a disk drive. Ql) Microprocessor and random access memory (
In a computer device that provides a video signal to a display device subjected to raster scanning, the computer device includes a RAM) Th and provides a digital calendar representing timing 1 of the video signal)'(f-a first counter to be provided to the display device, the counter and the RA
first address multiplexing means coupled to M and for coupling the digital counter lf from the first counter as an address to the RAM during at least a part of the horizontal erasing period of the video signal; coupling the digital count from the first counter to the RAM as a full address while the code is providing information for display on a display;
and during at least a portion of the vertical erasing period of the video signal, all of the address signals from the microprocessor R
a second address multiplexing means coupled to an AM; and a waveform means for converting data from the RAM area addressed to the first counter during the horizontal erasing period into the analog audio signal. A device that generates an analog audio signal. (12. The device according to claim 11,
The waveform means is coupled to a second counter that counts at a predetermined rate the data loaded from the location in the RAM; and a pulse t1 when the second counter is loaded? and a pulse generator for terminating said pulses when said second counter reaches a predetermined count. (13) q-J. Apparatus according to claim 12, characterized in that the termination of the pulse occurs when the counter has run out. (14) The device according to claim 13,
An apparatus characterized by comprising an integrator for integrating 8+j pulses 'ft from an if pulse generator. 15. The apparatus of claim 11 or claim 14, wherein the horizontal cancellation occurs at a frequency of about 22,000 Hz. (16) The device according to claim 15,
An apparatus characterized in that the vertical erasure occurs at a frequency of #60Hz. (17) The device according to claim 41,
The first counter calculates the R during the horizontal erasing period.
The apparatus is characterized by additional waveform means for converting the data accessed from the AM into a speed control signal for the disk drive. (18) Microprocessor and random access memo'
)(RAM)? ! ``In a computer device that provides a video signal to a display device that is scanned by raster, the RA
M and a predetermined location in the RAM when the video signal enters the horizontal erase period? ]-addressing means for directly accessing and enabling the microprocessor to write new data to all the locations when the video signal enters a vertical erasing period; An apparatus for generating a speed control signal for a disk drive, comprising waveform means for converting the speed control signal into a speed control signal for the disk drive, wherein said speed control signal is provided without interfering with said video signal. . (B) *The apparatus of claim 18, wherein said waveform means is coupled to a counter for counting at a predetermined rate all said data loaded from said location in said RAM. , a pulse generator that starts the pulse when the counter is loaded and ends the pulse when the force counter reaches a predetermined count? To prepare? Featured device. (2. The apparatus according to claim 19, characterized in that it includes an integrator for integrating the pulses from the pulse generator. (2. Claim 18) 2. The apparatus of claim 1, wherein the computing device detects the speed of a disk drive and varies the control signal as a function of the speed to perform dynamic calibration. 22. The apparatus of claim 18 or 21, wherein the speed control signal is varied as a function of the tracks accessed on the disk.