CA1226961A - Sound generation and disk speed control apparatus for use with computer systems - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

An apparatus for generating an analog audio signal and a speed control signal for a disk drive for use with a microprocessor having a RAM which provides a video signal for a raster scanned display. Direct addressing to the RAM is used during horizontal blanking periods to allow data to be read from the RAM and used to generate the audio and speed control signals. The data is updated during the blanking periods. The speed control signal to the disk controller varies as a function of track (radius).

Description

BACKGROUND OF TRY ~NY~NTION:

1. Field ox the Invention.
The invention relate to a sound generation apparatus, particularly ode employed with a computer system which includes a S raster scanned display and a disk speed control apparatus.

2. Prior Auto There are countless well-known techniques ton generating audio signals prom digital signals. These include the more straightforward approaches where digital signals are used to provide an instantaneous amplitude of the audio signal, to the more complex coder techniques where transfer. junctions representative ox voice are used. As ~111 be teen, thy present l~ve~tio~ convert a digital signal to an analog (audio) signal, although this conversion it only one aspect ox the present invention lo ought Own computer systems, particularly smaller system (eye., personal computers) employ raster skinned displays. The computer generates the video in~ormatlo~ and stores it it a ra~dom-access memory ROY. Counters synchronize with the horizontal and vertical ~ynchro~l~atio~ signal address the memory to provide display synchronized data signal from thy emery These signals are cavorted to a Leo iguana or i~sta~ce, through a shift register. In some case, thy memory bit aped" and the output Roy the Emory 6 directly used to generate the vim swig other cases, the OUtpllt prom toe Emory addresses ; character veneration which it Canada to provide video sisals.

Jo A considerable amount ox data prom RAM is required to generate a video display, particularly in a dynamic, graphics (non-te~t) mode. In the personal computer field, or small business computer yield, where microprocessors are used along with dynamic Rams the generation ox a video display consumes a relatively large amount of processor and memory time. It is thus di~icult to provide an audio signal, particularly a complex audio signal in a display mode, As will be seen the present invention provides an apparatus Jo for generating audio signals in conjunction with a microprocessor and RAM simultaneously with the generation ox video signals. The audio signals are generated without disrupting thy video display or computer operation, and importantly, with a minimum of hardware and processor time.
Typically in sloppy disk drives, some mechanism us employed to drove the sloppy disk motor at a constant speed. when the sloppy disk drive is manufactured, certain calibration steps are often used to assure that the floppy disk drive runs at a predetermined rate ox rotation. This requires, in addition to the calibration steps, relatively costly speed control mechanisms. As Jill by Seed / in the present invention, the computer is used to sense the rate ox rotation ox the disk drive and then provides a control signal to adjust the disk drive's rate ox rotation. This eliminates the prior art calibration and also tube prior art's speed control mechanism.
It has been suggested in the prior art that better utilization ox floppy disks or other disks can be obtained I
uniform isle density truncheon are used. This requires that the rate of rotation of the disk be made a function ox the radius of the particular track being accessed. The present invention provides such a feature.

, SUMMARY OF TOE INVENTION
, .
The present invention provides an apparatus or use with a computer system which includes a microprocessor and random-access memory (RAY), particularly where a raster scanned display is used with the computer system. Addressing means are used or directly accessing predetermined locations in the RAY, especially during the horizontal blanking period. The addressing means also permits data in these same locations to be updated during the blanking periods.
The data stored in these locations is converted prom its digital Norm to an analog signal. A pulse is initiated whey the data prom memory is loaded into a counter. The pulse is ended when the counter reaches an overflow. The resultant pulses are integrated to provide the audio signal.
The processor generates the data signals or the RAM or a single tone by adding a predetermined number to a stored number.
The most significant bits ox this sum identity a location in a look-up table add the resultant (digital data signal is then stored in RAM. The predetermined number it repeatedly added to the stored number to provide each of the data signals or the RAM. or more complex tones, a umber ox predetermined numbers and stored numbers are used along with a plurality ox lock-up tables The present invention also provides an apparatus or controlling the rate owe rotation ox a disk. The addressing meats used in conjunction with the sound generation apparatus are used as I part ox the disk control apparatus.

I

BRIEF DESCRIPTION OF TOE DRUNKS
. . _ _ Figure 1 is a block diagram ox the computer system and illustrates the address multiplying used in con~unctlon with the present invention.

figure 2 is a timing diagram used to describe times at which the digital signals representative of sound are accessed from the RAY and times at which they are updated in the RAY.

Figure 3 is a block diagram ox a counter used to generate the audio signals.

Figure 4 illustrate waveforms generated from the counter ox Figure 3.

Figure S it a flow diagram used to describe the method by which data signals are produced.

Figure is a block diagram and schematic ox the circuit or providing the audio signal and volume control.

Figure 7 is a Plow diagram illustrate the method by which data signals are provided or Pour tones.

Figure 8 is a slow diagram illustrating the method by high data signals are joyride or a "non harmonic" audio signal.

Figure 9 is a block diagram illustrating the general interconnection between the computer of Figure 1 and a disk drive motor.

Figure 10 is a block diagram illustrating part ox the S circuit used to generate the speed control signal for the disk drive .

Figure 11 is a block diagram illustrating an additional portion ox the circuit used for generating the speed control signal or the disk drive.
Figure 12 is a graph used to describe an aspect of the present invention.

DETAILED DESCRIPTION OF TOE INVENTION
. . . _ .
An apparatus or generating audio signals in conjunction with a computer system particularly one which generates signals for a raster scanned display and for generating a motor speed control signal it described. In the Pulling description numerous specific details are jet forth such as specific frequencies, number ox lines commercial part numbers, etc., to provide a thorough understanding ox the present invention. Hoover it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. It other instances ~ell-known circuits have been shown in block diagram ~orm.ln order not to unnecessarily obscure the present invention.
DEFINITION
In the following de~criptlon, the term "audio or wound data signal" or "sound data" is us to ldenti~y a digital signal which is converted to an analog (audio signal. Thy term motor speed control refers to thy control of rate ox rotation of a motor or disk driven by the motor.
GENERAL ARCHITECTURE
The present invention is currently realized a part ox a computer system (personal computer or small buoyancy computer employing a Part No. 68000 microproce~or. The address lines and data lines or this microprocessor 10 are shown in Figure 1. The other ~ell-kno~n lines coupled to this processor are jot owe in I Figure 1. The microprocessor lo is coupled to a ra~dom-access memory AYE) 11 comprising slxSeen OK dynamic memory "chips". The data line Q-15 i~t~rco~ct the microprocessor 10 and RAY 11 to

3 3 permit data to Yule prom the processor into the RAM. the data from the RAM is coupled through the JAM data butler 13 into the processor; also data is coupled -From -the RAY 11 to disk motor speed controller 27, video shirt register 28 and sound counters 29. The latter counters ~111 be described in detail in conjunction with Figure 3. Data is also received by the microprocessor 10 prom the read-only memory (RUM) 17 when the ROM is enabled Truman/).
Similarly, data is transferred to and prom the disk controller 18 when the disk controller 18 is enabled by a signal on line 35. This signal, as is the ROMEO/ signal is generated within the PALS 23.
Data is likewise coupled to and from the microprocessor 10 Jo a serial communications controller 14 and an interlace adapter 15 (Commercial Part Nos. 8530 and 6522, respectively).
addresses prom the microprocessor 10 are coupled to the ROM
17, PALS 23 and AYE address multiplexer I Some ox the address signals, as indicated, are also coupled to the disk controller 18, serial communications controller 14 and interface adapter 15.
The RAY address multiplexer 20 permits the RAM to be addressed either by the microprocessor 10 or directly by the count stored in the video counter 22~ During the time when the video signal is "painting" the screen, the multiplexer 20 selects the video counter 22, thus allowing the courter to directly address the RAM 11. (A signal prom PALS 23 controls this selection.) Turing other times, the RAM address multiplexer I permits the microprocessor 10 to directly access the JAM 11. The second address multiplexer 21 as is multiplexer 20 I controlled by a signal from the PALS 23. During the last portion ox the horizontal blanking signal, as will be described in conjunction with Figure 2, multiplexer 21 selects the highest order 7 bits prom the counter 22 and forces the memory to this address. This requires that the sound and disk speed data be stored in dedicated and consecutive locations of the RAY and permits easier access by the microprocessor when *his data it updated. A latch not shown, provides an additional bit input to the address lines ox the multiplexer 21 to cause direct access to a second page ox sound data in RAM 11.
The video counter 22 which consists ox two Part Nos. 74~S393 provides a digital video count which corresponds to the Bohemia position on a raster scanned display and additional counts ton the horizontal and vertical restore blanking) periods. The timing signals which operate this counter lug with the reset signals are generated by the PALS 23.
The PALS 23 consist ox three program array logic chips.
They receive the crystal controlled 16mHz oscillator inlay prom oscillator 31. The PALS 23 generate prom this soggily the standard memory igloo such as RASP, US and the elk timing signals used by the microprocessor. They also provide the horizontal synchronization signal (SYNC/) and thy ver~lcal synchronization igloo (VS~NCt~. These signal art collpled to the display ox lines 32, other docking signal used throughout the Emory, such us the 8 My clocking igloo used by the counters ox Figure 3 and the clocking signal used by the disk motor speed controller are generated within the PAL 23.
Two 32R~8 Rows 17 are employed in the presently prowar embodiment. They provide Syria or diagnostics, i~itiali2a~10n I

1 and other functions not relevant to the present invention.
The disk controller 18 provides an interface to a floppy disk drive. The controller is described in more detail in cop ending Canadian application Serial Noah, filed November 20, 1984, entitled "Integrated Floppy Disk Drive Controller", and assigned -to the assignee of the present invention.
The adapter communicates with the keyboard 24. A
mouse 25 provides cursor input and switching information to both the controller 14 and adapter lo. A volume control knob is drawn on the graphics screen and is controlled by the mouse to provide three bits of binary data on lines 37. As will be described in conjunction with Figure 6, these three bits are used for a static volume control for the audio signal.
VIDEO TIMING
....
In the presently preferred embodiment, horizontal scanning occurs at a rate of 22,256.84398 Ho. Vertical scan-in occurs at a rate of 60Hz. Each frame consists of 370 scan lines and there are 704 pixels, or dots, per horizontal scan. This corresponds to 44 sixteen bit words from the RAM 11. Thus, the main clock rate from oscillator 31 shown as 16mHz is more accurately 15.6672mH~.
Referring to Figure 2, on the display itself there are 512 "live" pixels in the horizontal direction and 342 lines on to screen. The 192 remaining bits during each horizontal scan is the horizontal blanking period sometimes referred to as the "fly back" time. It is during this period of time that the beam current in a cathode ray tube is lowered and the beam brought back from one side ox the screen to the other. In the vertical direction, in addition to 342 lines on the display, there are 28 additional periods during which time the vertical blallking occurs, that is, the beam current is again reduced and the beam returned prom the lower part of the screen to the upper part of the screen.
In figure 2, time is shown prom let to right by, or instance, the dotted line 39. On the lust scat, aster 512 wits have been displayed, the time represented by line 40 is reached, and blanking occurs. During blanking, it it not necessary Pro the JAM 11 to furnish data or the display. Prior to the time 40, referring to Figure 1, the count from counter 22 accesses the RAM 11 through the RAM address multlple~cer 20. Lucy occurs or each owe the flues it thy display. the counter I maintains Roth horizontal end vertical court . the counters do not increment in the llormal sense during the horizontal blanking period. Rather, Your bits OX the video counter are Rudy ton lo counting during this period. This eliminates address zaps for the sound data Y1hen time 40 is reached or each OX the scat fines, a timing signal prom the PALS 23 causes the multi plexer 20 to accept Rddresse3 Iron the microprocessor 10. During gee Text 19~ counts ox the 16m~1z clock, except ton the last count, the microprocessor it free to access the RAM and thus con periorlD tasks unrelated to the display. when thy last count in each OX the scan lives it reached, a sign rum the PILLS
23 Cassius the courter 22 through multiplier 21 to directly access the memory 11. At they'll tlsl~, the s~xteell bit Ford Roy the RAM 11 time 41 of figure 2) is read from the rnsmory Vito 8 by is going Jo toe Dick motor speed stroller 27 and 8 bits to the sound counters 29 was Jill ye inn, only six issue are used by the disk motor speed control lo Jo I

27.) During the "screen lime" one in Figure 2, the si~teen'bit words prom the memory are placed in the video shirt register 28 and used to provide the video signal. The PALS 23, as mentioned on line 32 provide the horizontal and vertical synchronization signal used in conjunction with the signal from the shirt register 28 to control the video display.
when the 342nd scan line is reached (shown as line 43~ and at time 40 along this line, the multiplexer 20 again alloys the microprocessor 10 to access the RAM 11. Ho~evsr 9 at the end ox line 43 and or the remaining period ill the vertical blanking, the multiplexer 21 still forces 9 bits ox address into the RAM 11 at time 41 to alloy the 16 bit word to be supplied to the speed controller 27 and kiter 29. (The lines RAY to RAY are time multiplexed to provide these address signals.) During the vertical blanking the microprocessor 10 is able to access the RAM 11, except for the last count ox each fine. It is during this period ox time as will be described that the disk motor speed control data and sound data stored in the RAY 11 is updated.
The multiplexer 21 with its wine bit address dullness contiguous locations in memory, thus alloying all the ode and motor speed data to be more easily accessed and updated by the processor lo Note that the Tory location in the RAM 11 for the sound and speed control data Jill be in a dli~erent location than thy screen data.
As currently implemented, during "live" video the microprocessor and video display signal transfers time share the data buy in alternating c~cle~O ~urlng horizontal blanking (ton I

words 32 to 42) the microprocessor alone has access to the data bus.
At time 41 ox Figure 2 (43rd Ford) the microprocessor and sound/speed data transfer time share the data bus in alternate cycles.
: It is possible or the microprocessor to update the wound data and speed control data during the five video. The data is, in tact, updated during blanking periods. As currently implemented an preferred, the vertical synchronization signal retrace signal) initiates the sound data updating. By using this signal and by updating the locations already accessed (e.g., beginning at the location used at line 39, time 41) updating does not interior with the reading ox the sound data. The outwore program assures that the updatln~ remains ahead ox the reading ox the solenoid data. It the microprocessor update the sound data without being synchronized lath the display, data could by replaced before being used. Also this arrangement frees the software prom the requirement ox being time synchronized with the wound for updating the data.
AUDIO SIGNAL GENERATION
The eight sound data bits represent the audio signal ore shifted in parallel unto two four hit counters 46 and 47, shown in Figure 3. these are commercial counters (Part No. 161~. Tb2 counter are clocked by the 8mHz docking signal on line 48.
Kettle kettles in these Conner until overrule which is tensed ox line 49- Tub, I all zeroed are placed in the Corey, longer period ox tire it required until oriole approximately 32 eke err oriole cay occur as soon a one cycle ox the 8mHz clock of all ones are loaded into the kiter.

The audio waveform is developed by first generating pulses the widths ox which are a junction ox the time between the loading of' the eight bits into the counters 46 and 47 and overflow. or instance, as shown by Figure 4, the leading edge 52 ox a pulse occurs upon loading ox sound data into the Courters. If all zeros are loaded, then approximately 32 eke. later, virile occurs and the pulse ends us indicated by the trailing edge 54. One pulse is generated during each horizontal sweep since one eye bit sound data Ford is loaded into the counters during each sweep. Therefore, lo pulses are generated at a frequency ox approximately 22,000~z, and in theory, this provides a bandwidth ox approximately Lucy. It Figure 4, a second pulse 56 is shown which has a subs~aDtially reduced width. This, ox course, would occur when a larger number it placed into the counter 46 add 47. The pulse 57, which is shown occurring during a third step, has a width which walls Betty the first and second pulses The pulses are integrated using an ordinary l~*egrator to provide the analog signal. The integrator By of Piggery 6 receives a load signal and the overrule signal; thy waveform 61 shown in figure

4 is developed within the integrator 60. aroma I represents the resultant integration ox the pulses shown on lure 4.
The three bits ox information Betty aye, 37b and 3?c~ prom the inters adaptor 55 are used to alloy a user to statically control volume. The ampler 63, 64 and I are it'd (ox or ox) to Kermit the output amplitude on live 68 to be caterwauled.
CALCULATION OX TOE SOUND DATA GOALS
Sound data Roy the memory which Dodd the wound ~ave~Qrms I

I

are calculated by the microprocessor 10. None specially they are "so~tware'l generated within the microprocessor. A higher order language, such a PASCAL, Jay be used to allow a user Jo more easily implement the flow diagrams which ore discussed below. In general, the sound data are produced quite rapidly since the process takes advantage ox the rapid adding capability ox the 68000 mlcroprocessorO
Referring to Figure I assume that a single laurel tone is to be generated. First, a lvok-up table it stored within tube system ] o memory; in the presently preferred embodiment the look-llp table is 2~6~8 bits. Thus, ton each eight bit address to the table an eight bit output results. or a pure tone, the lockup table contains points corresponding to a ~inewave. This is illustrated by the look-up table 70 ox Figure 5. The process ox generating the address for the subsequent value table is the repeated adding of Rome predetermined umber shown in block 74 as I to a nwDber stored in register 72. Initially, the 32 bit word stored in register 72 may have an value, or instance, all zeros. The increment, I is added to it. Thy resultant sum is restore it register 72.
The most significant eight bit are stripped prom the sum as shown by block 76 and used as an address for the look-up table OWE
Assume or sake ox discussion that 0 I small. Mach time this relatively small binary number is added to the number stored it register 72, the most sig~iiicant bits ~11 not change, but rather, numerous additions are needed our the to change.
Consequently, Mach ox the 256 locations in the look-up table 70 will be addressed several tires and the tight bits of data prom the , I

look-up table which are stored within the RAM 11 will vary slowly.
This, ox course, Jill correspond to a low frequency. It, on the other hand, the increment JO is relatively large, the results from the look-up table will change more rapidly and thus, for instance, each ox the consecutive eight bit data words prom the look-up table 70 which are stored in the RAM 11 will be different. This Gould correspond to a high frequency A new eight bit sound data word is obtained with each addition represented by block 74. Therefore, by varying the increment added on each cycle, the frequency ox the tone is virile. All the sound I data used during each frame can easily be calculated during a eye scan fine periods ox the vertical blanking period.
To obtain envelope control or amplitude modulation, a set ox tables may be used. Each table, ton instance, ox set 0-7l CoDtaiDS a sine~ave with maximum peak to peak value ox SET No By alloying a predetermined number ox frame intervals to pass before switching between jets, envelope control achieved.
Reargue to Figure 7, in the presently preferred embodiment, up to four 256~8 look-up tables may be used within the microprocessor lo And, the contents ox each look-up table can be user programmed and each may be di~ierent. For instance, look-up table 80 ox Figure 7 is shown as containing a sine wave, table 81 as a triangular wave, table 82 a a square wave, and table 83 as a ramp. The process described in con~u~ckion with Figure 5 it again used. Rover, this time with tour simultaneous tones being generated 24 bits, rather than 32, are used 25 (This is shown my block 85 in Figure 7.) A an insinuate on 1 is added to the previous sum (bloc 86). The most significant bits are tripped prom the sum (block 87) no used as an address for the corresponding eight bit word within the table 80. The same process is repeated or the number shown it hi block 87 where a different (or the same increment aye is added shown at block 88, and again the most significant bits ox thy sum are used to address looX-up table 81. Similarly, different stored values and increments are generated to alloy look-ups in tables 82 and 83. The resultant eight bits from each ox the tables are added as shown by blocks 80, I 90 and 91 and the most sigsi~lcant eight bits are stripped prom this sum as shown by block 92 and stored within the memory 11. This process is repeated or each of the sound data words stored within the RAM 11 when your tones are generated. Once again, the fundamental frequency Or each ox the your tones is determined by the increment high it added such as at hocks 86 and By and the harmonic context it determined by the "shape" stored inn the look-up table.
Table I, attached, it a program ~rltte~ in 68000 assembly language or implementing the flow dla~ram ox Figure 7.
with the above-described wound generation apparatus J
excellent tote control is achieved with up Jo 24 bit ox "~requPncy control being possible (or each tone) within the llkhz band This permits almost 17 million dl~er~nt tones to be erred ~ithln the band which it appro~l~ately equal or eater to the best discernabillty of the human ear.
The above described proses are particularly suited or providing periodic unction which are harmonic in nature and ?

provide a tonal quality representing music, and the like. For sounds such as voice, an "extended" look-up buffer may be used for initially storing a waveform representative ox, or example, speech.
This is shown as Burr 93 in figure 8. Thy buyer in awoke can ho within the RAM if and for practical reasons must be it a long waveform is to be stored. The eight bit values are again obtained by adding some increment I shown in block 95 to a 32 bit word stored in register 96 with the most significant bits being used to address locations in the buyer 93. The results for the look-up on Jo the emended buffer are stored an selected during the horizontal blanking period as was the case with the case ox Figures 5 and 7.
Table 2, attached, contains a program rotten in 68000 assembly language or implementing the slow diagram ox Figure 8.
DISK MOTOR SPEED CONTROLLER
____ __ Yost typically, floppy disk drives and other disk dries, include a mechanism for driving the disk at a constant, predetermined rate ox rotation speed). Upon fabrication of the disk drive, the speed control mechanism is calibrated to assure that data will be recorded and retrieved at a certain rate.
For the present i~ventioD the motor speed is controlled by a computer, and moreover, the motor speed is varied as a junction ox the track being accessed so that unl~orm Lowe densities result.
That is, the motor turns slower when the outer tracks (greater radius) are being used and Easter when the ire tracks (smaller radius) are being used.
In Figure 9, the computer ox Figure 1 is shown as computer I A disk drive sunk as a sloppy disk drive and in particular, a I

I

disk drive motor 98, is also lacerated wine 99 provides the computer 97 with pulses which indicate the motor speed. In the presently preferred embodiment, the studier indexing pulses prom the motor are used. Thy floppy disk drives employed are keyed to the motor hut, and thus Jo slippage occurs. Consequently, the lndz~
pulses themselves represent the actual rate ox rotation ox the floppy disk. It slippage is possible, then markers or bit streams prom the disk itself may be used Jo obtain an accurate indication ox the dusk spend. The speed control signal on line loo controls the motor speed. A predetermined signal level is used on line lo and the motor speed sensed on line 99. This alloys the computer 97 to record the characteristics ox the motor 9B. That is, *he computer knows or etch motor connected to it, the rate ox rotation of the motor or a particular speed control signal. It this manner the disk drive motor 98 itself need not be calibrated when Heinz ma~u~actured, and moreover, the speed control mechanism normally used within the disk drive is not needed since the spied control occurs prom the computer 98. As is apparent prom Figure g, closed loop operation occur since the computer 97 sense the actual motor speed on line ED
As currently implemented the computer 97 examines the pulses 99 and, I e~iPct, determines the characteristics ox the motor I when a new disk is placed it hi the disk drywall, before data is written or it errors occurred on reading or WriteNow, Obviously, other arraDg~ments may be used, or in~tanc~, the indexing pulse con be checked perio~icallgt or or that matter, continually.
. .

In the presently preferred embodiment, the motor operates at a speed from 350rpms or the innermost track, to 700rpms or the outer track. Obviously, the selected range orate ox rotation Jill be a function ox the radius ox the disk and will vary, depending upon the particular magnetic characteristics ox toe system and the size ox *he disk.
As previously mentioned, during each horizontal blanking period, 8 bits ox data are provided to the sound counters 29 ox Figure 1, and 8 bits are provided to the speed controller 27. In the presently implem~Mtation only six of the bits on this bus are used or speed control. The bus is illustrated as bus 109 in Figure 10 and these six links prom the bus are shown coupled to six stages ox a shirt register 102. The six bits prom the buy lob are loaded into the I stages ox the register 102 when the sound data signals aye loaded into the sound counters I
Figure 10 implements a polynomial counter. The data placed into the six stages ox the shirt register 102 are it'd under the control ox a clocking signal The elective shirt rate is approximately lmRz. Because ox the various waiting elates lnvolv~d in the iota register, the 8mHz docking signal is ~ctllal lye coupled to the reglst~r. The output ox the last stage ox the register is coupled to one input terminal of an exclusive OR gate 10~ through line 103. The output ox the irrupt stave is coupled to the other input terminal ox the gate 104 through line 105. This arrangement provides ton counting in the "polynomial generator' in a manner known in the prior art. The stage ox the shirt writer 10~ no also coupled to a state detector 106. This detector determines eye on I

a predetermined binary stave I reached within the gut register.
When this state is reached, a signal us coupled over line 109 to stop the shifting within the shill register 102; this signal is used to generate thy end ox a pulse in the same manner as used or the sound signal.
Referring to Figure 11, counting begins within the shirt register 102 ox Figure 10 at the beginning of each horizontal sweep.
At this tome, the leading edge ox a pulse is generated such as edge 115 ox the pulse one in Figure 12~ when the state detector 106 detects the predetermined state, the end ox the pulse is generated such as shown by trailing edge 116 ox Figure 12~ The pulses are integrated by the integrator 114 and the resultant signal on line 100 is used to control the speed ox the motor in an ordinary manner.

The 6 bits placed ~ithia the shirt register 102 Jill always reach the state detected by the detector 10~ before the end ox each horizontal sweep. In practice, thy state will be detected fluxing the first eke. ox the approximately Seiko. required or eye horizontal sweep.
Ten horizontal sweeps are used ton each speed control setting. This is chosen wince the printwheel preferred embodiment employ 370 total scan lines which is evenly distributed by 10.
Nonetheless, a pulse is generated or each hairstyle weep. (The time constant associated with the integrator 114 ox figure 11 is slow enough that a continuous ~lgnal results on Lowe 100.) The pulse idea generated or each ox the 10 swoop used to define Mach speed control value it "dithered to prowled precise values. For ''?~, instance, assume that a value corresponding to 6.5 is required on line 100. Referring to Figure 12, for the 10 sweeps used to define this value, the first would have the value 6, the second the value 7, and so on or the 10 sweeps. This would cause the trailing edge owe the pulses to vary between the values 6 and 7. Aster being integrated, however, the value on line 100 Gould correspond to 6.5.
By distributing the values and permitting the pulse dithering during the 10 sweeps used to define each speed control number, very accurate control occurs. Control accuracy beyond the 6 bits loaded into the shift register is obtained. In the present realization 400 unique levels or log bits are achieved.
log 12) Attached as Table 3, it the program used for the speed control, written in 68000 assembly language.
Thus, an improved apparatus ha been described what permits both sound generation and motor speed control it a sloppy d~sX
drive, or the like.

Claims (22)

1. In a computer system which includes a microprocessor and a random-access memory (RAM), and provides a video signal for a raster scanned display, an apparatus for generating an analog audio signal comprising:
addressing means for directly accessing predetermined locations in said RAM the said video signal is in a horizontal blanking period and for permitting said microprocessor to write new data into said locations when said video signal is in a blanking period, said addressing means being coupled to said RAM;
waveform means for converting data from said locations and accessed by said addressing means to said analog audio signal;
whereby said audio signal is efficiently provided by said computer system.

2. The apparatus defined by Claim 1 wherein said waveform means comprises:
a counter into which said data is loaded from said locations of said RAM, said counter counting at a predetermined rate after said data is loaded;
pulse generation means, coupled to said counter for initiating a pulse when said counter is loaded and for ending said pulse when said counter reaches a predetermined count, said pulse generation means coupled to said counter.

3. The apparatus defined by Claim 2 wherein said ending of said pulse occurs when said counter overflows.

4. The apparatus defined by Claim 3 including inte-gration means for integrating said pulses from said pulse generation means.

5. The apparatus defined by Claim 1 or 4 wherein said horizontal blanking occurs at a frequency of approximately 22,000Hz.

6. The apparatus defined by Claim 4 wherein said vertical blanking occurs at a frequency of approximately 60Hz and said horizontal blanking occurs at a frequency of approximately 22,000Hz.

7. The apparatus defined by Claim 1 including additional waveform means for converting data from said locations and accessed by said addressing means into a speed control signal for a disk drive.

8. In a computer system which includes a microprocessor and a random-access memory (RAM), and provides a video signal for a raster scanned display, an apparatus for generating an analog audio signal comprising:
a first counter for providing a digital count representative of said video signal timing for said display;
first address multiplexing means for coupling said digital count from said first counter as an address to said RAM at least during a portion of the horizontal blanking period of said video signal, said first address means coupled to said counter and RAM;
second address multiplexing means for coupling said digital count from said first counter as an address to said RAM during video display to access data stored in said RAM
and for coupling address signals from said microprocessor to said RAM at least during portions of the vertical blanking period to update said RAM;
waveform means converting data from said RAM
addressed during said horizontal blanking period by said first counter to said analog audio signal.

9. The apparatus defined by Claim 8 wherein said waveform means comprises;
a second counter into which said data is loaded from said RAM, said counter counting at a predetermined rate after said data is loaded;
pulse generation means coupled to said second counter for initiating a pulse when said second counter is loaded and for ending said pulse when said second counter reaches a predetermined count, said pulse generation means being coupled to second counter.

10. The apparatus defined by Claim 9 wherein ending of said pulse occurs when said second counter overflows.

11. The apparatus defined by Claim 10 including integration means for integrating said pulses from said pulse generation means.

12. The apparatus defined by Claims 8 or 11 wherein said horizontal blanking means occurs at a frequency of approxi-mately 22,000Hz.

13. The apparatus defined by Claim 11 wherein said vertical blanking occurs at a frequency of approximately 60Hz and said horizontal blanking occurs at a frequency of approximately 22,000Hz.

14. The apparatus defined by Claim 8 including an additional waveform means for converting data from said RAM, addressed during said horizontal blanking period by said first counter, to a speed control signal for a disk drive.

15. In a computer system which includes a microprocessor and a random-access memory (RAM) and provides a video signal for a raster scanned display, a method for generating an analog audio signal comprising the steps of:
accessing said RAM during horizontal blanking periods to obtain data signals representative of said audio signal;
converting said data signals into said audio signal;
updating said data signals representative of said audio signals during vertical blanking periods;
whereby said audio signal is provided without inter-ference with said video signal.

16. The method defined by Claim 15 wherein said micro-processor provides said data signals representative of said audio signal by:
(a) adding a predetermined number to a stored number;
(b) using the most significant bits of the sum as a location in a look-up table;
(c) storing the sum as said stored number of step(a);
(d) placing said data signals from said look-up table into said RAM, whereby the fundamental frequency of said audio frequency is a function of said predetermined number and the harmonic content of said audio signal is a function of the contents of said look-up table.

17. The method defined by Claim 16 wherein predetermined numbers are added to N stored numbers, and the resultant N sums are used as locations in N look-up tables; and where the most significant bits of the sum of data from said N look-up table provides said data signal representative of said audio signal.

18. In a computer system which includes a microprocessor and a random-access memory (RAM), and provides a video signal for a raster scanned display, an apparatus for generating a speed control signal for a disk drive comprising:
addressing means for directly accessing predetermined locations in said RAM when said video signal is in a horizontal blanking period and for permitting said microprocessor to write new data into said locations the said video signal is in a blanking period, said addressing means being coupled to said RAM;

waveform means for converting data from said locations and accessed by said addressing means to said speed control signal;
whereby said speed control signal is provided without interference with said video signal.

19. The apparatus defined by Claim 18 wherein said waveform means comprises:
a counter into which said data is loaded from said locations of said RAM, said counter counting at a predetermined rate after said data is loaded;
pulse generation means coupled to said counter for initiating a pulse when said counter begins counting and for ending said pulse when said counter reaches a predetermined count, said pulse generation means coupled to said counter.

20. The apparatus defined by Claim 19 including integration means for integrating said pulses from said pulse generation means.

21. The apparatus defined by Claim 18 wherein said computer system senses disk drive speed and varies said control signal as a function of said speed to provide dynamic calibration.

22. The apparatus defined by Claims 18 or 21 wherein said speed control signal is varied as a function of the track being accessed on a disk.

TABLE I

This code is executed every 16 sec at the vertical retrace interrupt. It computes the 370 values for the next sweep.

;loop once for half of the 370 values, summing the waveform values for each voice SoundLoop ;map voice 1 into D1 ;add voice 3 into D;
;add voice 4 into D1 ;update the DMA sound buffer with the new value ;loop for half the values ;now do the second half of the buffer ;OK, all done, Update sound table, restore registers and return to caller ;OK, now that we have everything set up, start the main loop to fill the buffer ;have we exhausted our request?
Routine: SetSpeed, SetASpeed Arguments: D6.W(input) -- track number speed should be set for Drive (input) -- current disk drive TrkSpeedTbl (in) -- speed code table for current drive Wait (output) -- 0, or SpdChgTime if CurSpeed changed registers other than A0-A2, D0-D2 are preserved Called By: (SetSpeed): Seek,RWPower (SetASpeed): MakeSpdTbl Function: This routine determines the correct speed value for Track and sets up the PWM memory buffer to produce the desired output. The value of Wait is set to SpdChgTime if the speed is changed. O
otherwise. The TrkSpeedTbl for the current drive is used. The drive enable is not changed, just the PWM buffer in memory.

SetASpeed is an alternate entry point which simply sets the pwm buffer according to a speed code in D2.

Set Speed BSR.S GetDrvl ; set up D1.A1 MOVE.W D6,D2 ; speed class is just track number LSR.W #4,D2 ; divided by 16 . . .
LSL.W #3,D2 ; adjust to double-longword word index ADD.W D1,D2 ; add drive specific offset MOVE.W TrkSpeedTbl (A1,D2),D2 ; get the speed we need ADD.W OffSpeed(A1,D1), 2 ; add in an adjustment (watch max,min) BSL.S @2 ; don't go below 0 MOVEQ #0,D2 @2 CMP.W #399,D2 BLE.S @3 MOVE.W #399,D2 ; don't go above 399 @3 MOVE.W PWNValue,D0 ; are we at that speed?
BPL.S @4 ; if speed is invalid, wait power-on time MOVE.W PwrOnTime(A1),D0 BRA.S @6 @4 SUB.W D2,D0 BEQ.S GetDrvl ; if so, just exit BPL.S @5 NEG.W D0 ; positive speed difference @5 LSL.W #5,D0 ; multlply by 32 to get speed settle time CMP.W SpdChgTime(Al),D0 ; minimum wait time for speed change BGT.S @6 MOVE.W SpdChgTime(A1),D) @6 ADD.W Wait(A1),D0 ; add in current wait time CMP.W PwrOnTime(A1),D0 BLT.S @7 MOVE.W PwrOnTime(Al),DO
@7 MOVE.W DO,Wait(Al) ;SetASpeed is an alternate entry point which simply sets up the speed code in D2 SetASpeed LoadPUMBuf SetSpdExit BRA GetDrv 1