FR2558629A1 - SOUND GENERATING AND DISC SPEED CONTROL APPARATUS FOR COMPUTER SYSTEMS - Google Patents

Abstract

THE INVENTION RELATES TO AN APPARATUS FOR GENERATING AN AUDIO SIGNAL AS WELL AS A SPEED CONTROL SIGNAL FOR A DISC UNIT IN A COMPUTER SYSTEM WHICH INCLUDES A MICROPROCESSOR 10 AND A MAS 11 SELECTIVE ACCESS MEMORY WHICH PROVIDES A VIDEO SIGNAL FOR A RECURRENT SCAN DISPLAY SCREEN. DIRECT ADDRESSING OF SPECIFIC MAS MEMORY LOCATIONS DURING PERIODS OF HORIZONTAL SUPPRESSION IS USED TO READ SOUND AND SPEED DATA WHICH ARE INTEGRATED TO PRODUCE CORRESPONDING ANALOGUE SIGNALS DURING PERIODS OF HORIZONTAL BLANK DELETION. THE SPEED CONTROL SIGNAL VARIES ACCORDING TO THE RADIUS OF THE TRACK.

Description

The present invention relates to a general apparatus

  sound generator, especially a device that is used

  with a computer system that includes a display device

  recurring scan plug and disc speed control apparatus. There are countless techniques well known for

  generate audio signals from digital signals.

  These techniques range from the most direct solutions following

  which digital signals are used to pro-

  from instantaneous amplitude of the audio signal to very complex vocoder techniques in which

  representative voice transfer functions are used

  As will be seen, the present invention converts a digital signal into an analog (audio) signal well

  that this conversion is only one aspect of the pre-

invention.

  Most often, computer systems, in particular

  link, relatively small systems (for example, or-

  personal diners) use display devices

  recurrent scanning (television type). The computer in-

  generate video information and save it to selective access memory (MAS). Synchronized counters

  with horizontal and vertical synchronization signals

  wedge address memory to provide data signals

  synchronized display data extracted from memory. These signals are converted to a video signal, for example, via a shift register. In some cases, the memory is organized in "dot mode" and the memory output signal is used directly to generate the video signal. In other cases, the memory output signal addresses a character generator which is

  scanned to provide video signals.

  There is a need for a significant amount of MAS data to generate a video display, in particular, in

  a dynamic graphic mode (which is not a text mode).

  In the field of home computers, and in the do-

  mainstream computers for small businesses in

  which microprocessors are used in combination with

  dynamic MAS, generating a video display using

  reads a relatively large amount of time from the processor and memory. It is thus difficult to produce an audio signal, in particular a complex audio signal, in a display mode.

  As will be seen, the present invention provides an app-

  similar for generating audio signals in combination with a microprocessor and random access memory at the same time

  time that video signals are generated. Signals

  dio are generated without interrupting either the video display or the operation of the computer and, importantly,

  by requiring only a minimum time of material and pro-

stopper.

  Typically, in flexible disk drives, a mechanism

  Any suitable mechanism is used to control the operation of the flexible disk drive motor at a constant speed. When the flexible disk drive is

  manufactured, some calibration steps are often used

  to ensure that the flexible disk drive rotates at a predetermined rotational speed. This requires, in addition to the calibration step, the use of relatively expensive speed control mechanisms. As we will see, next

  the present invention the computer is used to detect

  the speed of rotation of the disk drive, and then it

  produces a control signal to adjust the rotational speed

  tion of the disk drive. This eliminates the calibration of the prior art as well as the control mechanism

  speed of the prior art.

  It has been suggested in the prior art that better use of floppy disks and other disks could be obtained if uniform flux density transitions were used. This requires that the disc rotation speed be a function of the radius of the particular track being accessed. The present invention provides

such a characteristic.

  The subject of the present invention is an apparatus designed to be used with a computer system which comprises a microprocessor and a memory with selective access (MAS),

  in particular, in the case where a recursively scanning display

  rent is used with the computer system. Addressing means are used to directly access predetermined locations of the selective access memory, in particular, during the periods of deletion of the beam.

  during the horizontal return of the spot. Means of addressing-

  wise also allow the data contained in these same locations to be updated during periods

  deletion. The data stored in these locations

  cements are converted from digital form to an analog signal. A pulse begins when data from memory is loaded into a counter. The impulse is

  ends when the counter reaches an overshoot condition

  The resulting pulses are integrated

to produce the audio signal.

  The processor generates data signals for random access memory for a single tone by adding a predetermined number to a number stored in memory. The most significant bits of this sum identify a location

  in a look-up table and the data signal (nu-

  result) is then stored in memory

  selective access moire. The predetermined number is added by

  repeatedly to the number stored to produce each

  none of the data signals for the random access memory.

  For more complex tones, a number of predetermined numbers and numbers stored in memory are used

  with several consultation tables.

  The present invention also relates to an apparatus for

  reil to control the speed of rotation of a disc. Addressing means used in combination with the device

  sound generator are used as part of the app

same disc control.

  Other characteristics of the invention will appear

  on reading the description which follows and examining

  of the accompanying drawings in which: FIG. 1 is a block diagram of the computer system,

  this view representing the multiplexing of the addresses used

  read in combination with the present invention;

  Fig. 2 is a timing diagram used for

  write the times at which the digital signals representative of sounds are accessed in the MAS memory and the times at which they are updated in the MAS memory; Fig. 3 is a block diagram of a counter used to generate the audio signals; Fig. 4 represents the waveforms generated by the counter of FIG. 3; Fig. 5 is a flow chart used to describe the process by which the data signals are produced; Fig. 6 is a combined block diagram and electrical diagram of the circuit for producing the audio signal and the sound power control; Fig. 7 is a flowchart showing the method by which data signals are produced for four tones; Fig. 8 is a flowchart showing the method by which data signals are generated for an "unharmonic" audio signal

  Fig. 9 is a block diagram representing the interconnections

  general connections between the computer, in Figure 1 and a disk drive engine; Fig. 10 is a block diagram showing part of the circuit used to generate the speed signal for the disk drive; and Fig. 11 is a block diagram representing an additional part of the circuit used to generate the signal

  speed control for the disk drive.

  Figure 12 is a graph for describing one of the

aspects of the present invention.

  An apparatus designed to generate

  audio signals in combination with a computer system

  in particular, a system which generates signals for a recurrent scanning display device and for generating a motor speed control signal. In

  the description which follows, many specific details

  are listed, such as specific frequencies, number of lines, part numbers of commercially available devices, etc. to allow a full understanding of

  the invention. However, it will clearly appear to the specs

  technical specialists that one can implement the

  present invention without using these specific details.

  In other cases, well-known circuits have been shown in the form of block diagrams so as not to obscure the

present invention.

  In the following description, the term "audio" and

  the expressions "sound data signal" or "data so-

  ours "are used to identify a digital signal

  which is converted into an analog (audio) signal.

  "motor speed control" refers to the control of the speed of rotation of a motor or driven disc

by the engine.

  General architecture The present invention is currently being implemented as part of a computer system (personal computer

  or small business computer) that uses a mid

  croprocessor with part number 68000. The address lines and the data lines for this microprocessor are shown in Figure 1. The other well known lines coupled to this processor are not shown in Figure 1. The microprocessor 10 is coupled to a selective access memory (MAS) 11 comprising sixteen "chips"

  64K dynamic memory. Data lines 0-15 in-

  connect the microprocessor 10 and the MAS memory 11 to allow data to flow from the processor to the MAS memory. The data from the MAS memory is transmitted to the processor via the

  MAS data buffer 13; the data is also

  Lely transmitted from the MAS memory 11 to a unit 27 for controlling the speed of the drive motor of the

  disk, to a video shift register 28 and to comp-

  teurs 29 of sounds. These counters will be described in detail with reference to FIG. 3. The microprocessor also receives data from the read only memory (MEMOR) 17 when the latter is put into operation (by the signal ROMEN). Likewise, the data is transferred by and to the disc control unit 18 when the disc control unit 18 is put into operation by a signal transmitted on line 35. This if

  general as well as the ROMEN signal is generated by the

  logical buckets of program table (RLTP) or "PALS" 23. Data

  are also transmitted to the microprocessor 10 and by the mid

  croprocessor 10 to a sequential communication controller

  tiel 14 and an interface adapter 15 (commercially available under part number 8530 and under

part number 6522).

  The addresses transmitted by the microprocessor 10 are trans-

  stored in memory MEMOR 17, in RLTP logical networks 23 and in an address multiplexer in MAS memory, designated by

  the reference 20. Some of the address signals, such as indi-

  are also transmitted to the disk control unit 18, to the sequential communication controller 14 and to

the interface adapter 15.

  The address memory multiplexer 20 of the MAS memory allows addressing of the MAS memory either by the microprocessor or directly by the account stored in the video counter 22. During the time when the video signal "draws" the image d screen, the multiplexer 20 chooses the video counter 22, thus allowing the counter to address

  MAS 11 directly. The second multiplexer of a-

  dresses 21, as well as the multiplexer 20, is controlled by a signal sent by the RLTP logic networks 23. During the last part of the beam suppression signal during

  the horizontal return of the spot, as described in detail

  referring to Fig. 2, the multiplexer 21 chooses the 7 bits

  left or most significant of the counter 22 and sets automatic-

  memory at this address. This requires that the sound and speed data of the disc be stored in dedicated and consecutive locations in the MAS memory and allows easier access by the microprocessor when

  this data is updated. A bistable rocker, not re-

  presented, provides an additional input bit for

  address lines of the multiplexer 21 in order to cause the ac-

  direct access to a second page of sound data contained in

MAS memory.

  The video counter 22, which is made up of two elements designated by part numbers 74LS 393, provides a digital video account which corresponds to the position of the beam on a recurrent scanning display device and accounts

  additional for the return periods of the horizon spot-

  tal and vertical (beam suppression periods). The clock signals which operate this counter as well as the reset signals are generated by the program table logic networks (RLTP) 23. RLTP networks

  23 are made up of three lo-

  program chart gic. They receive the bone signal

  16 MHz cillator controlled by quartz from an oscillator 31.

  The RLTP networks 23 generate, from this signal, the usual signals for the memory, such as the RAS signals,

  CAS and clock and synchronization signals well

  used by the microprocessor. They also provide

  the horizontal synchronization signal (HSYNC) and the vertical synchronization signal (VSYNC). These signals

  are transmitted to the display device on lines 32.

  Other clock signals used throughout the memory, such as an 8 MHz clock signal used by the counters of FIG. 3 and the clock signal used

  by the drive motor speed control unit

  of the disk are generated by RLTP networks 23.

  Two 32Kx8 MEMOR 17 read only memories are used in the currently preferred embodiment. They

  provide the memory space necessary for the functions

  diagnostic, initialization and other functions

  which are not within the scope of the present invention.

  Disk control unit 18 provides an interface

with a flexible disk drive.

  The adapter 15 communicates with the keyboard 24. A mouse 25 provides input and switching information

  cursor to both controller 14 and adapter 15.

  A power control button is drawn on the image

  graphic screen and is mouse controlled to pro-

  deduct three bits of binary data on lines 37.

  As will be described with reference to FIG. 6, these three

  bits are used for a static sound power control

audio signal tick.

  Video synchronization In the currently preferred embodiment, horizontal scanning is performed at a frequency of

  22,256.84398 Hz. Vertical scanning occurs at a frequency

  quence of 60 Hz. Each frame has 370 lines of bass

  layering and there are 704 pixels or points per horizon scan-

  tal. This corresponds to 44 words of sixteen bits of memory

  MAS 11. Thus, the main clock frequency of the oscillator-

  player 31 indicated as being 16 MHz is more precise-

15.6672 MHz.

  As shown in Fig. 2 to which we refer

  ra, on the actual display screen, there are 512 "active" pixels in the horizontal direction and 342 lines. The remaining 192 bits of each horizontal scan constitute the horizontal blanking period, sometimes called "spot return" time. It is during this period of time that the beam current of a cathode ray tube

  is lowered and the beam is brought back to one side of the beam

  notch to another. In the vertical direction, in addition to 342

  lines displayed on the screen, there are 28 additional periods

  during which vertical suppression occurs

  wedge, i.e. the beam current is again reduced and the beam returns from the bottom

  from the screen to the top of the screen.

  In Fig. 2, time is shown, from left to

  right, for example by line 39 in broken lines.

  During the first scan, after 512 bits have been displayed

  the time represented by line 40 is reached and

  beam deletion occurs. During the deletion

  beam, there is no need for MAS to provide data for display. Before time

  , as can be seen in Fig. 1 to which we refer

  will count, the account of the counter 22 accesses the memory MAS 11

  by means of the address multiplexer 20 of the

  moire MAS. This occurs for each display line. (Counter 22 maintains both a horizontal account

  and a vertical account). The counters are not incremented

  tees in the normal direction during the horizontal blanking period. Instead, four bits of the video counter are reused for counting during this period. This eliminates the intervals between addresses for the data of

  his. When time 40 is reached for each line of ba

  layout, a clock signal transmitted by the RLTP networks 23 controls the multiplexer 20 so that it accepts addresses transmitted by the microprocessor 10. During the next 192 pulses of the 16 MHz clock, except for the

  last pulse, the microprocessor can freely access

  der to MAS memory and thus perform independent tasks

  display dantes. When the last pulse of each scan line is reached, a signal sent by the RLTP logic networks 23 has the effect that the counter 22 directly accesses the memory 11 via the

  multiplexer 21. At this time, the sixteen-bit word of the me-

  moire MAS 11 (time 41 of Fig. 2) is extracted from the meta-

  moire, 8 bits being transmitted to the vi control unit 27

  disk drive motor size and 8 bits being trans-

  put on the sound meters 29 (as we will see, the unit 27 of

  speed of the drive motor uses only six of these bits) .During "screen time" shown on

  in Fig. 2, the sixteen bit words of the memory are placed -

  in the video shift register 28 and are used to

  provide the video signal. RLTP 23 networks, as mentioned-

  born, provide, on line 32,1st synchronization signal

  horizontal tion and vertical synchronization signal

  used in combination with the shift register signal

  lage 28 to control the video display.

  When the 342 & me scan line is reached (re-

  presented by line 43) and at time 40 of this line, the multiplexer 20 again allows the microprocessor 10 to access the memory MAS 11. However, at the end of line 43 and during the remaining period of vertical suppression , the multiplexer 21 again applies 9 address bits to the memory MAS 11 at time 41 to allow the 16-bit word to be applied to the control unit 27

  speed and meters 29. (Lines RA0 to RA6 are multiple

  time -lexed to provide these address signals).

  During vertical suppression, the microprocessor 10 can access the MAS memory 11 except for the last clock pulse of each line. It was during this period of

  time as, as will be described below, the data decom-

  disc motor speed demand and sound data

  stored in memory MAS 11 are updated.

  Multiplexer 21 with its nine-bit address defi-

  nit contiguous memory locations thus allowing

  engine sound and speed data to be easier

  Lely accessed and updated by processor 10. We no-

  will be that the memory location in MAS 11

  for sound and speed control data is different

  rent from the location of the screen data.

  In the currently used embodiment,

  During the "active" video period, the microprocessor and video display signal transfers use the time-shared data bus in alternating cycles. during

  horizontal deletion (for words 32 to 42), mid

  croprocessor has only access to the data bus. At time 41 of FIG. 2 (43rd word), the microprocessor and the sound / speed data transfer share the data bus in alternating cycles. Microprocessor could update data

  sound and speed control data during shifting

  active video. In practice, however, this data is

  updated during beam suppression periods.

  In the currently constructed and preferred embodiment

  d, the vertical synchronization signal (return signal from the vertical spot) triggers the updating of the

  his. Using this signal and updating the locations

  already accessed (for example by starting at the location used on line 39 at time 41), the update does not interfere with the playback of sound data. The program of

  software ensures that the update stays ahead of time

  port for reading sound data. If the microprocessor updates the deson data without being synchronized with the display, the data could be overwritten before being used. In addition, this arrangement frees the software from the need to be synchronized with the sound to put

update the data.

  Generation of audio signals The eight bits of sound data representing the audio signal are shifted in parallel in two four-bit counters, 46 and 47, which have been shown in FIG. 3. These

  counters are commercially available items (part number 161).

  The meters receive the 8 MHz clock signal which is transmitted to them on line 48. The counting continues

  in these counters until an overshoot occurs

  capacity which is detected on a line 49. Thus, if a number containing only zeros has been loaded into

  the counters, a longer time must elapse before the

  capacity overflow (approximately 32 aces) while an overflow may occur from the first cycle of the 8 MHz clock if a number comprising only 1

is loaded into the counter.

  The audio waveform is produced by first generating pulses, each of which has a width which is a function of the time which elapses between the loading of the eight

  bits in counters 46 and 47 and overflow.

  For example, as shown in FIG. 4, the leading edge 52 of a pulse occurs when loading the sound data into the counters. If a number with only

  zeros is loaded, overflow occurs approxi-

  ron 32 as later and the pulse ends as indicated by the trailing edge 54. A pulse is generated during each horizontal scan since a sound word of

  eight bits are loaded into the counters with each scan.

  As a result, the pulses are generated at a frequency

* approximately 22,000 Hz and, entheory, this provides

  nit a bandwidth of about 11,000 Hz. In Fig. 4, a second pulse 56 has been shown which has a width

  greatly reduced. This, of course, occurs when

  that a larger number is loaded into the counters 46

  and 47. Pulse 57, which is depicted as occurring

  health during the third sweep, at a falling width

  between the first and second pulses.

  The pulses are integrated by a computer integrator

  nary to produce the analog signal. The integrator 60 of FIG. 6 receives a loading signal and signal

  overflow. Waveform 61 represents the in-

  resulting integration of the pulses represented on the

Fig. 4.

  The three information bits (bits 37a, 37b and 37c) of the interface adapter 55 are used to allow

  a user to statically recommend the sound power.

  Amplifiers 63, 64 and 65 are turned on or off to control the output amplitude

on line 68.

  Calculation of sound data signals

  The sound data extracted from the memory, which

  sound waveforms, are calculated by mid

  croprocessor 10. More specifically, they are generated "by software" inside the microprocessor. We can use an advanced language, such as Pascal, to allow

  to a user to more easily implement the

  ganigrams which are described below. In general, the data

  sound are produced extremely quickly given

  born that the processor takes advantage of the added capacity

68,000 microprocessor pide.

  Referring to FIG. 5, it will be assumed that a single "pure" tone must be generated. First, a table

  is stored in the system memory

  teme; in the currently preferred embodiment, the look-up table has 256 × 8 bits. Thus, for each eight bit address applied to the table, an eight bit output signal is produced. For a pure tone, the consultation table contains points corresponding to a wave

  sinusoidal. This is shown for the look-up table.

  tion 70 of FIG. 5. The generation process of the a-

  stands for the next value in the table is to addi-

  repeatedly specify a predetermined number represented in rectangle 74 as t 00 to a number stored in a register 72. Initially, the 32-bit word contained in the register 73 may have a value

  any, for example, contain only zeros. The incred-

  ment A00y is added. The resulting sum is reloaded into register 72. The eight most significant bits are extracted from the sum, as indicated in rectangle 76,

  and used as the address for the look-up table 70. Suppose, for purposes of illustration, that t 00 is small. The bits

  more significant do not change each time this relatively small binary number is added to the

  number recorded in register 72 but it is necessary, at the

  milk, many additions to make them change. By

  Therefore, each of the 256 locations in the table

  sultation is addressed multiple times and the eight-bit lookup table data that is stored

  in the MAS 11 memory vary slowly. This, natural-

  ment corresponds to a low frequency. If, on the other hand, the

  incredibly. 0, is relatively large, the lookup table results change more quickly, and so

  for example, all eight-bit data words consecutively

  tifs extracted from the consultation table 70 can be

  different. This corresponds to a high frequency. A new

  the eight word bit sound data word is obtained with each addition represented by rectangle 74. Therefore,

  by modifying the increment added to each cycle, we do

  laugh the frequency of the tone. All the sound data used during each frame can be easily calculated in a few periods of scan line of the period of

vertical removal.

  To obtain envelope control or amplitude modulation, a series of tables can be used. Each table, for example, in a series of tables 0-7 contains a sine wave with a maximum peak-to-peak value

  of 2n'de table By letting flow a certain number of-

  weft tervalles between the passage from one table to another

  you can order the envelope.

  As shown in Fig. 7, in the embodiment

  currently preferred, up to four tables

  sultation of 256x8 can be used by micropro-

  stopper 10. In addition, the content of each consultation table

  tation can be programmed by user and content

  of each table may be different from that of the others.

  For example, the look-up table 80 of FIG. 7 is shown as containing a sine wave, the table 81 as containing a triangular wave, the table 82 as containing a square wave and the table 83 as containing a ramp. However, in this case (in which four tones

  are generated) 24 bits are used instead of 32.

  (This is represented by block 85 in Fig. 7). In this case also, an increment designated A01 is added to the

  previous sum (rectangle 86). The most significant bits

  catives are extracted from the sum and are used as the address for the corresponding eight-bit word from table 80. The same process is repeated with regard to the number

  represented in rectangle 87, to which an increment A02 (dif-

  or identical) is added, as indicated in the rec-

  tangle 88, the most significant bits of the sum being, again, used to address the lookup table

  81. Likewise, values and increments stored in different memory

  are generated to allow the consultation of tables 82 and 83. The eight resulting bits of each of the tables are added, as indicated by the rectangles 89, 90 and 91, and the eight most significant bits are t8629 extracted from this sum, as indicated in rectangle 92 and stored in memory 11. This process is repeated for each of the data words stored in memory in MAS 11 when four tones are generated. In this case also, the fundamental frequency of each of the four tones is de-

  terminated by the increment that is added, such as that indicated

  as in rectangles 86 and 88, and the residue is determined

  by the "form" stored in the look-up table.

  Table I appended hereto is a program written in the 68,000 microprocessor assembly language for

  implement the flow diagram of FIG. 7.

  With the tone generator described above, excellent tone control is obtained, a "frequency control" with up to 24 bits can be used

  (for each tone) in the 11 kHz band. This allows

  gendering in the band almost 17 million different tones, which is approximately equal to (or greater) than the most

  great capacity of perception of the human ear.

  The processes described above are more specific-

  suitable for providing periodic functions which are harmonic in nature and produce a tonal quality representing music or the like. For sounds, such

  that voice, you can use a consultancy buffer

  enlarged to initially store a waveform that represents, for example, speech. This memory is represented by the buffer memory 93 in FIG. 8. The buffer may actually be contained in

  MAS 11 memory and it must be for practical reasons.

  ticks if a long waveform is to be stored.

  The eight-bit values are again obtained by adding a certain increment t 00 represented in rectangle 95 to a 32-bit word recorded in a register 96, the bits

  the most significant of the sum being used to address

  ser buffer locations 93. The results of viewing the enlarged buffer are saved

  memory and selected during the deletion period

  horizontal position, as in Figs. 5 and 7.

  The attached table 2 contains a program written in the assembly language of the 68,000 microprocessor for putting

  the flow diagram of FIG. 8.

  Disc drive motor speed control unit Generally, floppy disc drives and other disc drives include a mechanism for driving the disc to

  a predetermined constant speed of rotation (speed).

  When manufacturing the disk drive, the speed control mechanism is calibrated to ensure that the data

  will be recorded and played back at a certain rate.

  According to the present invention, the motor speed is

  controlled by a computer and, in addition, the speed of the mo-

  tor is modified according to the track which is accessed so as to obtain uniform flux densities. In other words, the engine runs slower when the outer tracks are used (the radius is larger) and faster when the inner tracks are used (the

radius is smaller).

  In Fig. 9 the computer of FIG. 1 has been represented

  tee as computer 97. A disk drive, such as a flexible disk drive and, in particular, the disk drive motor 98 have been shown. Line 99 transmits pulses to computer 97 which indicate the speed of the motor. In the presently preferred embodiment, the standard indexing pulses of the motor are used. The flexible disk drives used are keyed to the motor shaft and, therefore, no

  skating. Therefore, the indexing pulses themselves

  same represent the effective rotation speed of the flexible disk. If slippage is possible, you can use the bit marks or streams of the disc itself to get an accurate indication of the speed of the disc. The speed control signal transmitted on line 100 controls the speed of the motor. A predetermined signal level is

  used on line 100 and the motor speed is detected

  ted on line 99. This allows computer 97 to record

  record the characteristics of the engine 98. In other words, the computer knows, for each engine which

  is connected, the speed of rotation of the motor for a

  general speed control. In this way, it is not necessary to calibrate the motor 98 of the disk drive and, moreover, the speed control mechanism.

  normally used in the disk drive is not required

  because the speed control is carried out by the computer. As is clear from FIG. 9, closed loop operation occurs, since the computer 97 detects the effective speed of the motor

using line 99.

  In the embodiment currently used, the

  computer 97 examines pulses 99 and determines the ca-

  characteristics of engine 98 when a new disc is placed

  c in the disk drive, before data is written to it, or if read or write errors have occurred. Obviously we could use other

  arrangements, for example, the indexing pulses for-

  should be checked periodically or even continuously-

is lying.

  In the currently preferred embodiment, the mo-

  The engine operates at a speed ranging from 350 rpm, for the innermost track, up to 700 rpm, for the outermost track. It is obvious that the range of rotational speeds chosen will depend on the radius of the disc and will vary according to the particular magnetic characteristics of the

system and disc format.

  As previously mentioned, during each horizontal blanking period, 8 bits of data are transmitted

  to the sound counters 29 of FIG. 1 and 8 bits are applied

  than the speed control unit 27. In the embodiment currently in use, only six of the bits of this bus are used for speed control. This bus is represented as being a bus 109 in FIG. 10 and these six bus lines are shown as being coupled to the six stages of a shift register 102. The six bits of bus 108 are loaded into the six stages of register 102 when

  the sound data signals are loaded into the comp-

sound tutors 29.

  Fig. 10 represents a polynomial counter. Data placed in the six stages of the shift register

  102 are shifted under the control of a clock signal.

  The effective offset speed is approximately 1 MHz. Due to the various wait states that occur in the shift register the 8 MHz clock signal is actually applied to the register. The output signal of the last stage of the register is transmitted to an input terminal of an exclusive OR gate 104 by a line 103. The signal of

  output of the first stage is transmitted to the other terminal

  entrance of door 104 by a line 105. This arrangement has

  on counting in the "polynomial generator" of a ma-

  known in the prior art. The floors of the re-

  shift register 102 are also coupled to a detector

  106. This detector determines when a dual state

  predetermined number is reached in the shift register.

  When this state is reached, a signal is applied on line 109 to stop the shift of the shift register

  102; this signal is used to generate the end of an im-

  drive in the same way as that used for the signal

of his.

  Referring to FIG. 11, the counting begins in the shift register 102 of FIG. 10 at the start of each

  horizontal scanning. At this time, the front edge of an im-

  pulse is generated such that the front 115 of the pulse shown in FIG. 12. When the status detector 106

  detects the predetermined state, the end of the pulse is generated

  drée, as represented by the rear edge 116 of FIG. 12.

  The pulses are integrated by the integrator 114 and the resulting signal on line 100 is used to control

  the engine speed in the usual way.

  The 6 bits placed in the shift register 102 have-

  always dye the state detected by the detector 106 before the end of each horizontal scan. In practice, the state will be detected during the first 40 microseconds of the 44

  as approximately required for each horizon scan-

  tal. Ten horizontal scans are used for each speed control setting. This number is chosen being

  since the presently preferred embodiment uses

  reads 370 scan lines in total divisible into ten parts

  equal ties. However, a pulse is generated for each horizontal scan. (The time constant associated with the integrator 114 of Fig. 11 is sufficiently long

  so that a continuous signal is produced on line 100).

  The pulse width generated for each of the 10 scans used to define each speed control value "fluctuates" to provide precise values. For example, suppose that a value corresponding to 6.5 is required on line 100. Referring to Fig. 12, for the ten scans used to set this value, the first

  will have the value 6, the second the value 7, the third will

  their 6 and so on for the ten scans. This has the effect of varying the trailing edge between the values 6

  and 7. After being integrated, however, the trans-

  bet on line 100 corresponds to 6.5. By distributing the

  values and allowing fluctuation of pulses during

  in the 10 scans used to define each number of

  speed control, you get a very precise command.

  We obtain a precision of the command greater than

  that allowed by the 6 bits loaded in the register at

  wedging. In the present embodiment, 400 are obtained.

separate levels or log (400) bits.

  log (2) Table 3 in the appendix is the program used for speed control written in the assembly language of the

68D00 microprocessor.

  Thus an improved apparatus has been described which allows both the generation of sounds and the control of speed.

  of the motor of a flexible disk drive or the like.

TABLE I

  This code is executed every 16 seconds during the

  terruption back from the vertical spot. It calculates the 370

values for the next scan.

  MOVEM.L (A6), D2-D7 / A0-A5; load sound parameters in the MOVE.L registers Sound base, A6; pointerlamemoire-tampon ADD.W '370, A6; in fact, point the middle of; the MOVE.L buffer 4 $ 00FF0000, D1; put mask in the left part of D1 MOVE # 2, - (SP); trigger loop counter; exterior MOVE # 185, - (SP); cycle through the loop 185 times (half the buffer) cycle through the loop once for half of the 370 values; adding the waveform values for each Voice SoundLoop CLR.W D1; erase the contents of the addition register (but not the mask) ADD.L D2, D3; calculate voice 1 ADD. L D4, D5; calculate voice 2 ADD.L D6, D7; calculate voice 3 ADD.L A0, A1; calculate voice 4 map voice 1 in D1

MOVE.L D5, D0

  AND.L D1, D0; eliminate with the mask all the bits except the left bits SWAP DO; use bits 16-23 MOVE.B 0 (A3, D0), D0; consult the waveform table ADD.W D0, D1; add the obtained value add voice 3 to D1

MOVE.L D7, DO

  AND.L D1, D0; eliminate with the mask all; bits except the left bits SWAP D0; use bits 16-23 MOVE.B 0 (A4, D0), D0; consult the waveform table ADD.W D0, D1; add the value obtained add voice 4 to Dl

MOVE.L A1, D0

  AND.L D1, D0; using the mask, eliminate all the bits except the bits: on the left SWAP DO; use bits 16-23 MOVE.B 0 (A5, D0) D0; consult the shape table; wave ADD.W D0, D1; add the value obtained update the direct access sound buffer by loading the new value LSR.W # 2, D1; divide by 4 (use the most significant bits) MOVE.B D1, (A6); load the result in the buffer

  ADDQ 42, A6; advance memory pointer-

  buffer browse the loop for half the values SUBQ # 1, (SP); decrement BNE.S sound loop counter; run the loop until; the end now load the second half of the MOVE.L sound base, A6; point the start of the; MOVE # 185 buffer, (SP); reset the counter to 0 SUBQ # 1,2 (SP); decrement the second BNE.S sound loop counter; browse the loop until the end OK, everything is finished, update the sound table, restore the registers and return to the program calling ADDQ 44, SP; exit loop counter MOVE.L Pointeurson, A6; get address of tables

ADDQ # 2, A6

  MOVEM.L D2-D7 / A0-A1, (A6); save the MOVEM.L (SP) +, D0-D7 / A0-A6 sound registers; restore calling program records

TABLE 2

  MOVE.L Sound base, A2; get address of ADD.W A64, A2 sound base; start 32 LEA 676 (A2), A4 bytes; calculate the end address CLR.W (SP); indicator goes 1 MOVE 9337, D2; 338 bytes for movement in 1st half OK, now everything is ready, start first loop to fill the buffer

  MOVE.B (A1), (A2); move it into memory-

  ; ADDQ 92, A2 direct access buffer; advance to the next location ADD.L D1, D3; increment SWAP D3 cumulative index; pass left side; right ADD.W D3, A1; advance (possibly) to the next entry ADD.W D3, D0; cumulative summons made CLR.W D3; reset whole SWAP D3 part; restore D3 has the request been satisfied? CMP.L A1, A3; end of buffer; crossed? DBLE D2, Interpolate; if so stop

TABLE 3

  Routine: SetSpeed (Set speed) SetASpeed (Set; speed A): Arguments: D6.W (input) - the speed of the number; track should be fixed; Drive (drive) (drive) - Drive -; with disc in operation; TrkSpeed (Track speed table)

  ; (in function) - Table of vi codes

  ; size per unit in operation; WAIT (Exit) - O or SpdChgTime

  (gear change time if Cur--

Speed has changed.

  Registers other than A0-A2, D0-D2 are preserved Called by: (SetSpeed); Seek (research), RWPower; (Supply Read / Enter) (SetASpeed): MakespdTbl (Establish table; speeds)

  Function: This routine determines the value of vi-

  correct size for the track and; loads the modulation buffer; pulse duration (PWM) for it; produce the desired output signal. The ; wait value (WAIT) is set to

  ; SpdChgTime if the speed is changed.

  ; Otherwise, it is equal to 0. The table; TrkSpeedTbl for unit in operation

  ; is used. The activation of the

  ; nity is not changed, only the mete

  ; pulse modulation buffer; in duration (PWM) contained in the memory

; main.

  ; ; SetASpeed is another entry point that simply loads it into the buffer; PWM a speed code contained in the

; register D2.

  Set Speed BSR.5 GetDrvl; prepare D1.A1 MOVE.W D6, D2; the gear category is just the track number LSR.W e4, D2; divided by 16 ... LSL.W # 3, D2; adjust to double length word index ADD.W D1, D2; add specific offset of the unit MOVE.W TrkSpeedTbl (A1, D2), D2; get the speed you need ADD.W OffSpeed (A1, D1), 2; add an adjustment (monitor: max, min) BSL.S (Y2; do not go below 0

MOVEQ # 0, D2

C2 CMP.W, D2

BLE.S 3

  MOVE.W # 399, D2; do not go above 399 @ 3 MOVE.W PWMValue, D0; are we at this speed? BPL.S @ 4; if the speed is invalid, wait for power up time MOVE.W PwrOnTime (A1), DO

BRA.S @ 6

@ 4 SUB.W D2, D0

  BEQoS GetDrvl; in this case, simply exit

BPL.S @ 5

  NEG.W D0; positive speed difference LSL.W # 5, D0; multiply by 32 to stabilize the time speed CMP.W SpdChgTime (A1), D0; minimum waiting time for gear change

BGT.S 6

MOVE.W SpdChgTime

(A1), D0

  @ 6 ADD.W Wait (A1), D0; add current waiting time CMP.W PwrOnTime (Ai), D0

BLT.S 7

  MOVE.W PwrOnTime (A1), D0 7 MOVE.W D0, Wait (A1) SetASpeed (speed setting A) is another entry point which simply sets the speed code contained in the D2 register SetASpeed MOVE.W D2, PWMValue; note the speed so that you can refer to it then MOVE.L D3-D6 / A2, - (SP); preserve A2-A7, D3-D7 SUB.W # 399, D2; reverse (for sony)

NEG.W D2

EXT.L D2; make a long one ...

  DIVU # 10, D2; stay in the left word

MOVEQ 411, D0

  @ 1 MOVE.B D0, D1; main speed value MOVE.B D0, D3; save bit 0

LSR.B # 1, D0

EOR.B D0, D3

  LSR.B # 1, D3; new bit 5 -, carry over

BCC.S @ 2

BSET # 5, D0

DBRA D2, @ 1

  SWAP D2; the rest determines the fluctua-

  tion MOVE.B DitherTbl (D2), D5; 10 bits are needed for the fluctuation table

ASL # 8, D5

  MOVE.B DitherTbl +1 (D2), D5; get 2 bits of the following LoadPWMBuf (load pulse duration modulation buffer) MOVEQ> 36, D3; large loop covered 37 times LEA PMWBuffer, A0; load the PWM buffer memory (37x10 = 370 bytes)

  MOVE.L PWMBuf2, A2; in the case of a second me-

  buffer memory I1 MOVE.Q # 9, D2; inner loop traversed 10 times MOVE.W D5, D4; fluctuation pattern

  @ 2 LSL.W 41, D4; carry bit = 1 means use

ser higher value

BCC.S @ 3

  MOVE.B D0, D6; use higher value BRA.S a4 @ 3 MOVE.B D1, D6; use main value

@ 4 MOVE.B D6, (A2)

  ADDQ # 2, A0; every second byte is an in-

sound formation

ADDQ # 2, A2

DBRAP. D2, 2

* DBRA D3, @ 1

  MOVEM.L (SP) +, D3-D6 / A2; observe the rescue agreements

  check registers SetSpdExit (output from speed setting) BRA GetDrw 1

  DitherTbl (fluctuation table); used to fluc-

  ; kill speed values equally Byte $ 00, $ 20, $ 21, $ 24, $ 94 Byte $ AA, $ B5, $ B7, $ 7B, $ FF, $ 40, $ 00

Claims (17)

CLAIMS i - An apparatus for generating an audio signal forming part of a computer system which comprises a microprocessor (10) and a selective access memory (MAS) (11) and which produces a video signal for a recurring scan display device, this apparatus being characterized in that it comprises: addressing means (21) for directly addressing predetermined locations of the selective access memory (11) when the video signal is in a horizontal blanking period and to allow the microprocessor to write new data to said locations when said video signal is in a blanking period, said addressing means being coupled to the random access memory; waveform generating means for converting data from said locations and accessed by the addressing means into analog audio signals, so that the audio signal is efficiently produced from the computer system.   2 - Apparatus according to claim 1, characterized in that   the waveform generating means include: a com-   counter (29) into which said data is loaded from said locations in the random access memory, said counter counting at a predetermined frequency after   the data has been loaded; means generating impulse   sions coupled to the counter to start a pulse when   the counter is loaded and to complete the pulse when   that the counter reaches a predetermined count, the means   pulse generators being coupled to the counter.   3 - Apparatus according to claim 2, characterized in that   the end of the pulse occurs when the capacity of the comp- is exceeded.   4 - Apparatus according to claim 3, characterized in that it comprises integrating means (60) for integrating   the pulses of the pulse generating means.   5 - Apparatus according to one of claims 1 and 4, character-   laughed at in that horizontal deletion occurs at a   frequency of approximately 22,000 Hz.   6 - Apparatus according to claim 5, characterized in that   vertical suppression occurs at a frequency of approximately matively 60 Hz.   7 - Apparatus according to claim 1, characterized in that it comprises means generating additional waveforms for converting data extracted from said locations and accessed by the addressing means into a   speed control signal for a disk drive.   8 - A device for generating an audio signal forming part of   part of a computer system that includes a microprocessor   seur (10) and a selective access memory (MAS) (11) and which produces a video signal for a recurrent scanning display device, this apparatus being characterized in that it comprises a first counter (22) for producing a   digital account representative of the synchronization of the   general video for said display device; first address multiplexing means (21) for coupling the digital account produced by the first counter as an address of the random access memory at least during part of the horizontal blanking period, said   first addressing means (21) being coupled to said account   and to said selective access memory; second address multiplexing means (20) for transmitting said account   digital audit first counter as address of the-   said selective access memory during the periods during which said video signal provides information for presentation on the display device and   to transmit address signals from a micro-   memory processor with random access at least during parts of the vertical blanking period; of   waveform generating means for converting data   from the selective access memory addressed during the   horizontal deletion period by the first counter (22) into an analog audio signal.   9 - Apparatus according to claim 8, characterized in that the waveform generating means comprise: a second counter (29; 46, 47) in which are loaded the data coming from the selective access memory, said counter comprising at a predetermined frequency after   the data has been loaded there; means generating im-   pulses coupled to the second counter to start a pulse   when the second counter is loaded and finally   the impulse when the second counter reaches a pre-   determined, said pulse generating means being coupled to the second counter.   - Apparatus according to claim 9, characterized in that the end of the pulse occurs when the capacity of the second counter is exceeded.   11 - Apparatus according to claim 11, characterized in that it comprises integrating means (60) for integrating   the pulses of the pulse generating means.   12 - Apparatus according to one of claims 8 and 10, charac-   terized in that horizontal deletion occurs at a frequency of around 22,000 Hz.   13 - Apparatus according to claim 12, characterized in that the vertical suppression occurs at a frequency approximately 60 Hz.   14 - Apparatus according to claim 8, characterized in that it comprises means for generating additional waveforms for converting data extracted from the memory with selective access during the horizontal blanking period by the first counter (22) into a signal from   speed control for a disk drive.   - Method for generating an analog audio signal in a computer system which comprises a microprocessor (10) and a selective access memory (11) and supplies a video signal for a recurring scanning display device, this method being characterized in what it consists of accessing the selective access memory (11) during the horizontal blanking periods in order to obtain data signals representative of the audio signal; converting the data signals to said audio signal; to update the signals   data representative of the audio signal during   vertical suppression riodes; so the audio signal   is produced without interference with the video signal.   16 - Method according to claim 15, characterized in that the microprocessor (10) supplies data signals representative of the audio signal: (a) by adding a predetermined number to a number stored in memory; (b) using the most significant bits of the sum as an address of a look-up table (70; , 81, 82, 83);   (c) storing the sum in memory as a number stored in step (a); and (d) placing the lookup table data signals in the random access memory (11); so that the fundamental frequency of the audio signal is a function of the predetermined number and that the residue of the audio signal is a function of the table counter consultation.   17 - Method according to claim 16, characterized in that predetermined numbers are added to N numbers stored and the N resulting sums are used as addresses of N lookup tables (80, 81, 82, 83), and in that that the most significant bits of the sum of the data of the N look-up tables constitute the signal   data representative of the audio signal.   18 - Apparatus for generating a control signal for a disk drive forming part of a computer system comprising a microprocessor (10) and an access memory   selective (MAS) (11) and produces a video signal for a   positive recurrent balalay display, this device being characterized in that it comprises: addressing means (21) for direct access to   predetermined locations of the random access memory   when the video signal is in a suppress period   horizontal and to allow the microprocessor to   write new data in said locations when the video signal is in a deletion period, said   addressing means being coupled to the memory with selective access   tif; waveform generating means for converting the data extracted from these locations and accessed by the addressing means into a speed control signal, so that the speed control signal is produced without interference from the video signal. 19 - Apparatus according to claim 18, characterized in that the waveform generating means comprise: a   counter (102) into which the ex-   processes the locations of the selective access memory, the counter counting at a predetermined frequency, after the data has been loaded, generating means (112)   of pulses coupled to the counter to start a pulse   when the counter starts counting and for   impulse when the counter reaches a pre-   determined, the pulse generating means being coupled at the counter.   - Apparatus according to claim 19, characterized in that it includes integrating means (114) for integrating   the pulses of the pulse generating means.   21 - Apparatus according to claim 18, characterized in that the computer (97) detects the speed of the disk drive (98) and varies the control signal according to   speed to ensure dynamic calibration.   22 - Apparatus according to one of claims 18 and 21, ca-   characterized in that the speed control signal is   modified according to the track of the disc being accessed.