DE3501291A1 - SOUND PRODUCTION AND DISK SPEED CONTROL UNIT IN A COMPUTER SYSTEM - Google Patents

Description

PATENTANWÄLTE ZENZ & HELBER D 4300 ESSEN 1 AM RUHRSTEIN 1 TEL .: (02 01) 4126 ^? - A 90

APPLE COMPUTER, INC. 20525 Mariani Avenue, Cupertino, California 95014, V.St.A.

Tone generator and disk speed controller

in a computer system

The invention relates to a sound generating device, particularly for use with a raster scan and display a computer comprising a disk speed controller.

There are countless methods for generating audio signals from digital signals. These range from straight forward Solutions in which digital signals are used to generate an instantaneous amplitude of the audio signal, up to more complex vocoder methods in which the voice is performing Transfer functions are used. As will be seen, in accordance with one aspect of the invention, a digital Signal converted into an analog (audio) signal.

Computer systems, particularly smaller systems (e.g. personal computers), use raster scanning displays very frequently. The computer generates and stores the video information store them in direct access memory (RAM). With the horizontal and vertical synchronization signals synchronized counters address the memory to display synchronized Obtain data signals from memory. These signals are converted into a video signal by a shift register, for example. In some cases the memory is "bit mapped" and the output of the memory is used directly to generate the video signal used. In other cases, the output

signal of the memory a character generator which is scanned to generate video signals. A considerable proportion of the Data in the RAM is required to generate a video display, especially in the case of a dynamic, graphic display (non-text) operating mode. In personal computers or small professional computers that have microprocessors together are used with dynamic RAMs, the generation of a video display consumes a relatively large proportion of the Processor and storage time. It is therefore difficult to convert an audio signal, especially a complex audio signal, into a Playback mode to deliver.

As will be seen, the invention provides an apparatus for generating audio signals in conjunction with a microprocessor and a RAM simultaneously with video signals. The audio signals are produced without interrupting the video playback or the computer operation and, in particular, require a minimum of hardware and processor time.

Floppy disk drives typically have devices for driving the floppy disk motor at a constant speed used. In the manufacture of the floppy disk drive, certain calibration steps are often used to ensure that the floppy disk drive is using a predetermined Speed is running. This requires, in addition to the calibration steps, relatively expensive speed control devices. As will be seen, the invention uses the computer to measure the speed of rotation of the disk drive to scan and then to generate a control signal for regulating the speed of the disk drive. This will make the previously required calibrations and the previously provided speed control devices avoided.

It is already known that there can be better use of

Floppy disks or other disks with more uniform flux density at the junctions can be achieved. For this it is necessary that the speed of the disk is made dependent on the radius of the track being accessed. The invention sees one such Feature before.

The invention provides an apparatus for use with a microprocessor and random access memory (RAM) having Computer system, especially if a raster-scanned display is used in the computer system. It will an addressing device for direct access to predetermined memory locations in the RAM, in particular during the horizontal or line-rate blanking period, is used. The addressing device also allows data in the same memory locations to be updated during blanking periods. The ones in these Data stored in memory locations is converted from its digital form into an analog signal. When the data are loaded from the memory into a counter, a pulse is triggered. The pulse ends when the counter reached an overflow. The resulting pulses are integrated to produce the audio signal.

The processor generates the data signals for the RAM for a single tone by adding a predetermined number to a stored one Number added. The most significant bits of this sum identify a location in a look-up table, and the resulting (digital) data signal is then stored in RAM. The predetermined number is repeated to that stored number is added to generate each of the data signals for the RAM. For more complex tones, a number is predetermined Numbers and stored numbers are used along with a plurality of look-up tables.

The invention also provides a device for controlling the rotary

speed of the plate. The address facility associated with used with the toner generator is part of the disk controller.

In the drawing, an embodiment of the invention is shown schematically. Show it:

1 shows a block diagram of the computer system and an explanation of the address multiplexing according to FIG Invention;

Fig. 2 is a timing diagram showing the times when the RAM is transferred to the digital Signals are accessed and to which they are updated in RAM;

3 shows a block diagram of a counter for generating audio signals;

Figure 4 shows waveforms generated by the counter of Figure 3;

5 shows a flow chart for explaining the method for generating data signals;

6 shows a block diagram and a circuit diagram for generating the audio signal and the volume control;

7 shows a flow chart for explaining the method for generating the data signals for four tones;

8 shows a flow chart to explain the method for generating data signals for a "non-harmonic" audio signal;

9 is a block diagram to explain the general connections between the computer according to FIG Fig. 1 and a disk drive motor;

Fig. 10 is a block diagram for explaining part of the circuit for generating the speed control signal for the disk drive;

11 is a block diagram for explaining an additional part of the circuit for generating the speed control signal for the disk drive; and

12 shows a representation for explaining an aspect of the invention.

It is a device for generating audio signals in connection with a computer system, in particular one which generates signals for a raster scan display and a motor speed control signal. In the The following description includes numerous specific details such as specific frequencies, the number of lines, commercial Part numbers etc. are given to provide a good understanding of the invention. It is clear, however, that those skilled in the art the invention can be used without these specific details. On the other hand, known circuits are in the form of block diagrams shown in order not to unnecessarily burden the invention with details.

DEFINITION OF TERMS

In the following description, the term "audio or

Sound data signal "or" sound data "to identify a digital signal that is converted into an analog (audio) signal. The term engine speed control refers to controlling the speed of rotation of a motor or one driven by the motor Plate.

GENERAL STRUCTURE

The invention is currently used as part of a computer system (Personal Computer or small business computer) using a 68000 type microprocessor. The address and Data lines of this microprocessor 10 are shown in FIG. The other known lines connected to this computer are not shown in FIG. The microprocessor 10 is connected to random access memory (RAM) 11 which comprises sixteen 64K dynamic memory "chips". The data lines 0-15 interconnect microprocessor 10 and RAM 11 to allow data to flow between the processor and RAM. The data of the RAM are coupled to the processor via the RAM data buffer 13; the data of the RAMs 11 coupled to disk motor speed controller 27, video shift register 28 and audio counters 29. the the latter counters will be described in detail in connection with FIG. The microprocessor 10 receives data also from read only memory (ROM) 17 when the ROM is activated (ROMEN /). Similarly, data to and from the disk controller becomes 18 when the disk controller 18 is activated by a signal on line 35. This signal will how the ROMEN / signal is generated in the PALS 23. Similar is data to and from microprocessor 10 with a serial message controller 14 and an interface adapter 15 coupled (trade numbers 8530 and 6522).

Addresses of the microprocessor 10 become the ROM 17, the PALS and coupled to RAM address multiplexer 20. Some of the address signals are, as indicated, also to the disk controller 18, the serial link controller 14 and the Interface adapter 15 coupled.

The RAM address multiplexer 20 enables the RAM to be addressed both by the microprocessor 10 and directly by the count value stored in the video counter 22. During the time the video signal is painting the screen, the multiplexer 20 selects the video counter 22, which enables the RAM 11 to be addressed directly by the counter will. (A signal from PALS 23 controls this selection.) During the other times, RAM address multiplexer 20 allows this Microprocessor 10 direct access to RAM 11. The second address multiplexer 21 is like the multiplexer 20 by a Signal of the PALS 23 controlled. During the last part of the horizontal blanking signal, as in connection with Fig. 2, the multiplexer 21 takes the seven most significant bits of the counter 22 and forces the memory to this address. This requires that the sound and disk speed data be in assigned and consecutive Memory locations of the RAM are stored, giving the microprocessor easier access when updating the data enables. A latch circuit (not shown) supplies an additional bit input signal to the Address lines of the multiplexer 21 for direct access to a second page of the audio data in RAM 11.

The two 74LS393 video counters 22 generate a digital video count representing the beam position of a raster scanned Displays and additional counter values

for the horizontal and vertical retrace (blanking) periods. The time signals that operate this counter together with the reset signals are generated by the PALS 2 3.

The PALS 23 has three program field logic chips. These receive the crystal-controlled 16MHz oscillator signal from the oscillator 31. The PALS 23 generates the standard memory signals, such as RAS /, CAS /, and those used by the microprocessor from this signal used known time signals. It also supplies the horizontal synchronization signal (HSYNC /) and the vertical one Synchronization signal (VSYNC /). These signals are applied to the display via lines 32. Others outside clock signals used by the memory, such as the 8 MHz clock signal used by the counters of Figure 3 and that used by the disk motor speed controller The clock signal used are also generated within the PALS 23.

In the preferred embodiment of the invention, two 32Kx8 ROMs 17 are used. They provide storage space for Diagnostic, initiation and other functions which are of no importance for the invention. The disk controller 18 forms an interface for a floppy disk drive.

The adapter 15 is connected to a keyboard 24. A mouse 25 provides both cursor input and switch information to the control device 14 as well as to the adapter 15. A volume control button shown on the graphic screen is activated by the Mouse controlled and supplies three bits of binary data on lines 37. As will be described in connection with FIG. 6 these three bits are used for static volume control of the audio signal.

VIDEO TIMELINE

In the preferred embodiment of the invention, the horizontal scan is performed at 22,256.84398 Hz and the vertical scan Sampling at 60Hz. Each (half) image consists of 370 scan lines with 70 4 pixels or picture elements per horizontal scan. This corresponds to 44 16-bit words of RAM 11. The with 16MHz specified main clock of the oscillator 31 is more precise 15.6672MHz.

Reference is now made to FIG. The display itself has 512 "live" pixels and in the horizontal direction Lines on the screen. The 192 bits remaining for each horizontal scan form the horizontal blanking period, which is also known as the "flyback time. During this period of time, the beam current in a cathode ray tube lowered and the beam moved back from one side of the screen to the other side. In the vertical Direction, in addition to the 342 lines on the screen, there are 28 additional periods during which the vertical blanking runs, i.e. the beam current is reduced again and the beam from the lower part of the screen to the upper part Part of the screen reset.

In Fig. 2, the time running from left to right is shown with broken lines 39, for example. After the 512 bits are represented in the first sample, the time represented by line 40 is reached and a Blanking. RAM 11 does not need any during blanking To provide data for the display. Before time 40, see FIG. 1, the count value of counter 22 accesses via the RAM address multiplexer 20 towards the RAM 11. This is done for each of the lines in the display. (The counter 22 holds both a horizontal as well as a vertical count.) The counters are

/ Ko-

not increased in the normal sense during the horizontal blanking period. Rather, four bits of the video counter are used for reused the count during this period. This eliminates address gaps for the audio data. If for each of the scanning lines the time 40 is reached, causes a time signal of the PALS 23 that the multiplexer 20 addresses the microprocessor 10 assumes. During the next 192 counts of the 16MHz clock, except for the last count, the Microprocessor free to access the RAM and can thus perform tasks unrelated to the display. if the last count in each of the scanning lines is reached, a signal from the PALS 23 via the multiplexer 21 leaves the counter 22 access the memory 11 directly. At that time will the 16-bit word of RAM 11 (time 41 in Fig. 2) from memory read, eight bits being transmitted to disk motor speed controller 2 7 and eight bits being transmitted to tone counters 29 (as will be seen, only six bits are used by disk motor speed controller 2 7) . During the "screen time" shown in FIG. 2, the 16-bit words are transferred from memory to the video shift register 28 given and used to develop the video signal. As mentioned, the PALS 23 delivers the horizontal and vertical synchronization signals, which are used in conjunction with the signal of the shift register 28 for controlling the video display be used.

When the 342nd scan line (shown as line 43) and time 40 on that line is reached, the multiplexer enables 20 the microprocessor 10 again accesses the RAM 11. At the end of line 43 and for the remaining period of the vertical Blanking the multiplexer 21 gives nine address bits at time 41 in the RAM 11 to enable the 16-bit word is applied to the speed control device 27 and to the counter 29. (The lines RAO to RA6 are multi-timed

plexes to provide these address signals.) During the vertical Blanking, the microprocessor 10 can access the RAM 11, except for the last count of each line. How else is described, during this period of time, the disk motor speed control data and data stored in RAM 11 become updated the sound data.

The multiplexer 21 defines with its 9-bit address adjacent storage locations in the memory, which the processor 10 a Allow easier access and update of sound and motor speed data. It should be noted that the memory locations in RAM 11 for the tone and motor speed control data is in a different location than the screen data.

In the example described, the microprocessor and video display signal transmissions share during "live" video the data bus in alternating cycles. During the horizontal blanking (for words 32 through 42) the microprocessor only access to the data bus. At time 41 according to FIG. 2 (43rd word) the microprocessor and the tone / speed data transmission share the data bus in alternating cycles.

It is possible for the microprocessor to update the audio data and the speed control data during the live video. The data is actually updated during the blanking periods. In the preferred implementation, initiated the vertical synchronization signal (flyback signal) updates the audio data. Using this signal and by updating the memory locations that have already been accessed (e.g. starting with the storage space used for line 3 9, time 41) the update does not interfere with that Reading the audio data. The software program ensures that

the update before reading the audio data remains. If the microprocessor receives the audio data without synchronization with the display updated, the data can be replaced before it is used. This execution frees the software from the need for time synchronization with the audio for data update.

AUDIO SIGNAL GENERATION

The eight audio data bits representing the audio signal are, as shown in FIG. 3, in parallel in two 4-bit counters 46 and 4 pushed. These are commercial counters. These counters are clocked by the 8 MHz clock signal on line 48. In These counters are continuously counted up to an overflow, which is scanned on line 49. So is one longer time required for overflow if all 0 ■ s in the counters are set (approximately 32 usec.), while an overflow can occur in one cycle of the 8MHz clock if all 1's have been loaded into the counters.

The audio waveform is developed by first generating pulses, the width of which is a function of the time between the eight bits being loaded into counters 46 and 47 and the overflow is. For example, as shown by Figure 4, when the tone data is loaded into the counters, the leading edge 52 of a pulse occurs on. If all O'en are loaded, an overflow occurs approximately 32 usecs later and the pulse ends on the trailing edge 54. A pulse is generated during each horizontal sweep, since an 8-bit audio data word is generated during each sweep is loaded into the counters. Therefore, pulses are generated at a frequency of approximately 22,000Hz (22kHz), which in theoretically a bandwidth of approximately 11,000Hz (11kHz) results. In Fig. 4, a second pulse 56 is essential

shown reduced width. This naturally occurs when a larger number is placed in counters 46 and 47. The in The pulse 57 shown in the third pass has a width between that of the first and second pulses.

The pulses are integrated using a conventional integrator to develop an analog signal. Of the Integrator 60 of Figure 6 receives a load signal and an overflow signal; the waveform 61 shown in Fig. 4 is in Integrator 60 developed. The waveform 61 represents the resulting integration of the pulses according to FIG.

The three information bits (bit 37a, 37b and 37c) of the interface adapter 5 5 are used to allow a user statistical control of the volume. the Amplifiers 63, 64 and 65 are switched (on or off) to control the output amplitude on line 68 enable.

CALCULATION OF THE SOUND DATA SIGNALS

Tone data of the memory defining the tone waveform is calculated by the microprocessor 10. More precisely, she are generated within the microprocessor by "software". A higher level programming language such as PASCAL can which allows a user to more easily implement the flowcharts discussed below. In general the tone data can be generated quite quickly, since the method has the advantage of the microprocessor's fast adding capability 68000 exploited.

Referring to Figure 5, it is assumed that a single "clean" tone is to be generated. First, a lookup

table stored in system memory; in the preferred embodiment, look-up table 25 is 6x8 bits. This results in an 8-bit output signal for each 8-bit address in the table. For a pure tone, the look-up table contains points corresponding to a sine wave. This is illustrated by the look-up table 70 of FIG. The method for generating the address for the following table of values consists in the repeated addition of a predetermined number, which is shown in block 74 as Δ0 _η , to a number stored in register 72. Initially, the 32-bit word stored in register 72 has any value, for example all zeros. The increment Δί> ₀ is added. The resulting sum is stored back in register 72. The most significant eight bits of the sum are separated as shown by block 76 and used as the address for the look-up table 70.

For the purpose of explanation it is assumed that Δ0 _{Ο is} small. This relatively small binary number is added to the number stored in register 72, the most significant bits not changing, rather numerous additions are required to change them. Accordingly, each of the 25 6 locations in the look-up table 70 is addressed multiple times and the eight bits of the look-up table data stored in RAM 11 slowly change. This of course corresponds to a low frequency. On the other hand, if the increment A0 _{Q is} relatively large, the results from the look-up table will change more quickly and so, for example, each of the successive 8-bit data words of the look-up table 70 stored in RAM 11 will be different. This would correspond to a high frequency. A new 8-bit tone data word is obtained with each addition represented by block 74. Therefore, by changing the increment added in each cycle, the frequency of the tone becomes

varies. All of the audio data used during each (half) picture (frame) can easily be used during a few scanning line periods the vertical blanking period.

To get envelope control or amplitude modulation, a set of tables is used. E.g. every table of the record 0-7 has a sine wave with a maximum peak

Set no
ze peak value of 2 * '. Envelope control is achieved by allowing a predetermined number of frame intervals to run before switching between sets.

Reference is made to FIG. 7 below. In the preferred embodiment, there can be up to four 25 6x8 look-up tables within the microprocessor 10 can be used. The contents of the look-up tables can be user-programmed and be different. For example, in Fig. 7, look-up table 80 is shown to be a sine wave, table 81 a triangular wave, table 82 contains a square wave, and table 83 contains a ramp. That in connection with The method described in FIG. 5 is used again. Now (with the simultaneous generation of four tones) 24 Bits used instead of 32. (This is shown by block 85 in Figure 7.) Again, an increment is shown as

Δ0 ₁ added to the previous sum (block 86). The bits with the highest evaluation are separated from the sum (block 8 7) and used as the address for the corresponding 8-bit word within table 8 0. The same process is repeated for the number shown in block 87 to which a different (or the same) increment Δ0 _? as shown in block 88, again using the most significant bits of the sum to address the look-up table 81. Similarly, different stored values and increments are generated to be shown in tables 82

and look up 83. The resulting eight bits of each table are, as shown by blocks 80, 90 and 91, added, the most significant bits separated from these sums as shown by block 92, and stored in memory 11 saved. This procedure is carried out for each one stored in the RAM 11 Tone data repeated when four tones are generated. Again, the fundamental frequency for each of the four tones is determined by the increment that is added (blocks 8 and 88) and the harmonic content is determined by the ones in the Look-up table stored "shape" is determined.

The attached Table 1 is a program written in 68000 assembly language for implementing the flowchart of FIG. 7.

The sound generating apparatus described above provides an excellent one Tone control is achieved, taking up to 24 bits of "frequency control" (for each tone) within the 11 kHz band possible are. This makes it possible to generate almost 17 million different tones within the band, which is an approximation equals (or better) the best perception of the human ear.

The methods described above are particularly suitable for generating periodic functions which are harmonic in nature and a music or the like. performing sound quality. For tones, such as the voice, an "extended" look-up buffer is used for the initial storage of a waveform representing, for example, speech. This is shown with the buffer 93 in FIG. The buffer itself can and must be provided within the RAM 11 for practical reasons when a long waveform is to be stored. The 8-bit values are in turn obtained by adding an increment A0 _Q (block 95) to a value stored in register 96.

y 12

cherten 32-bit word, whereby the most significant bits are used to address locations in the buffer 9 3. the Results of the look-up in the expanded buffer are stored and, as in the case of FIGS. 5 and 7, during horizontal blanking period selected.

The attached table 2 contains a program written in 68000 assembly language for the implementation of the flow diagram of FIG. 8.

PLATE MOTOR SPEED CONTROL UNIT

Typically, floppy disk drives and other disk drives have to drive the disk at a constant, predetermined rate Rotation speed (speed) on a suitable device. After the disk drive is manufactured, the speed control device calibrated to ensure that the data is recorded and at a certain speed to be recovered.

In the present invention, the engine speed is controlled by a computer, and furthermore, the engine speed is controlled varies as a function of the accessed track so that a uniform flux density results. That means that the motor slows down when accessing the outer tracks (larger radius) and when accessing the inner tracks Tracks (smaller radius) rotates faster.

In FIG. 9, the computer of FIG. 1 is shown as computer 97. Likewise is a disk drive, e.g. a floppy disk drive and more particularly, a disk drive motor 98 is shown. Line 99 provides the computer 97 with engine speed indicating pulses. In the preferred embodiment

which uses the usual index impulses of the motor. The used Floppy disk drives are positively connected to the motor hub so that no slippage occurs. Accordingly the index pulses themselves represent the actual speed of the floppy disk. If a slip is possible, markings or bit streams of the disc itself can be used to obtain an accurate indication of the disc speed. That Speed control signal on line 100 controls engine speed. It becomes a predetermined signal level is used on line 100 and the engine speed is sensed on line 99. This allows the computer 97 record the characteristics of the engine 98. Through this the computer recognizes the rotational speed of each motor connected to it for a specific speed Control signal. In this way, the disk drive motor 98 does not need to be calibrated after its manufacture, and the speed control device normally used in the disk drive is not required as the speed is controlled by the computer 98. How out 9, there is a closed working loop (closed control loop), since the motor 97 scans the actual motor speed via the line 9 9.

In the current implementation, the computer checks the pulses 99 and determines before writing or data before reading or writing errors occur, the characteristics of the motor 98 when a new disk is inserted into the disk drive is inserted. Obviously, other arrangements can be used, for example the index pulses be checked periodically or continuously.

In the preferred embodiment, the motor runs at a speed of 350 rpm for the outermost lane through to 700 rpm, for the inner track. The selected

The rotational speed range is a function of the radius of the disk and is dependent on the particular magnetic characteristics of the system and the size of the disk varies.

As previously mentioned, during each horizontal blanking period eight data bits are supplied to the tone counters 29 of FIG. 1 and eight bits to the speed control device 27. In the In the illustrated embodiment, only six of the bits on the bus are used for speed control. The bus is shown in FIG. 10 as bus 109, the six lines of which are connected to six stages of a shift register 102 are. The six bits of bus 108 are loaded into the six stages of shift register 102 when the tone data signals into the tone counters 29 are loaded.

Fig. 10 shows a polynomial counter. The data input to the six stages of the shift register 102 is shown in Control of a clock signal shifted. The effective shift frequency is approximately 1MHz. Because of the different Waiting states that affect the shift register are actually connected to the register by the 8MHz clock signal. The output of the last stage of the register is connected to an input of an exclusive-OR gate 104 on the line 103 connected. The output of the first stage is connected to the other input of the gate 104 via the line 105. This circuit is provided in a known manner for counting in the "polynomial generator". The stages of the shift register 102 are also connected to a condition detector 106. This detector determines when a predetermined binary State is reached within the shift register. If this state is reached, a signal is sent over the line coupled to stop the shift functions within shift register 102; this signal is in the same Way as for the sound signal to generate the end of a

ZQ>.

Used.

According to FIG. 11, the counting in the shift register 102 begins after Fig. 10 at the beginning of each horizontal sweep explained. At this point, the leading edge of a pulse becomes like the edge 115 of that shown in FIG Impulse generated. When the condition detector 106 detects a predetermined condition, the end of the pulse will be such as shown by trailing edge 116 in FIG. The pulses are integrated by the integrator 114 and that resulting signal on line 100 is used to control the speed of the motor in the normal manner.

The six bits put into the shift register 102 will always be the state before the detected by the detector 106 Reach the end of each horizontal pass. In practice, the status is during the first 40 usec. the one for everyone horizontal run required approximately 44 usec. recognized .

Ten horizontal passes are used for each speed control input. This number was chosen because the The preferred embodiment uses 370 full scan lines evenly divided into ten. Still for a pulse is generated every horizontal sweep. (The time constant associated with integrator 114 of FIG. 11 is small enough to give a continuous signal on line 100.) The one generated for each of the ten sweeps Pulse width used to determine each speed control value is "jittered" to provide accurate values. As an example, assume that a value equivalent to 6.5 is required on line 100. In reference to on FIG. 12, for the ten runs used to define this value, the first value is 6, the second value

7 etc. for the ten runs. That causes the trailing edge 116 of the impulses varies between the values 6 and 7. To an integration will correspond to the value on line 100 6.5. By distributing the values and enabling the Pulse tremors during the ten passes defining each speed control number results in a very accurate one Steering. Control accuracy beyond the six bits loaded into the shift register is achieved. In the illustrated embodiment, 400 special levels or

^(koö >

(2)

Bits reached.

In the attached table 3 this is for speed control The program used was written in 6800 0 assembly language.

An improved device has been described which has both tone generation and speed control a floppy disk drive or the like. enables.

TABLE 1

This code is sent every 16 seconds when there is a vertical return interruption executed. It calculates the 37 0 values for the next run.

MOVEM.L

MOVE.L
ADD. W.
him

MOVE.L
from D1
MOVE
MOVE

(A6), D2-D7 / AO-A5; put tone parameters in the

register

SoundBase, A6; point to buffer # 370, A6; actually, point halfway in

# $ 00FF0000, D1

# 2, - (SP) # 185, - (SP); form a mask in the upper part

; initiate outer loop counter; run through loop 185 times (Half of the buffer)

loop through once for half of the 370 values; sum the waveform values for each voice

Tone loop CLR.W D1

ADD.L D2, D3

ADD.L D4, D5

ADD.L D6, D7

ADD. L AO, A1

draw part 1 in D1

MOVE.L D5, D0

AND.L D1, DO

SWAP DO

MOVE.B 0 (A3, DO), DO

ADD.W (D0, D1) add voice 3 in D

MOVE.L D7, D0

AND.L D1, DO

SWAP DO

MOVE.B 0 (A4, D0), D0

ADD.W DO, D1 add voice 4 in D1

MOVE.L A1, DO

AND.L D1, DO

SWAP DO

MOVE.B 0 (A5, DO), D0

ADD.W D0, D1; clear the sum register (not the mask)

; calculate voice 1

; calculate voice 2

; calculate voice 3

; calculate voice 4

; cover the high bits juse bits 16-23 j see waveform table
; add them up

; cover the high bits; use bits 16-2; refer to the waveform table
; add them up

; cover the high bits; use bits 16-2; refer to the waveform table
; add them up

update the DMA tone buffer with the new value

LSR.W # 2, D1 divide by 4 (use the

most valued bits)

MOVE.B D1, (A6); put it in the buffer

ADDQ # 2, A6; bump the buffer pointer

Loop for half the values

SUBQ # 1, (SP); decrease the counter

BNE.S SoundLoop; switch to the loop until it

stands

now process the second half of the buffer

MOVE.L SoundBase, A6 pointing to the beginning of the buffer

MOVE # 185, (SP); reset the counter

SUBQ # 1,2 (SP)! Decrease the second counter

BNE.S SoundLoop; loop to the end

OK, all done, update the tone table, save the registers again and return to the caller

ADDQ # 4, SP; jump from the loop counter

MOVE.L SoundPtr, A6; take table address

ADDQ # 2, A6

MOVEM.L D2-D7 / A0-A1, (A6); save the tone register

MOVEM.L (SP) +, D0-D7 / A0-A6; save the caller registers again

TABLE 2

MOVE.L ADD. W LEA

CLR.W MOVE

OK, now loop

MOVE.B ADDQ

ADD. L SWAP area ADD. W.

ADD.W. Pay CLR.W back SWAP

SoundBase, A2 # 64, A2 676 (A2), A4

- (SP) # 33 7, D2; take the tone base address; start 3 2 bytes in ; calculate the ending address

; Tag goes to 1; 338 bytes in the first half move

after we have set everything, start the main to fill the buffer

; read it into the DMA buffer; bump to the next memory location

; bump the cumulative index; take the high part in the low

; bump to the next entry

(perhaps)
; add up the finished

; set the integer part; save D3 again

# 2, A2

D1, D3, D3

D3, A1 D3, D0 D3 D3

have we issued or requested?

CMP.L A1, A3; after the end of the buffer?

DBLE D2, Interpolate; if so, stop it

TABEL

Routine: SetSpeed, SetASpeed

Versions: D6.W (input) - track number speed should

be set for

Drive (input) - current disk drive TrkSpeedTbl (in)

Wait (output) -

Addressed (called) by:

- Speed code table for instantaneous Drive 0, or SpdChgTime if CurSpeed changed registers other than A0-A2, are D0-D2 protected

(SetSpeed): Seek, RWPower (SetASpeed): MakeSpdTbl Function: This routine determines the correct speed value for the track and sets the PWM buffer to generate the desired output value. The value of WAIT must be set to SpdChgTime when the speed is changed; otherwise 0. The TrkSpeedTbl is used for the current drive. Drive activation is not changed, only the PWM buffer in memory.

SetASpeed is an alternating input point that simply sets the PWM buffer according to a speed code in D2.

Set speed

BSR.S GetDrvl

MOVE.W D6, D2

LSR.W # 4, D2

LSL.W # 3, D2

ADD.W D1, D2

MOVE.W TrkSpeedTbl (A1, D2), D2

ADD.W. OffSpeed (A1, D1), 2

BSL.S 2

MOVEQ # 0, D2

CMP.W # 399, D2 BLE.S 3

jset D1.A1

; Speed class is equal to an even lane number ; divided by 16; adjust to double long word index

; add drive-specific offset

; reach the required speed

; add in an adjustment

(monitor max, min); do not go below 0

MOVE.W # 399, D2 MOVE.W PWMValue, DO

BPL.S 4

MOVE.W PwrOnTime (A1) D0; don't go below 399; are we at this speed?
; if the speed is invalid, wait for power-on

BRA. S. 6th do SUB.W D2, D0 BEQ.S GetDrvl BPL.S 5 NEG.W

LSL.W # 5, DO; if so, output

; positive speed difference

; multiply by 32 to get speed set process to get

CMP.W SpdChgTime (Ai), DO jminimum waiting time for speed change BGT.S 6
MOVE.W SpdChgTime (Ai), D)

; add to the current waiting time

ADD.W Wait (Ai), D0

CMP.W PwrOnTime (A1), DO

BLT.S 7

MOVE.W Pwr0nTime (A1), DO

MOVE.W DO, Wait (A1)

SetASpeed is an alternative input point that simply sets the speed code in D2

SetASpeed

MOVE.W D2, PWMValue MOVEM.L D3-D6 / A2, - (SP)

SUB. W. # 3 99, D2 NEG.W D2 EXT.L D2 DIVU #1 0, D2 MOVEQ #1 1, DO MOVE.B DO , D1 MOVE.B DO , D3 LSR.B #1 , DO EOR. B. DO , D3 LSR.B #1 , D3 BCCS 2 BSET # 5 , DO DBRA D2 , 1

; note the speed for future reference; protect A2-A7, D3-D7

; reverse it (for sony)

; bring it up ...; rest in high words

; Main speed value jprotect bit 0

; new bit 5 - cy

SWAP

D2

; Rest determines "tremors"

MOVE.B DitherTbl (D2), D5; need 10 bits for

Tremor table

ASL # 8.D5

MOVE.B Dithertbl + 1 (D2), D5; take 2 bits from the

next

LoadPWMBuf

MOVEQ
LEA

# 36, D3 PWMBuffer, A0

MOVE.L PWMBuf2, A2

MOVE.Q # 9, D2

MOVE.W D5, D4

LSL.W # 1, D4

BCCS 3 MOVE.B D0, D6 BRA. S. 4th MOVE.B D1, D6 MOVE, B D6, (A2) ADDQ # 2, AO ADDQ # 2, A2 DBRA D2, 2 DBRA D3, 1

MOVEM.L (SP) +, D3-D6 / A2

SetSpdExit
DitherTbl

• byte
.Byte

BRA

GetDrv; large loop runs 37 times; fill up PWM buffer

(37x10 = 370 bytes); in the case of an alternative buffer

; inner loop runs times
; Tremor pattern

; Carry bit = 1 means use a higher value

; use higher value; use main value

; every other byte is a pad of sound

; observe registry security conventions

; used to balance the speed values to dither

$ 00, $ 20, $ 21, $ 24, $ 94

$ AA, $ B5, $ B7, $ 7B, $ FF, $ 40, $ 00

Claims (20)

PATENTANWÄLTE ZENZ & HELBER · D 43OO ESSEN 1 · AM RUHRSTEIN 1 · TEL .: (Ο2Ο1) 4126, A QO APPLE COMPUTER, INC. Claims 1. Device for generating an analog audio signal in a computer system with a microprocessor and a random access memory (RAM), which generates a video signal for a raster-scanned display, marked by an addressing device (20, 21) for direct access to predetermined memory locations of the RAM (11) when the video signal is in a horizontal blanking period, and to enable new data to be written into these memory locations by the microprocessor (10) when the video signal is in a blanking period, the addressing device (20, 21) is coupled to the RAM (11); and waveform generating means (80 ... 88) which is accessed by the addressing device (20, 21) to convert data from the memory locations into the analog audio -Signal. 2. Apparatus according to claim 1, characterized in that the waveform generator device (80 ... 88) a counter (46, 47) into which the data of the memory locations of the RAM (11) are loaded, the counter (46, 47) after loading the data, counts at a predetermined frequency; and having a pulse generating device connected to the counter (46, 47) for triggering a pulse, when the counter (46, 47) is loaded, and to terminate this pulse when the counter (46, 47) reaches a predetermined count achieved. 3. Apparatus according to claim 2, characterized in that the end of the pulse on reaching the overflow of the counter (46, 47) is provided. 4. Apparatus according to claim 2 or 3, characterized in that an integration device (60) for integrating the pulses the pulse generating device is provided. 5. Device according to one of claims 1 to 4, characterized in that that the horizontal blanking takes place at a frequency of approximately 22,000 Hz. 6. Apparatus according to claim 5, characterized in that the vertical blanking at a frequency of approximately 60Hz he follows. 7. Device according to one of claims 1 to 6, characterized in that that a further waveform generator device (112) which is accessed by the addressing device (20), for converting the data of the storage locations into a speed control signal for a disk drive. 8. Device according to one of claims 1 to 7, characterized by a first counter (22) for generating the video signal timing for the digital count representing the display; a first address multiplexing device (21) for applying the digital count of the first counter (22) as an address to the RAM (11), at least during a portion of the horizontal Blanking period of the video signal, wherein the first addressing device (21) is connected to the counter (22) and the RAM (11); a second address multiplexer (20) for applying the digital count of the first counter (2 2) as an address to the RAM (11), during periods in which the audio signal Provides information for representation on the display and for entering address signals from the microprocessor (10) into the RAM (11) at least during portions of the vertical blanking period; and a waveform generator means which during the horizontal blanking period is addressed by the first counter (22), for converting data from the RAM (11) into the analog audio signal. 9. Apparatus according to claim 8, characterized in that the waveform generator means a second counter (46, 47) into which data from the RAM (11) are loaded, the counter counting at a predetermined frequency after the data has been loaded; and has a pulse generating device, which with the - ^ second counter is connected to trigger a pulse when the second counter is loaded and to terminate this Pulse when the second counter reaches a predetermined count. 10. Apparatus according to claim 9, characterized in that the Pulse is terminated when the second counter (46, 4 7) reaches its overflow. 11. Apparatus according to claim 10, characterized in that an integrating device (60) for integrating the pulses of the Pulse generating device is provided. 12. Apparatus according to claim 8, characterized in that an additional waveform generator device which is addressed by the first counter during the horizontal blanking period ' is used to convert data from the RAM (11) into a speed control signal is intended for a disk drive. 13. Method for generating an analog audio signal in a computer system comprising a microprocessor and a random access memory (RAM) and which supplies a video signal for a raster-scanned display, characterized in that that the RAM is accessed during the horizontal blanking periods for data signals representing audio signals to win; that the data signals are converted into the audio signal and that the data signals representing the audio signals are updated during vertical blanking periods, taking the audio signal without affecting the video signal is being developed. 14. The method according to claim 13, characterized in that the data signals representing the audio signal are generated by the microprocessor in that (a) a predetermined number is added to a stored number, (b) the most significant bits of the sum are used as a location in a look-up table, (c) the sum is stored and used as the stored number according to step (a) and (d) the data signals from the look-up table are placed in the RAM, where the fundamental frequency of the audio frequency is a function the predetermined number and the harmonic content of the audio signal are a function of the contents of the look-up table is. 15. The method according to claim 14, characterized in that Predefined numbers are added to η stored numbers and the resulting η sums as storage locations in η look-up tables are used, and that the most significant bits of the data sum from the η look-up tables form the data signal representing the audio signal. 16. Apparatus for generating a speed control signal for a disk drive in a computer system with a microprocessor and a random access memory (RAM), wherein the computer system generates a video signal for a raster scan display, characterized by an addressing device (20, 21) for direct access to predetermined memory locations of the RAM (11), if the Video signal is in a horizontal blanking period and to enable new data to be written into these memory locations, when the video signal is in a blanking period is located, the addressing device (20, 21) being connected to the RAM (11), and waveform generator means for converting the data accessed from the memory locations by the addressing device (20, 21) into the speed control signal, whereby the speed control signal can be developed without affecting or by the video signal. 17. Apparatus according to claim 16, characterized in that the Waveform generator means a counter into which data can be loaded from the memory locations of the RAM (11), the counter pays after loading the data at a predetermined frequency, and has a pulse generating device, which with is coupled to the counter and triggers a pulse when the counter starts counting and terminates the pulse when the Counter has reached a predetermined count. 18. Apparatus according to claim 16 or 17, characterized in that that an integrator device (114) for integrating the pulses from the pulse generator (112) is provided. 19. Device according to one of claims 16 to 18, characterized in that that the computer system is adapted to sense the disk drive speed and the control signal changes as a function of speed in order to achieve a dynamic calibration. 20. Device according to one of claims 16 to 19, characterized in that that the speed control signal is variable as a function of the track accessed on a disk.