JP2999914B2 - Data transfer time control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer time control circuit for controlling a time for serially transferring sampled data according to a sampling frequency.

[0002]

2. Description of the Related Art A VRAM for high-speed processing has an SRAM section called a SAM for inputting / outputting sampled video data through a serial port, and a DRAM section for storing video data. The sampled video data is transferred from the SRAM unit to the DRAM unit. Then, when transferring video data from the SRAM section to the DRAM section, the SAM and the DR are transferred every predetermined time (transfer cycle).
Video data is transferred to and from the AM unit. The time required for this transfer cycle is defined by the minimum time T _min according to the specifications of the VRAM, and during this transfer cycle, external access to the SAM must be temporarily suspended.

For example, video data obtained by sampling an appropriate video signal by a dot at a predetermined sampling frequency f _S corresponding to the video signal per horizontal cycle to a DRAM unit via a serial port at each horizontal cycle. When writing, that is, when transferring video data every horizontal cycle, the number b of dots obtained by converting the minimum time T _min of the transfer cycle by the sampling frequency is b = f _S × T _min (1). The number of dots b, as is dependent on the sampling frequency f _S, the more increases the number of dots b larger value of the sampling frequency f _S, the number of dots smaller the value of the sampling frequency f _S Conversely b Is reduced. However, when the value of the number of dots b is fixed, the value of the number of dots b is changed in a system using VRAM so that the fixed number of dots b can be obtained within the minimum time T _min even if the sampling frequency changes. It is determined based on the specified maximum sampling frequency.

[0004]

As described above, the number of dots b
Is fixed to a value corresponding to the highest sampling frequency used in a system using VRAM, if the video signal is sampled at a low sampling frequency, the data of the video signal sampled per horizontal cycle By reducing the number of a-dots, the time ratio occupied by the value of the dot number b with respect to the value of the a-dot, which is the number of sampled data per horizontal period, increases. In other words, the time during which access to the SAM is prohibited becomes longer, and the time during which the SAM can be accessed per horizontal cycle is reduced.

[0005] However, different values are selected for the sampling frequency depending on the user of the VRAM. Therefore, when the difference between the highest value and the lowest value of the sampling frequency to be used is large, the number of sampled data that can write the video signal sampled at the low sampling frequency to the VRAM decreases. . As a result, there is a problem that data obtained by sampling the video signal may be lost and a display image may be lost. The present invention has been made in view of the above problems, and provides a data transfer time control circuit that can control a data transfer time to a time suitable for a sampling frequency even when a sampling frequency for sampling a signal is significantly different. With the goal.

[0006]

A data transfer time control circuit according to the present invention is a data transfer time control circuit for controlling a time for transferring sampled data according to a sampling frequency. And a decoder for receiving the count value of the counter, outputting a signal having a time width until the count value reaches a predetermined value, and controlling the decoder to supply a signal for specifying the predetermined value to the decoder. And a unit for specifying a time for transferring data based on a signal output from the decoder.

[0007]

The counter counts the signal corresponding to the sampling frequency at which the signal is sampled, and inputs the count value to the decoder. When a signal having a predetermined value determined based on the sampling frequency is supplied from the control unit to the decoder, a signal is output from the decoder until the count value of the counter reaches the predetermined value, and when the count value reaches the predetermined value, the signal from the decoder is output. The signal disappears. Thereby, the time width of the signal output from the decoder changes according to the sampling frequency.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a configuration of a data transfer time control circuit according to the present invention. The input signal processing circuit 1 to which the video signal SVD is input has a data extraction circuit 1a, a clock generation circuit 1b, and an A / D (analog / digital) conversion circuit 1c as a sampling circuit. The video signal SVD is input to a data extraction circuit 1a and an A / D (analog / digital) conversion circuit 1c. The data extracting circuit 1a extracts a synchronization signal for determining a sampling frequency and data such as the number of scanning lines from the video signal SVD, and the extracted data is input to the CPU 2 via the data bus DB. You. The CPU 2 reads the value of the sampling frequency from a memory (not shown) stored in advance in correspondence with the data, for example, based on the input data, and determines the sampling frequency. The frequency signal of the optimized frequency is input to the clock generation circuit 1b and the A / D conversion circuit 1c of the input signal processing circuit 1 via the data bus DB.

The CPU 2 reads out and determines a decode value of the decoder 3 from a memory (not shown) stored in advance corresponding to, for example, a sampling frequency.
DC is supplied to the decoder 3. Further, the CPU 2 inputs the frequency signal of the determined sampling frequency to the clock generation circuit 1b and the A / D conversion circuit 1c via the data bus DB. The clock generating circuit 1b generates a clock of the sampling frequency based on the frequency signal of the sampling frequency input thereto, and the generated clock is input to the counter 5 as a count target.

The A / D conversion circuit 1c performs analog / digital conversion of the video signal SVD at the sampling frequency according to the frequency signal of the sampling frequency inputted thereto, and samples the video signal SVD. The converted data DT is input to the VRAM 4. The horizontal synchronizing signal HD extracted by the data extracting circuit 1a is input to the counter 5 as a reset signal.
The count value of the counter 5 is input to the decoder 3. The decoder 3 outputs the count value input from the counter 5 to the CPU.
The output of the decoder 3 is set to the H level until the decode value of the decode signal DC input from 2 is reached, and when the decode value is reached, the output of the decoder 3 is set to the L level.
A transfer time specification signal ST for specifying the time of the transfer cycle is output. The transfer time regulation signal ST output from the decoder 3 is input to the VRAM control circuit 6. VRAM
The control circuit 6 supplies the VRAM 4 with a VRAM control signal VC for controlling the transfer of data from the SRAM section to the DRAM section in the VRAM 4 while the transfer time regulation signal ST is being input.

Next, the operation of the data transfer time control circuit constructed as described above is synchronized with the horizontal synchronizing signal from the SRAM section to the DR section.
A case where data transfer to the AM unit is started will be described with reference to FIG. 2 showing a timing chart of signals of each unit. When the video signal SVD is input to the input signal processing circuit 1, the data extraction circuit 1a converts the input video signal SVD into a synchronization signal,
Data for determining the sampling frequency such as the number of scanning lines is extracted and input to the CPU 2 via the data bus DB. Then, the CPU 2 reads the value of the sampling frequency corresponding to the input data from the memory (not shown) and determines a sampling frequency suitable for the video signal SVD.

The frequency signal is transmitted from the CPU 2 to the clock generator 1b and the A / D converter 1c via the data bus DB.
Enter Further, the CPU 2 reads out a decoded value corresponding to the determined sampling frequency from a memory (not shown), determines the value to be, for example, “8”, and supplies the decoded signal DC to the decoder 3. On the other hand, the clock generation circuit 1b responds to the frequency signal input from the CPU 2 by changing the sampling frequency, for example, as shown in FIG.
The clock CLK1 shown in FIG. Data extraction circuit 1a
Extracts the horizontal synchronizing signal HD shown in FIG. 2A from the video signal SVD. And the clock CLK1 is a count target,
The horizontal synchronizing signal HD is input to the counter 5 as a reset signal. The A / D conversion circuit 1c samples the video signal SVD by performing analog / digital conversion using the frequency signal of the sampling frequency, and inputs the sampled digital video data DT to the VRAM 4.

When the horizontal synchronizing signal HD is input to the counter 5 as described above, the counter 5 starts counting the clock CLK1 from the rising edge of the horizontal synchronizing signal HD, and inputs the count value to the decoder 3. The output of the decoder 3 goes high until the count value of the counter 5 reaches “8”, which is the decode value of the decode signal DC, and goes low when the count value reaches the decode value.
The transfer time regulation signal ST shown in (b) is output and input to the VRAM control circuit 6.

Thus, the VRAM control circuit 6 outputs a VRAM control signal VC for transferring data from the SRAM section to the DRAM section in the VRAM 4 and supplies the VRAM 4 to the VRAM 4 while the transfer time regulation signal ST is being output. During the period in which the transfer time regulation signal ST is being output, data is transferred from the SRAM unit in the VRAM 4.
Transfer to DRAM section. That is, in the case of the clock CLK1 corresponding to the sampling frequency, the input signal processing circuit 1
Can be specified as the transfer cycle time suitable for the video signal SVD input to the. Then, the dot number b becomes “8”.

Next, when video signals SVD of different types are input to the input signal processing circuit 1, the sampling frequency suitable for the video signal is determined by the CPU 2 as described above. Based on the determined sampling frequency, the clock generator 1b outputs, for example, a low-frequency clock CLK2 shown in FIG. 2D. Further, the CPU 2 determines a decode value corresponding to the determined sampling frequency to, for example, “4” and supplies the decoded signal DC to the decoder 3. Then, the counter 5 starts counting the clock CLK2 from the rising of the horizontal synchronizing signal HD. As described above, the counter 5 counts up from the decoder 3 until the count value of the counter 5 reaches the decode value "4" as shown in FIG.
An H level transfer time regulation signal ST shown in (b) is output, and data is transferred from the SRAM section to the DRAM section in the VRAM 4 while the transfer time regulation signal ST is being output.

That is, when video signals of different types are input, a sampling frequency suitable for the video signal is determined,
In the case of the clock CLK2 corresponding to the sampling frequency, four clocks can define a transfer cycle time suitable for the video frequency input to the input signal processing circuit 1. Then, the dot number b becomes “4”. Therefore, the number of dots b obtained by converting the time required for the transfer cycle by the sampling frequency is:
The number of dots b that changes according to the sampling frequency and corresponds to the value of dot a, which is the number of sampled data per horizontal period
The time to prohibit access to the SAM can be given appropriately according to the sampling frequency without increasing the time ratio occupied by the value of.

Therefore, even when the sampling frequencies are significantly different, the number of sampled data that can be written to the VRAM does not decrease. In the present embodiment, the case where the video signal is sampled at the sampling frequency has been described. However, it goes without saying that the same effect can be obtained with a signal other than the video signal.

[0018]

As described above in detail, according to the present invention, a signal corresponding to a sampling frequency for sampling a signal is counted and input to a decoder, and a signal designating a predetermined value is given to the decoder to count the signal. Is defined as the time width of the frequency output by the decoder when the signal reaches a predetermined value. Therefore, even if the sampling frequency is significantly different, the time width of the signal output from the decoder is sampled. An excellent effect that can be controlled to a value suitable for the frequency is provided.

When the time for transferring the video data sampled by the sampling frequency from the SRAM unit to the DRAM unit is controlled in this way, even if the sampling frequency is significantly lower,
The time required to transfer data becomes appropriate, the number of sampled data that can be written to the VRAM does not decrease, and no data is lost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data transfer time control circuit according to the present invention.

FIG. 2 is a timing chart of signals of each section.

[Explanation of symbols]

 1 input signal processing circuit 2 CPU 3 decoder 5 counter

Claims (1)

(57) [Claims] 1. A data transfer time control circuit for controlling a time for transferring sampled data in accordance with a sampling frequency, a counter for counting a signal corresponding to the sampling frequency, and a count value of the counter being input. A decoder that outputs a signal having a time width until the count value reaches a predetermined value; and a control unit that supplies a signal to specify the predetermined value to the decoder. A data transfer time control circuit, which is configured to define a transfer time.