JPS61131477A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61131477A JPS61131477A JP59252907A JP25290784A JPS61131477A JP S61131477 A JPS61131477 A JP S61131477A JP 59252907 A JP59252907 A JP 59252907A JP 25290784 A JP25290784 A JP 25290784A JP S61131477 A JPS61131477 A JP S61131477A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- diffusion layer
- type
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000009792 diffusion process Methods 0.000 claims description 32
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕、。[Detailed description of the invention] [Industrial application field].
本発明は半導体装置、より詳しくはエピタキシャル層構
造を利用して形成しうる高濃度埋込層と、ソース、ドレ
イン拡散層との低電圧降伏を利用してグランド線を不要
とした半導体装置に関する。The present invention relates to a semiconductor device, and more particularly to a semiconductor device that eliminates the need for a ground line by utilizing low voltage breakdown between a highly doped buried layer that can be formed using an epitaxial layer structure and source and drain diffusion layers.
第２図に従来の０ＭＯ５構造が断面図で示され、同図に
おいて、２１はｎ型基板、２２はｐウェル、２３と２４
はそれぞれｐ＋＋９ソース・ドレイン拡散層、２５は例
えば多結晶シリコン（ポリシリコ７ン）で作ったゲー・
ト電極５．２６はｎ＋型の拡散層を示す、。FIG. 2 shows a conventional 0MO5 structure in cross section, in which 21 is an n-type substrate, 22 is a p-well, 23 and 24
are respectively p++9 source/drain diffusion layers, and 25 is a gate layer made of polycrystalline silicon (polysilicon), for example.
The top electrode 5.26 represents an n+ type diffusion layer.
第２図の構造において点線で囲んだ部分は１つのトラン
ジスタを構成し、ホール（ｈ）はソース拡散層２３から
ドレイン拡散層２４へ動き、ＶＤＣＦ線はソース拡散層
２３とｎ＋型型数散層２６ら図示の如くに引き出されて
いる。In the structure of FIG. 2, the part surrounded by the dotted line constitutes one transistor, the hole (h) moves from the source diffusion layer 23 to the drain diffusion layer 24, and the VDCF line moves between the source diffusion layer 23 and the n+ type scattering layer. 26 are pulled out as shown in the figure.
一般にトランジスタの製作においては、電源線、グラン
ド線、ゲート線４の３本が集、積回路（ＩＣ）の上を延
在する如°＜坪形成されている。そのことは、ＩＣの集
積度を高めるについての障害となり、また、ソース拡散
層２３とｎ４″型拡散層の接続をとるについては、それ
ぞれρ体数層の窓開けをなし、これら２つの拡散層を例
えばアルミニウム（Ａ４．）配線でつなぐ工程が必要と
なる。そして、かかる配線を形成する場合に、唇に他の
配線が設けられ！いるものであると、設計と製作に難し
い問題が発生する。Generally, in manufacturing a transistor, three wires, a power supply line, a ground line, and a gate line 4, are formed so as to extend over an integrated circuit (IC). This becomes an obstacle to increasing the degree of integration of the IC, and when connecting the source diffusion layer 23 and the n4'' type diffusion layer, a window of ρ body number layer is opened for each, and these two diffusion layers are connected to each other. For example, a step is required to connect the wires with aluminum (A4.) wires.If such wires are formed and other wires are provided on the lips, difficult problems will occur in design and manufacturing. .
（問題点を解決するための手段）
本発明は、上記問題点を解消した半導体装置を提供する
もので、その手段は、−導電型の半導体基板に形成され
た前記基板と同導電型の埋込層と、該埋込層の上に成長
した基板と同導電型のエピタキシャル層とをもったトラ
ンジスタにおいて、前記エピタキシャル層に形成された
ソース拡散層とドレイン拡散層のうちソース拡散層のみ
が前記埋込層に接する構造とし、グランド電位が前記ソ
ース拡散層、埋込層を経て基板から取り出されることを
特徴とする半導体装置によってなされる。(Means for Solving the Problems) The present invention provides a semiconductor device that solves the above-mentioned problems. In a transistor having a buried layer and an epitaxial layer grown on the buried layer and having the same conductivity type as the substrate, only the source diffusion layer is formed in the source diffusion layer and the drain diffusion layer formed in the epitaxial layer. This is achieved by a semiconductor device characterized in that it has a structure in contact with a buried layer, and a ground potential is taken out from the substrate via the source diffusion layer and the buried layer.
第２図に戻ると、Ｖｐｐ線は基板２１と同電位にある。 Returning to FIG. 2, the Vpp line is at the same potential as the substrate 21.
そこで、本発明においては、この基板と同電位のＶｌ）
ｌ）線を従来の例の如く基板の上に設けることなく、基
板内からとってＶｐｐ線を不要とする。Therefore, in the present invention, Vl) which has the same potential as this substrate
l) Eliminate the need for Vpp lines by taking them from within the substrate instead of placing them on the substrate as in the conventional example.
そのためには、ソース拡散層とｎゝ拡散層をｐｎ接合を
形成する如くに作り、 Ｖｐｐ線を基板からとる。しか
し、そうなると基板抵抗を考慮に入れなければならない
ので、ｎ１型拡散層を基板表面付近にではなくｎ＋型埋
込層として形成しておき、ソース拡散層２３をこのｎ１
型埋込層にまで達する縦型構造にすることにより、Ｖｂ
ｂ線を不要とするだけでなく、そうする場合に発生ずる
基板抵抗の問題をも解決するものである。To do this, the source diffusion layer and the n-diffusion layer are formed to form a pn junction, and the Vpp line is taken from the substrate. However, in this case, the substrate resistance must be taken into account, so the n1 type diffusion layer is formed not near the substrate surface but as an n+ type buried layer, and the source diffusion layer 23 is formed in this n1 type.
By creating a vertical structure that reaches the mold buried layer, Vb
This not only eliminates the need for the b-line, but also solves the problem of substrate resistance that occurs when doing so.
（実施例〕
以下、図面を参照して本発明の実施例を詳細に説明する
。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図に本発明の好ましい実施例であるｃｎｏｓ構造が
断面図で示され、同図において、１はｎ型基板、２はｎ
＋型埋込層、３はエピタキシャル層、４はエピタキシャ
ル層３に形成されたｐウェル、５はｐ＋型のドレイン拡
散層、６はポリシリコンのゲート電極、７はｐ＋型ソー
ス拡散層、をそれぞれ示す。FIG. 1 shows a cross-sectional view of a CNOS structure which is a preferred embodiment of the present invention, in which 1 is an n-type substrate and 2 is an n-type substrate.
3 is an epitaxial layer, 4 is a p-well formed in the epitaxial layer 3, 5 is a p+ type drain diffusion layer, 6 is a polysilicon gate electrode, and 7 is a p+ type source diffusion layer, respectively. show.
上記のデバイスにおいては １ｇ２１１〜１０２１のオ
ーダーの高濃度のソース拡散層７がｎ“型埋込層２に接
している。そして、このｐｎ接合の降伏電圧は実験によ
ると１ｖ程度であるので、通常の使用において、ソース
拡散層７−ｓ−ｎゝ型埋込層２一基板１へと導通がとれ
、第１図に示す如く基板の下からＶｐｐ線をとれば二従
来例の如く基板の上にＶｂｂ線を設ける必要がなくなる
。なお、基板がそれをグランドにおと讐パッケージに組
み立てられている場合には、図示のＶＥＮＤ線ｉ―成す
る必要はない。In the above device, the source diffusion layer 7 with a high concentration on the order of 1g211 to 1021 is in contact with the n" type buried layer 2.The breakdown voltage of this pn junction is about 1V according to experiments, so it is usually In using the source diffusion layer 7, the s-n type buried layer 2, and the substrate 1, conduction is established, and if the Vpp line is taken from the bottom of the substrate as shown in FIG. It is no longer necessary to provide a Vbb line at the VEND line shown in the figure.If the board is assembled into a package with the board connected to the ground, there is no need to provide a VBB line as shown in the figure.
第１図に示すｐチャネルＣＭＯ３は、下記の工程で製造
される。The p-channel CMO3 shown in FIG. 1 is manufactured by the following steps.
■固有抵抗１Ω・Ｃ１１％結晶方位（１０Ｇ）のｎ型シ
リコン基板１を用意する。(2) Prepare an n-type silicon substrate 1 with a specific resistance of 1Ω and a C11% crystal orientation (10G).
■□この基板に、燐または砒素をドーズ量１×１０”／
ｃｍ’ 、１００ ＫｅＶの加速エネルギーでイオン注
入して、ｎ＋型埋込層２を作る。■□Add phosphorus or arsenic to this substrate at a dose of 1×10”/
cm', and an n+ type buried layer 2 is formed by ion implantation with an acceleration energy of 100 KeV.
■エピタキシャル成長によって、１〜２μｍの厚さにエ
ピタキシャル層３を形成する。(2) Form an epitaxial layer 3 to a thickness of 1 to 2 μm by epitaxial growth.
■例えば選択酸化法（ＬＯＣＯ５法）によって素子分離
のための１μ網程度め膜厚のフィールド酸化ｌｉｔ （
図示せず）を形成する。かくして得られた素子領域に下
記の工程を実施する。 。■For example, use selective oxidation method (LOCO5 method) to perform field oxidation with a film thickness of about 1μ mesh for device isolation (
(not shown). The following steps are performed on the element region thus obtained. .
■絶縁膜（ゲート酸化膜）を作るために、例えば熱酸化
によって５ｉＯ２ＩＩ！を５００人の膜厚に形成する。■To make an insulating film (gate oxide film), for example, 5iO2II! to a thickness of 500 people.
■ポリシリコンを全面に５０００人の膜厚に被着して、
それをバターニングしてゲート電極６を形成する。
° □
■ソース、ドレイン拡散を行う、すなわち、砒素をドー
ズ量５Ｘ１０１略／ｃａｒ２．１００ ＫｅＶの加速エ
ネルギーでイオン注入□する。このとき、拡散層５と７
は同じ深さに作られる。■Polysilicon is applied to the entire surface to a thickness of 5,000 people,
The gate electrode 6 is formed by patterning it.
° □ ■ Source and drain diffusion is performed, that is, arsenic is ion-implanted at a dose of 5×101 approximately/car with an acceleration energy of 2.100 KeV. At this time, diffusion layers 5 and 7
are made at the same depth.
■ドレイン拡散層５のみを例えばレジストでカバーする
。(2) Cover only the drain diffusion layer 5 with, for example, a resist.
■ソース拡散層７だＧｊに、砒素をドーズ量ｌ×１０１
５／ ｃｍ２．２００ ＫｅＶの加速エネルギーでイオ
ン注入し、ソース拡散層７がｆｌゝ型埋込層２にまで達
するようにする。■ Arsenic is dosed l×101 in the source diffusion layer 7 Gj.
Ions are implanted with an acceleration energy of 5/cm2.200 KeV so that the source diffusion layer 7 reaches the fl-type buried layer 2.
［相］燐・シリケート・ガラス（ＰＳＧ）を全面に化学
気相成長法（ＣＶ［）ｅ）でｌμ−程度の膜厚に成長す
る。 □
■ＰＳＧ ＩＩにコンタクトホールを開ける。[Phase] Phosphorous silicate glass (PSG) is grown on the entire surface by chemical vapor deposition (CV[)e) to a film thickness of about lμ-. □ ■Drill a contact hole in PSG II.
＠＾Ｅを全面に被着する。Apply ＠＾E to the entire surface.
Ｏ・＾ｌをパターニングして、電源線、ゲート線を形成
する。しかし、ｖｐＤ線は形成する必要がない。Pattern O.^l to form power supply lines and gate lines. However, the vpD line does not need to be formed.
なお、以上の説明はｐチャネルＣＭＯ５の製造を例にと
ってなしたが、本発明の適用範囲はその場合に限定され
るものではない。Note that although the above explanation has been made using the manufacture of a p-channel CMO 5 as an example, the scope of application of the present invention is not limited to that case.
以上説明したように本発明によれば、ＩＣの製造におい
て、従来３本の配線を設ける必要があったのが２本で足
りることになるので、ｔＣの集積度を高めるに有効であ
り、また面積が限定されたところデバイスを形成するに
便利である。As explained above, according to the present invention, in the manufacture of ICs, only two wires are required instead of three wires in the past, which is effective in increasing the degree of integration of tC. It is convenient to form devices where the area is limited.
第１図は本発明実施例の断面図、第２図は従来例の断面
図である。
図中、１はｎ型シリコン基板、２はｎ１型埋込層、３は
エピタキシャル層、４はｐウェル、５はドレイン拡散層
、６はゲート電極、７はソース拡散層、をそれぞれ示す
。
第１図
第２図FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. In the figure, 1 is an n-type silicon substrate, 2 is an n1-type buried layer, 3 is an epitaxial layer, 4 is a p-well, 5 is a drain diffusion layer, 6 is a gate electrode, and 7 is a source diffusion layer. Figure 1 Figure 2
Claims (1)
型の埋込層と、該埋込層の上に成長した基板と同導電型
のエピタキシャル層とをもったトランジスタにおいて、
前記エピタキシャル層に形成されたソース拡散層とドレ
イン拡散層のうちソース拡散層のみが前記埋込層に接す
る構造とし、グランド電位が前記ソース拡散層、埋込層
を経て基板から取り出されることを特徴とする半導体装
置。In a transistor having a buried layer formed on a semiconductor substrate of one conductivity type and having the same conductivity type as the substrate, and an epitaxial layer grown on the buried layer and having the same conductivity type as the substrate,
Among the source diffusion layer and drain diffusion layer formed in the epitaxial layer, only the source diffusion layer is in contact with the buried layer, and the ground potential is taken out from the substrate via the source diffusion layer and the buried layer. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252907A JPS61131477A (en) | 1984-11-30 | 1984-11-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59252907A JPS61131477A (en) | 1984-11-30 | 1984-11-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61131477A true JPS61131477A (en) | 1986-06-19 |
Family
ID=17243823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59252907A Pending JPS61131477A (en) | 1984-11-30 | 1984-11-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61131477A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489557A (en) * | 1987-09-30 | 1989-04-04 | Toshiba Corp | Semiconductor device |
| JP2010024661A (en) * | 2008-07-16 | 2010-02-04 | Shin Nikkei Co Ltd | Connection window |
-
1984
- 1984-11-30 JP JP59252907A patent/JPS61131477A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489557A (en) * | 1987-09-30 | 1989-04-04 | Toshiba Corp | Semiconductor device |
| JP2010024661A (en) * | 2008-07-16 | 2010-02-04 | Shin Nikkei Co Ltd | Connection window |
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