JPS61128544A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61128544A
JPS61128544A JP59251063A JP25106384A JPS61128544A JP S61128544 A JPS61128544 A JP S61128544A JP 59251063 A JP59251063 A JP 59251063A JP 25106384 A JP25106384 A JP 25106384A JP S61128544 A JPS61128544 A JP S61128544A
Authority
JP
Japan
Prior art keywords
fuse
section
wiring
conductive layer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59251063A
Other languages
Japanese (ja)
Inventor
Kenichi Yasuda
憲一 安田
Kiichi Morooka
諸岡 毅一
Narihito Yamagata
整人 山形
Kazutami Arimoto
和民 有本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59251063A priority Critical patent/JPS61128544A/en
Publication of JPS61128544A publication Critical patent/JPS61128544A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To decrease circuit area and to improve energy efficiency when a fuse is cut, by forming the conductive layer on a substrate through an insulation film to construct the wiring section that connects a fuse which is one part of the redandant circuit with a fuse by means of this conductive layer. CONSTITUTION:A wiring section 12 is constructed on a silicon substrate 7. The wiring section 12 connects a fuse section 11 which is one part of the redandant circuit with a fuse section 11 by means of a conductive layer 10. This layer 10 is formed with polysilicon through a PSG inter layer insulation film 8. And the wiring section 12 corresponds to the conventional node or aluminum wiring. Further, this fuse section 11 and wiring section 12 can be constructed with metal silicide having high-melting point, rather than polisilicon. The circuit area can be reduced, with advantage in layout since no connecting section with conventional aluminum is required. Moreover, a facorable energy efficiency is achieved since the energy of the laser is not conducted to the n<+> diffusion layer through aluminum wiring when the fuse is cut.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に関し、特にダイナミックメモ
リにおけるレーザプログラム方式のスペアデコーダの改
良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an improvement of a laser-programmed spare decoder in a dynamic memory.

〔従来の技術〕[Conventional technology]

従来のこの種の装置を第3図ないし第5図を用いて説明
する。第5図はスペアデコーダの回路図であり、図にお
いて、RAO−RA6.RAO〜RASはアドレス信号
、CRDIはゲート信号、PRDはプリチャージ信号で
ある。
A conventional device of this kind will be explained with reference to FIGS. 3 to 5. FIG. 5 is a circuit diagram of a spare decoder, and in the figure, RAO-RA6. RAO to RAS are address signals, CRDI is a gate signal, and PRD is a precharge signal.

また第3図は第5図に示す回路を実際に半導体基板上に
形成した例であり、また第4図は第3図のff−ff線
断面図である。図において、1はとニーズ部で、ポリシ
リコン(Poj!ysL)等で形成されている。2はノ
ードで、半導体基板中のn+拡散層により構成されてい
る。3.4はアルミニウムで形成されたアルミ配線で、
上記ヒユーズ1とノード2とはアルミ配線3を介して接
続されている。5はトランジスタで、n十拡散層6を介
してGNDラインと結がっている。父上記ヒユーズ1は
アルミ配線4を介してトランジスタ5と接続されている
。7はシリコン基板、8はPSGJ’1iii間絶縁膜
、9はパッシベーション膜である。
3 shows an example in which the circuit shown in FIG. 5 is actually formed on a semiconductor substrate, and FIG. 4 is a sectional view taken along the line ff-ff in FIG. 3. In the figure, reference numeral 1 denotes a need portion, which is made of polysilicon (Poj!ysL) or the like. Reference numeral 2 denotes a node, which is constituted by an n+ diffusion layer in the semiconductor substrate. 3.4 is an aluminum wiring made of aluminum,
The fuse 1 and the node 2 are connected via an aluminum wiring 3. Reference numeral 5 denotes a transistor, which is connected to the GND line via an n+ diffusion layer 6. The above-mentioned fuse 1 is connected to a transistor 5 via an aluminum wiring 4. 7 is a silicon substrate, 8 is a PSGJ'1iii insulating film, and 9 is a passivation film.

第5図に示すスペアデコーダは、メモリにおける不良ラ
インを救済するためのものであるから、このままでは不
活性であり、選択されない。正規のラインに不良が発生
した場合に、第5図に示すデコーダを活性化し、不良ラ
インと予備ラインとを入れ替えるのであるが、スペアデ
コーダを活性化するためには、レーザを用いてヒユーズ
1部分プログラムは切断するヒユーズ1の組み合わせで
行なわれ、プログラムが行なわれることによって、不良
デコーダに相当するスペアデコーダが構成されるように
なる。
Since the spare decoder shown in FIG. 5 is for relieving a defective line in the memory, it is inactive and not selected as it is. When a defect occurs in a regular line, the decoder shown in Figure 5 is activated and the defective line is replaced with a spare line. Programming is performed by combining fuses 1 to be cut, and by performing programming, a spare decoder corresponding to a defective decoder is configured.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら従来の構成では、ヒユーズ部1がアルミ配
線3を介してn十拡散層2と接続されているため、熱容
量が小さくなり、ヒユーズ切断時にレーザのエネルギが
効率良く消費されなかった。
However, in the conventional configuration, since the fuse portion 1 is connected to the n+ diffusion layer 2 via the aluminum wiring 3, the heat capacity is small, and the laser energy is not efficiently consumed when cutting the fuse.

又アルミ配線3を形成しなければならないため、面積を
要し、レイアウト上不利であった。
Furthermore, since the aluminum wiring 3 must be formed, a large area is required, which is disadvantageous in terms of layout.

この発明は上記のような問題点を解消するためになされ
たもので、ヒユーズ切断時のエネルギ効率を高めるとと
もに、回路を形成するのに必要な面積を少なくできる半
導体装置を提供することを目的としている。
This invention was made to solve the above-mentioned problems, and aims to provide a semiconductor device that can increase the energy efficiency when cutting a fuse and reduce the area required to form a circuit. There is.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、半導体基板上に絶縁膜を
介して導電層を形成し、この導電層でもって冗長回路の
一部であるヒユーズ及び該ヒユーズ間を結合する配線部
を構成するようにしたものである。
In the semiconductor device according to the present invention, a conductive layer is formed on a semiconductor substrate via an insulating film, and the conductive layer constitutes fuses that are part of a redundant circuit and a wiring portion that connects the fuses. This is what I did.

〔作用〕[Effect]

この発明における半導体装置では、ヒユーズと配線部と
が一体成形されることから、回路面積が少なく、又従来
のように熱が熱容量の小さいアルミ層を通してn十拡散
層へ逃げることもないため、エネルギ効率が高い。
In the semiconductor device according to the present invention, since the fuse and the wiring part are integrally molded, the circuit area is small, and unlike the conventional case, heat does not escape to the diffusion layer through the aluminum layer with a small heat capacity, so energy is reduced. High efficiency.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図及び第2図は本発明の一実施例による半導体装置
を示し、第1図は上記装置の平面図、第2図は第1図の
■−■線断面図である。図において、第3図ないし第5
図と同一符号は同図と同一のものを示し、10はシリコ
ン基板7上にPSG眉間絶縁膜8を介してポリシリコン
を用いて形成された導電層で、該導電層10により冗長
回路の一部であるヒユーズ部11及びヒユーズ部11間
を結合する配線部12が構成されており、該配線部12
は従来のノード及びアルミ配線(第3,4図の2.3参
照)に相当するものである。なおこのヒユーズ部11及
び配線部12はポリシリコンではなく、高融点金属シリ
サイドでもって構成してもよい。
1 and 2 show a semiconductor device according to an embodiment of the present invention, FIG. 1 is a plan view of the device, and FIG. 2 is a sectional view taken along the line 1--2 in FIG. 1. In the figure, Figures 3 to 5
The same reference numerals as in the figure indicate the same parts as in the figure, and 10 is a conductive layer formed using polysilicon on the silicon substrate 7 via the PSG eyebrow insulating film 8, and the conductive layer 10 serves as a redundant circuit. A fuse part 11 that is a fuse part and a wiring part 12 that connects the fuse parts 11 are configured.
corresponds to the conventional node and aluminum wiring (see 2.3 in Figs. 3 and 4). Note that the fuse portion 11 and the wiring portion 12 may be made of refractory metal silicide instead of polysilicon.

次に作用効果について説明する。Next, the effects will be explained.

上述のような回路の構成においては、従来のようなアル
ミニウムによる接合部(第3.4図の3参照)が不必要
なため、回路面積を少なくすることができ、レイアウト
上有利である。又、ヒユーズ切断時におけるレーザのエ
ネルギがアルミ配線を介してn十拡散層(第3,4図の
2参照)へ伝わることもないため、エネルギ効率がよい
、さらにn十拡散層よりポリシリコン又は高融点シリサ
イドの方が寄生抵抗及び寄生容量が小さいため、時定数
が小さくなり、デコーダの充放電が高速化され、動作の
安定化・高速化につながる。
In the circuit configuration as described above, the conventional aluminum joint (see 3 in FIG. 3.4) is unnecessary, so the circuit area can be reduced, which is advantageous in terms of layout. In addition, the energy of the laser when cutting the fuse is not transmitted to the n0 diffusion layer (see 2 in Figures 3 and 4) through the aluminum wiring, so energy efficiency is good. Since high melting point silicide has smaller parasitic resistance and parasitic capacitance, the time constant becomes smaller, and the charging and discharging of the decoder becomes faster, leading to more stable and faster operation.

なお上記実施例ではレーザプログラム方式のスペアデコ
ーダを例にとって説明したが、この他、電気プログラム
方式スペアデコーダあるいはマスクROMなどの半導体
ヒユーズに関するものにも適用できることは言うまでも
ない。
Although the above embodiment has been explained by taking a laser program type spare decoder as an example, it goes without saying that the present invention can also be applied to an electric program type spare decoder or a semiconductor fuse such as a mask ROM.

また上記実施例では一体形成部の材料としてポリシリコ
ン、高融点金属シリサイドを使用した例を説明したが、
その他シリサイドあるいはポリサイドを使用した場合に
も同様の効果がある。
Further, in the above embodiment, an example was explained in which polysilicon and high melting point metal silicide were used as the material of the integrally formed part.
Similar effects can be obtained when using other silicides or polycides.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明によれば、半導体基板上に絶縁膜
を介して導電層を形成し、この導電層でもって冗長回路
の一部であるヒユーズ及び該ヒユーズ間を結合する配線
部を構成するようにしたので、回路面積を少なくできる
とともに、ヒユーズ切断時のエネルギ効率を向上できる
効果がある。
As described above, according to the present invention, a conductive layer is formed on a semiconductor substrate via an insulating film, and this conductive layer constitutes fuses that are part of a redundant circuit and a wiring section that connects the fuses. This has the effect of reducing the circuit area and improving the energy efficiency when cutting the fuse.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体装置の平面図
、第2図は第1図の■−■線断面図、第3図は従来の半
導体装置の平面図、第4図は第3図のIV−IV線断面
図、第5図はスペアデコーダの回路図である。 図中、7は半導体基板、8は絶縁膜、10は導電層、1
1はヒユーズ部、12は配線部である。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, FIG. 3 is a plan view of a conventional semiconductor device, and FIG. FIG. 5 is a sectional view taken along the line IV--IV in the figure, and is a circuit diagram of the spare decoder. In the figure, 7 is a semiconductor substrate, 8 is an insulating film, 10 is a conductive layer, 1
1 is a fuse section, and 12 is a wiring section. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に絶縁膜を介して導電層が形成され
、該導電層により冗長回路の一部であるヒューズ及び該
ヒューズ間を結合する配線部が構成されていることを特
徴とする半導体装置。
(1) A semiconductor characterized in that a conductive layer is formed on a semiconductor substrate with an insulating film interposed therebetween, and the conductive layer constitutes a fuse that is part of a redundant circuit and a wiring section that connects the fuses. Device.
(2)上記導電層は、ポリシリコン又は金属シリサイド
を用いて形成されたものであることを特徴とする特許請
求の範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the conductive layer is formed using polysilicon or metal silicide.
JP59251063A 1984-11-28 1984-11-28 Semiconductor device Pending JPS61128544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59251063A JPS61128544A (en) 1984-11-28 1984-11-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59251063A JPS61128544A (en) 1984-11-28 1984-11-28 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61128544A true JPS61128544A (en) 1986-06-16

Family

ID=17217071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59251063A Pending JPS61128544A (en) 1984-11-28 1984-11-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61128544A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03106055A (en) * 1989-09-20 1991-05-02 Nippondenso Co Ltd Semiconductor device and manufacture thereof
WO1997023907A1 (en) * 1995-12-22 1997-07-03 Micron Technology, Inc. Reduced pitch laser redundancy fuse bank structure
US5905295A (en) * 1997-04-01 1999-05-18 Micron Technology, Inc. Reduced pitch laser redundancy fuse bank structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269537A (en) * 1975-12-08 1977-06-09 Fujitsu Ltd Semiconductor memory
JPS558815A (en) * 1978-07-04 1980-01-22 Teijin Ltd Filter
JPS5756947A (en) * 1980-09-22 1982-04-05 Toshiba Corp Semiconductor integrated circuit device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5269537A (en) * 1975-12-08 1977-06-09 Fujitsu Ltd Semiconductor memory
JPS558815A (en) * 1978-07-04 1980-01-22 Teijin Ltd Filter
JPS5756947A (en) * 1980-09-22 1982-04-05 Toshiba Corp Semiconductor integrated circuit device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03106055A (en) * 1989-09-20 1991-05-02 Nippondenso Co Ltd Semiconductor device and manufacture thereof
WO1997023907A1 (en) * 1995-12-22 1997-07-03 Micron Technology, Inc. Reduced pitch laser redundancy fuse bank structure
US5747869A (en) * 1995-12-22 1998-05-05 Micron Technology, Inc. Reduced pitch laser redundancy fuse bank structure
US6597054B1 (en) 1995-12-22 2003-07-22 Micron Technology, Inc. Reduced pitch laser redundancy fuse bank structure
US5905295A (en) * 1997-04-01 1999-05-18 Micron Technology, Inc. Reduced pitch laser redundancy fuse bank structure

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