JPS6076140A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6076140A JPS6076140A JP58183837A JP18383783A JPS6076140A JP S6076140 A JPS6076140 A JP S6076140A JP 58183837 A JP58183837 A JP 58183837A JP 18383783 A JP18383783 A JP 18383783A JP S6076140 A JPS6076140 A JP S6076140A
- Authority
- JP
- Japan
- Prior art keywords
- fuse link
- layer
- laser beam
- semiconductor device
- fuse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
- H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は冗長性メモリを備える半導体装置にれるべき
ヒユーズリンクを備える半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device equipped with a fuse link to be used in a semiconductor device equipped with a redundant memory.
［従来技術］
第１因は、従来の半導体装置のヒユーズリンク部分を示
す断面図である。図において、たとえばシリコン基板で
ある半容体基体１上にフィールド酸化膜２が配置され、
このフィールド酸化１１１２上にヒユーズリンク３が配
置される。そして、ヒユーズリンク３は、ＰＥＧ （リ
ン珪酸ガラス）膜４によって覆われる。ヒユーズリンク
３の材料としては、一般的にはポリシリコン、高融点金
属またはそれらのシリサイド化合物が用いられる。[Prior Art] The first factor is a cross-sectional view showing a fuse link portion of a conventional semiconductor device. In the figure, a field oxide film 2 is placed on a half-volume base 1, which is a silicon substrate, for example.
Fuse link 3 is placed on this field oxide 1112. The fuse link 3 is then covered with a PEG (phosphosilicate glass) film 4. As a material for the fuse link 3, polysilicon, a high melting point metal, or a silicide compound thereof is generally used.
冗長回路を具備したメモリにおいて、不要メモリセルな
不活性にしたり、スペアデコーダに置換すべきアドレス
を書込んだりするために、第１図に示したようなヒユー
ズリンクをレーザビームによって切断することが行なわ
れる。In a memory equipped with a redundant circuit, fuse links as shown in Figure 1 can be cut with a laser beam in order to deactivate unnecessary memory cells or to write addresses to be replaced in spare decoders. It is done.
このヒユーズリンクの切断は次のようなメカニズムによ
ってなされる。すなわち、レーザピームムのエネルギが
ヒユーズリンク３に吸収され、そのためヒユーズリンク
３がｍｓ、気化し切断される。ヒユーズリンク３は完全
に切断されねばならず、そのためにレーザビームのエネ
ルギを適切に選ぶ必要がある。しかしながら、実際には
、ヒユーズ膜厚のばらつき、ＰＳＧ膜厚のばらつき、照
射位置ずれ等を考慮して、これらのばらつきがあっても
ヒユーズリンクを完全に切断することができるようにす
るために、レーザビームのエネルギは実際の必要量より
も大きくなるように設定しである。This fuse link is disconnected by the following mechanism. That is, the energy of the laser beam is absorbed by the fuse link 3, so that the fuse link 3 is vaporized and cut for ms. The fuse link 3 must be completely cut, and for this purpose the energy of the laser beam must be selected appropriately. However, in reality, in order to be able to completely cut the fuse link even when there are variations in fuse film thickness, PSG film thickness, irradiation position deviation, etc., The energy of the laser beam is set to be greater than the amount actually required.
この場合、レーザビームが必要量以上に大きなエネルギ
を有しているので、ヒユーズリンク３は完全に切断され
る。しかし、余分のエネルギ、すなわち過剰エネルギが
さらにヒユーズリンク３以外の層、すなわちヒユーズリ
ンク３の下のフィールド酸化１ｉＩ ２、シリコン基板
１にも吸収されるという事態が生ずる。このような事態
が生じたとき、その不具合として２つのモードが考えら
れる。１つはレーザビームによってフィールド酸化膜２
に穴があいたり、またはフィールド酸化膜２の亀裂が入
った個所に溶融したポリシリコンが侵入し、ヒユーズ−
リンク３と基板１とが電気的に接続されるというモード
である。他の１つは、シリコン基板１が溶融し、近傍に
配置されているｐｎ接合特性を劣化させるモードである
。In this case, the fuse link 3 is completely cut off because the laser beam has more energy than necessary. However, a situation arises in which extra energy, ie excess energy, is also absorbed in layers other than the fuse link 3, ie the field oxide 1iI 2 under the fuse link 3, the silicon substrate 1. When such a situation occurs, there are two possible modes of failure. One is to remove the field oxide film 2 using a laser beam.
If there are holes in the field oxide film 2 or cracks in the field oxide film 2, molten polysilicon may enter the area and cause a fuse.
This is a mode in which the link 3 and the board 1 are electrically connected. The other mode is a mode in which the silicon substrate 1 melts and deteriorates the characteristics of pn junctions arranged nearby.
［発明のＩＩＡ要］
この発明は上述された欠点を解消するためになされたも
のであり、その主たる目的は、ヒユーズ切断時の品質劣
化を防止し得る半導体装置を提供することである。[IIA Summary of the Invention] This invention has been made to eliminate the above-mentioned drawbacks, and its main purpose is to provide a semiconductor device that can prevent quality deterioration when a fuse is cut.
この発明は、レーザビームで切断されるべきヒユーズリ
ンクの下に、絶縁物を介して、レーザビームの過剰エネ
ルギを吸収するための第２の層を配置したことを特徴と
する半導体装置である。The present invention is a semiconductor device characterized in that a second layer for absorbing excess energy of the laser beam is disposed below the fuse link to be cut by the laser beam, with an insulating material interposed therebetween.
［発明の実施例］
第２図は、この発明の一実施例のヒユーズリンク部分を
示す断面図である。図において、半導体基体１上にフィ
ールド酸化膜２が配置されることは第１図と同様である
。ただ特徴的な構成は、ＰＳＧ膜４によって覆われるヒ
ユーズリンク３の下に、絶縁！！！５を介して、第２の
ｆｆ１ｉ６が配置されていることである。ヒユーズリン
ク３は、一般的には、ポリシリコン、高融点金属または
それらのシリサイド化合物から作られる。そして、第２
の層６の材料としては、切断されるべきヒユーズリンク
３と同じ材料、すなわちポリシリコン、高融点金属、ま
たはそれらのシリサイド化合物から作られるのが好まし
い。なぜならば、そのようにすれば、集積回路製造フロ
ー上、抵抗、ゲート電極など他の目的にも用いることが
可能だからである。[Embodiment of the Invention] FIG. 2 is a sectional view showing a fuse link portion of an embodiment of the invention. In the figure, field oxide film 2 is disposed on semiconductor substrate 1, as in FIG. However, the characteristic structure is that the fuse link 3 covered by the PSG film 4 is insulated! ! ! The second ff1i6 is arranged through the second ff1i6. The fuse link 3 is generally made of polysilicon, a refractory metal or a silicide compound thereof. And the second
The layer 6 is preferably made of the same material as the fuse link 3 to be cut, ie polysilicon, a refractory metal or a silicide compound thereof. This is because, in this way, it can be used for other purposes such as resistors and gate electrodes in the integrated circuit manufacturing flow.
上述の４Ｒ造によれば、ヒユーズリンク３を切断するの
に必要なエネルギよりも大きなエネルギを有するレーザ
ビームが用いられても過剰エネルギは第２の層６に吸収
されるので、前述した不具合を生じさせない。According to the above-mentioned 4R structure, even if a laser beam having a larger energy than that required to cut the fuse link 3 is used, the excess energy is absorbed by the second layer 6, so that the above-mentioned problem can be avoided. Don't let it happen.
なお、第２のｗｊ６の形状または寸法は、レーザビーム
を照射する方向から見て、ヒユーズリンク３より大きく
するのが望ましい。こうすることによって、照射位置が
たとえずれたとしても、レーザビームのエネルギは第２
の層６に吸収され、フィールド酸化１！！２やシリコン
基板１に到達するのを防止することができる。Note that the shape or size of the second wj6 is desirably larger than that of the fuse link 3 when viewed from the laser beam irradiation direction. By doing this, even if the irradiation position is shifted, the energy of the laser beam will be the same as the second one.
is absorbed into the layer 6 of the field oxidation 1! ! 2 and the silicon substrate 1 can be prevented.
［発明の効果］
以上のように、この発明によれば、ヒユーズリンクの下
にレーザビームの過剰エネルギを吸収するための８Ｉ２
の層を配置した構成であるので、ヒユーズ切１１１Ｆｉ
時の品質劣化を効果的に防止することができる。[Effects of the Invention] As described above, according to the present invention, the 8I2 for absorbing excess energy of the laser beam is provided below the fuse link.
Since the structure has layers of
It is possible to effectively prevent quality deterioration over time.
ｉ１因は、従来の半導体装置のヒユーズリンク部分を示
す断面図である。第２因は、この発明の一実施例のヒユ
ーズリンク部分を示す断面図である。
図において、３はヒユーズリンク、５は絶縁膜、６は第
２の層を示す。
代理人 大 岩 増 雄1 is a sectional view showing a fuse link portion of a conventional semiconductor device. The second factor is a sectional view showing a fuse link portion of an embodiment of the present invention. In the figure, 3 indicates a fuse link, 5 indicates an insulating film, and 6 indicates a second layer. Agent Masuo Oiwa
Claims (3)
の下に、絶縁物を介して、レーザビームの過剰エネルギ
を吸収するための第２の層を配置したことを特徴とする
、半導体装置。(1) A semiconductor device characterized in that a second layer for absorbing excess energy of the laser beam is disposed below the fuse link to be cut by the laser beam, with an insulating material interposed therebetween.
リシリコン、高融点金属またはそれらのシリサイド化合
物から作られる、特許請求の範囲第１項記載の半導体装
置。(2) The semiconductor device according to claim 1, wherein the fuse link and the second layer are made of polysilicon, a high melting point metal, or a silicide compound thereof.
層の寸法は前記ヒユーズリンクより大きくされているこ
とを特徴とする特許請求の範囲第１項または第２項記載
の半導体装置。(3) The semiconductor device according to claim 1 or 2, wherein the dimensions of the second layer are larger than the fuse link with respect to the direction in which the laser beam strikes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58183837A JPS6076140A (en) | 1983-09-30 | 1983-09-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58183837A JPS6076140A (en) | 1983-09-30 | 1983-09-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6076140A true JPS6076140A (en) | 1985-04-30 |
Family
ID=16142704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58183837A Pending JPS6076140A (en) | 1983-09-30 | 1983-09-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076140A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS631054A (en) * | 1986-06-20 | 1988-01-06 | Toshiba Corp | Fuse built-in type semiconductor device |
| JPS633432A (en) * | 1986-06-24 | 1988-01-08 | Nec Corp | Semiconductor device |
| US5223735A (en) * | 1988-09-30 | 1993-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device in which circuit functions can be remedied or changed and the method for producing the same |
| US6265778B1 (en) | 1999-07-27 | 2001-07-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a multi-level interconnection structure |
| US6339250B1 (en) * | 1998-07-06 | 2002-01-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2007134523A (en) * | 2005-11-10 | 2007-05-31 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5775442A (en) * | 1980-10-29 | 1982-05-12 | Toshiba Corp | Semiconductor device |
| JPS58170A (en) * | 1981-06-24 | 1983-01-05 | Mitsubishi Electric Corp | Semiconductor device |
| JPS59135746A (en) * | 1983-01-24 | 1984-08-04 | Nec Corp | Semiconductor device containing programable element |
-
1983
- 1983-09-30 JP JP58183837A patent/JPS6076140A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5775442A (en) * | 1980-10-29 | 1982-05-12 | Toshiba Corp | Semiconductor device |
| JPS58170A (en) * | 1981-06-24 | 1983-01-05 | Mitsubishi Electric Corp | Semiconductor device |
| JPS59135746A (en) * | 1983-01-24 | 1984-08-04 | Nec Corp | Semiconductor device containing programable element |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS631054A (en) * | 1986-06-20 | 1988-01-06 | Toshiba Corp | Fuse built-in type semiconductor device |
| JPS633432A (en) * | 1986-06-24 | 1988-01-08 | Nec Corp | Semiconductor device |
| US5223735A (en) * | 1988-09-30 | 1993-06-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device in which circuit functions can be remedied or changed and the method for producing the same |
| US5279984A (en) * | 1988-09-30 | 1994-01-18 | Mitsubishi Denki Kabushiki Kaisha | Method for producing a semiconductor integrated circuit device in which circuit functions can be remedied or changed |
| US6339250B1 (en) * | 1998-07-06 | 2002-01-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6265778B1 (en) | 1999-07-27 | 2001-07-24 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a multi-level interconnection structure |
| JP2007134523A (en) * | 2005-11-10 | 2007-05-31 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
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