JPS61127469U - - Google Patents

Info

Publication number
JPS61127469U
JPS61127469U JP1001685U JP1001685U JPS61127469U JP S61127469 U JPS61127469 U JP S61127469U JP 1001685 U JP1001685 U JP 1001685U JP 1001685 U JP1001685 U JP 1001685U JP S61127469 U JPS61127469 U JP S61127469U
Authority
JP
Japan
Prior art keywords
test stations
semiconductor testing
testing device
memory
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1001685U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1001685U priority Critical patent/JPS61127469U/ja
Publication of JPS61127469U publication Critical patent/JPS61127469U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る半導体試験装置の全体ブ
ロツク図、第2図は従来の半導体試験装置の全体
構成ブロツク図、第3図は他の実施例を示す半導
体試験装置のブロツク図である。 11……テスタ本体、12……CPU、13…
…メモリ、14,15……テストステーシヨン、
16,17……データバツフア、18,19……
入出力装置、20,21……被測定試料。
FIG. 1 is an overall block diagram of a semiconductor testing device according to the present invention, FIG. 2 is a block diagram of the overall configuration of a conventional semiconductor testing device, and FIG. 3 is a block diagram of a semiconductor testing device showing another embodiment. 11...Tester body, 12...CPU, 13...
...Memory, 14,15...Test station,
16,17...data buffer, 18,19...
Input/output device, 20, 21... Sample to be measured.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 中央処理装置とメモリとを含む半導体試験装置
において、複数のテストステーシヨンを設け、こ
れらの各テストステーシヨンに各専用のデータバ
ツフアと入出力装置とを付属させるようにしたこ
とを特徴とする半導体試験装置。
1. A semiconductor testing device including a central processing unit and a memory, characterized in that a plurality of test stations are provided, and each of these test stations is attached with its own dedicated data buffer and input/output device.
JP1001685U 1985-01-29 1985-01-29 Pending JPS61127469U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1001685U JPS61127469U (en) 1985-01-29 1985-01-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1001685U JPS61127469U (en) 1985-01-29 1985-01-29

Publications (1)

Publication Number Publication Date
JPS61127469U true JPS61127469U (en) 1986-08-09

Family

ID=30490809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1001685U Pending JPS61127469U (en) 1985-01-29 1985-01-29

Country Status (1)

Country Link
JP (1) JPS61127469U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01291440A (en) * 1988-05-18 1989-11-24 Tokyo Electron Ltd Wafer prober

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01291440A (en) * 1988-05-18 1989-11-24 Tokyo Electron Ltd Wafer prober

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