JPS61127222A - Pulse generator - Google Patents

Abstract

PURPOSE:To obtain plural sets of output pulses without complicating the constitution by using a memory circuit in place of a counter deciding a pulse width and a pulse interval, setting the memory circuit so that each bit corresponds to each output pulse and scanning an address corresponding to a time axis of the memory circuit in a prescribed time. CONSTITUTION:In an address switch 19, the content of an address counter 18 inputted to a terminal B is outputted from a terminal Q to make address designation for a memory circuit 24. In writing information to the circuit 24, an operation control circuit 1 transmits information 3 to a data register 16 generated from a gate circuit 22 by using a Q output of an FF21 and an inverted reference clock 2b and the said information is written in the circuit 24. Each count of the address counter is fed to the circuit 24 through the switch 19 and the address is scanned sequentially at each cycle of a clock 2a. An output of the circuit 24 is fed to output pulse generating FF25-1-25-n. When one output of the FF25 goes to H, an output of an output effective pulse detection circuit 26 goes to H, and an output of a gate circuit 28 is a write pulse to the circuit 24.

Description

[Detailed description of the invention] [Field of application for sedentary work] This invention not only generates a constant pulse with a constant repetition frequency, but also changes the pulse width and pulse interval aperiodically for each pulse generation. The present invention relates to a pulse generator capable of

[Conventional technology]

An example of this type of device is an atta, as shown in Figure 4.

In the figure, (1) is an arithmetic control circuit, (2) is a reference clock generation circuit used to determine the pulse interval of the desired output pulse and pulse 1 error, etc., and (2a) is a reference clock generation circuit (2). ′ output clock, (3
) is the pulse interval and pulse @ from the arithmetic control circuit (1).
Data line to be determined, (4) is data line (3)
(5) is a pulse width strobe signal indicating that the content of data line (3) is a pulse width, (6) is a data line input to terminal 1. The contents of (3) are input to terminal T, the pulse interval register is stored as a pulse interval strobe signal (4), and the contents are output from terminal Q. (7) is the data line (3) input to terminal Pulse width strobe signal (5) that inputs the contents of to terminal T
This is a pulse width register that stores the contents at terminal Q and outputs the contents from terminal Q.

(8) is a pulse interval down counter, and terminal E is l'-
When the terminal RI is at the "H" level and the terminal is at the "L" level, it counts down every reference clock (2a) input to the terminal T, and when all bits of the contents reach the rLJ level, the "H" level is output from the terminal CO. When the signal is output and the terminal R is at rI (J level, the contents of the terminal Q of the pulse interval register (6) input to the terminal DVc become the counter value at the input of the reference clock (2a). 9) is a pulse width down counter manufactured in the same manner as the pulse interval down counter (8).

(10) is a pulse output flip-flop, the output of the terminal CO of the pulse interval down counter (8) is input to the terminal J, and the output of the terminal C of the pulse width down 7 counter (9) is input to the terminal K.
The output of O is inputted, the reference clock (2a) is inputted to terminal T, and the output is sent out from terminal Q. 1 is a pulse generation completion flip-flop, the output of the terminal CO of the pulse width down counter (9) is input to the terminal J, the reset command signal of the arithmetic control circuit (1) is input to the terminal K, and the output of the terminal CO of the pulse width down counter (9) is input to the terminal K. The reference clock (2a) is input,
It is configured to send the output of the terminal Q to the circuit (1).

(131 is the output of the pulse output flip-flop σ■,
is the desired output pulse. The pulse output flip-flop (101) and the pulse generation completion flip-flop l are so-called J- flip-flops, and when both terminals J and K are at "H", the reference clock (2
With the arrival of a), the state is reversed, and terminal J becomes rI (J and terminal K
When rLJQ, terminal Q becomes 1 upon arrival of reference clock (2).
4J, at the end Q becomes rLJ level, and when terminal J is rLJ and terminal K is "H", the arrival of the reference clock (2a) causes terminal Q to become l'-LJ and terminal Q becomes "H" level.

Next, the operation will be explained. A timing chart showing the operation of FIG. 4 is shown in FIG.

The pulse interval down counter (8) is connected to the reference clock (2a
) counts down each time the pulse (Fig. 5 (A)) is input, and when the value reaches O (Fig. 5 Φ)), the terminal C
O becomes "H" level (Figure 5 (C)).

With this “H” level signal, the reference clock (21
! (7) Due to the arrival of the pulse), the pulse output flip-flop 1α is activated, and the output pulse l becomes the "H" level (FIG. 5, 0). At the same time, the contents of the pulse interval down counter (8) become the contents of the pulse interval register (6) (value 11 in FIG. 5).

On the other hand, the pulse width down counter (9) performs an operation of counting down every time the reference clock (2a) arrives while the output pulse l of the flip-flop (10) is at the "H" level. And this pulse width down counter (9)
When the content of becomes 0 (FIG. 5 (g)), the terminal CO becomes rf (J level (FIG. 5 0)).

This "H" level signal is supplied to the terminal on the pulse output flip-flop side and to the terminal J of the pulse generation completed 7 flip-flop I, so when the next reference clock (2a) pulse arrives, the output pulse (13) is The level becomes "L", and the terminal Q of the pulse generation completion flip-flop l becomes "L".
H level (Fig. 5g)). Output pulse (131
is supplied to the terminal E of the pulse width down counter (9), so when the output pulse date reaches the rLJ level, the operation of the pulse width down counter (9) stops. The arithmetic control circuit (1) detects that the terminal Q of the pulse generation completion flip-flop (1]) has become "H" level, and knows that the output pulse (2) has been generated.

When it is desired to change the pulse interval and pulse object, the arithmetic control circuit (1) puts one shift on the data line (3),
Sends pulse interval strobe (4) (Figure 5 0) and pulse width strobe signal (5) (Figure 5 (I>)) to register pulse interval register (6) and pulse width register (7).
11 (each 15.7 in FIG. 5(K)) is stored in the memory. Then, the arithmetic control circuit (1) sends a reset command signal 1121 (Fig. 5 (J)) and register +61.
, informs that the value setting for (7) has been completed.

As a result of this reset command signal t121, the terminal Q of the pulse generation completion flip-flop becomes rLJ level. The pulse interval register (8) continues to operate, but when its value becomes 0, its terminal CO becomes "H" level again. Due to this "H" level signal, when the next reference clock (2a) pulse arrives, the output pulse Ω becomes "
At the same time, the pulse interval down counter (8) and pulse width down counter (9) are set to the pulse interval register (6) and pulse width register (7), respectively.
) are set (15 and 15 respectively in the example in Figure 5).
7). The above operations are repeated to generate pulses having arbitrary pulse intervals and pulse widths as shown in FIG.

[Problem that the invention seeks to solve]

Since the conventional pulse generator is configured as above,? J! In order to obtain the pulse output of IIK, each circuit other than the arithmetic control circuit (1) in FIG. 4 is required to have a quantity equivalent to the number of pulse outputs to be obtained.

Also, to obtain one pulse output, a register and a counter are used. Therefore, K, which handles a plurality of sets of pulse outputs, has the disadvantage that the scale of the circuit becomes large.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and provides a pulse generator that can easily obtain multiple output pulses without complicating the configuration or increasing the circuit scale. is intended to provide.

[Means for solving problems]

The pulse generator according to the present invention uses a memory circuit in place of a counter that determines the pulse width and pulse interval, and sets each bit of the memory circuit to correspond to each output pulse, and corresponds to the time axis of the memory circuit. The address is scanned over a fixed period of time.

[Effect]

In this invention, the contents of a data register that temporarily stores information from an arithmetic control circuit are sequentially stored in a memory circuit, and the memory contents are scanned and read out every reference clock and sent to an output pulse generating flip-flop. When one of the plurality of sets of output pulses is determined to be valid, an output pulse is created by this flip-flop.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, in which parts that are the same as those in the conventional system are given the same reference numerals and explanations thereof will be omitted.

In Figure 1, (2b) is an inverted reference clock that is the inverted reference clock (2a), (one is a data line (3)
A data strobe indicating that the content of is the data to be written into the memory circuit t241Kl (to be described later). Address strobe indicating that the address is for the data line (161 is the data line (3
) is a data register that temporarily stores the contents of the data line (3) as convolution data to the memory circuit (2) described later using the data strobe I, and αη is a data register that temporarily stores the contents of the data line (3) as an address to the memory circuit example using the address strobe α9. The decoy is an address counter, which indicates the address to be used when reading information from the rear memory circuit and generates a pulse, and at the same time always performs a count-up operation using the reference clock (2a). It looks like this.

α9 is an address switch in which the contents of terminal A appear on terminal Q when terminal S is "H", and the contents of terminal B appear on terminal Q when terminal S is l'-LJ. This is to switch the contents of .

3 is an OR circuit, and when the output of the reference clock (2a) or the output valid pulse detection circuit) is at the "H" level, the output is also at the "H" level. (21) samples the data strobe α input to the terminal J using the reference clock (2a), and when the terminal J is rf (J,
A data strobe synchronous flip-flop that outputs "L" from the terminal Q when the terminal J is rLJ, @ is the reference clock (2b), a data strobe synchronous flip-flop (211 and a two-man NAND gate to be described later) When the output of the circuit is both “H” and Q, the output is rL.
The 3-man-powered NAND gate circuit J is composed of a data strobe synchronous flip 70 block (2υ, 3-man-powered NAND gate circuit), etc., and is a memory write creation circuit that creates a signal to the Me4 circuit example described later. An example is a memory circuit.When the output signal of the memory write creation circuit, which is the input signal to the terminal W, is "H" or "Q", the output of the data switcher (described later), which is the input signal to the terminal, is "H" or "Q". Data is written and stored in the address specified by the output of the address switch αl, which is the input to the terminal A, and when the input to the terminal W is rLJQ, the contents of the address specified by the input from the terminal are read out. The contents are output from terminals 01+01, . . . , On.

(25-i) to (25-n) sample the signal at terminal 01, which is the output of the circuit example inputted to the terminal, using the inverted reference clock (2b) inputted to the terminal T, and This is an output pulse flip-flop that outputs an output pulse (13-1) from Q. Note that the data in the memory circuit (to) consists of n bits, and the terminal also has n bits. The terminals A, B, and Q of the memory input data register and the terminals A, B, and Q of the data switch each have n bits. Terminal A of the memory circuit (to) is composed of m bits, and is terminal A on the address switch side.

B, Q, the terminal Q of the memory read address counter 18), and the terminals X of the memory write address register A each have m bits.

In case ①, any one of the first output pulse (13-1) to the nth output pulse (13-n) is "H".
If so, it is an output M effect pulse detection circuit that sets the output to "H", and if it is, it is a data switch that switches between the contents of the data register (16) and "0".

When both the output of the output valid pulse detection circuit ■ and the inverted reference clock (2b) are "H" and Q, the output is set to rLJ, and the 3-man NAND gate circuit (support) and the 2-man NAND gate circuit When either the output of the 3-person NAND gate circuit (■) or the output of the 2-person NAND gate circuit (2) is "L", the output is r.
Figure 2 is an inverting circuit that inverts the output level of the two-man NAND gate circuit that makes LJ, and the output level of the three-man NAND gate circuit and applies it to the terminal of the data strobe synchronous flip 70 Tsubu Co., Ltd. 3 is a timing chart showing the timing relationship of the signals shown in the figure. The operation will be explained below with reference to FIGS. 1 and 2.

During the "H" level of the reference clock (2a) (Fig. 2 (A)), the memory write time is the "H" level of the reference clock (2a).
The period during the "L" level is the memory lead time. That is, the content is read from the memory circuit (to) while the reference clock (2 &) is "L", and the content is read to the memory circuit (to) while the reference clock (2a) is [HJ]. .

Correspondingly, the address input to the memory circuit [with] is the memory read address while the reference clock (2a) is RF (J), and the memory write address while the reference clock (2a) is "L". address switch αg)
Let's do it. That is, by inputting the reference clock (2a) to the terminal S on the address switch side via the OR circuit ■, while the reference clock (2a) is "H", TR is the address counter input to the terminal B. The contents of U address the memory circuit (to) from terminal Q (second
figure))). While the reference clock (2a) is rLJ, tw is
The contents of the address register α input to the terminal A specify the address from the terminal Q to the memory circuit. (Figure 2 (C)).

When information is stored in the memory circuit example, the arithmetic control circuit (1) puts the information on the data line (3) and outputs the data strobe (
14 and the data register (161&C), and the data register (161 temporarily stores the information).The data strobe signal (141 (FIG. 2 (G)) is input to the data strobe synchronous flip-flop (G).
As shown in FIG. 2, sampling is performed at the rising edge of the reference clock (2a). This output and the inverted reference clock (2b) are generated by a three-person NAND gate circuit @ as shown in Figure 2 (
Create a pulse to the memory circuit (to) shown in I). (This pulse is valid at rLJ) and the contents of the data register (1ω are written into the memory circuit example).

The address counter decoy always increments the flag one by one at the rising edge of the reference clock (2&) (however, if all bits become "1", then they become "0"). This value is set to "H" of the reference clock (2a) by the address switch αω.
During this period, the address of the memory circuit (to) is supplied. In this way, memory addresses are sequentially scanned every cycle of the reference clock (2a). Memory circuit (to) output 01
M
1) to (25-n). In FIG. 2(g), only output 01 is shown. Output pulse creation flip-flop (
In steps 25-1) to (25-n), the contents read from the memory circuit (to) are sampled at the rising edge of the inverted reference clock (2b). Then, an output pulse 03 as shown in FIG. 2 is obtained.

If the pulse interval of the reference clock (2a) is tz1, and the difference in addresses for entering "1" into the example memory circuit is AI, then the pulse interval of the output pulse q3 is tl-AI. The number of consecutive addresses that are entered as "1" in the memory circuit (to) is B.
1, the output pulse (pulse width of 131 is tl・B
It is l.

Since the capacity of the example memory circuit is limited to M, if pulses are to be generated constantly, the memory contents must be constantly updated from the arithmetic control circuit (1). A flowchart for updating is shown in FIG. If the memory capacity (number of addresses) of the memory circuit (to) is N, the pulse interval of the output pulse is t
, e is a flowchart in the case where N is smaller than N. Although address countering is always in operation, the count value Aa is the one at the time when the arithmetic control circuit (1) reads this value.

The value of a is a constant larger than the value that the address counter (18) advances from when the arithmetic control circuit (1) reads the contents of the address counter until it sets the data in the data register (to). The αθ value is used to calculate the memory address that sets the output pulse date to the “H” level.
” This is the difference from the previous memory address when the level was increased. In the example of Fig. 2, the value of α is α=AI (value of 3 in the figure),
α=3. α=2. It changes sequentially with α=1. Ac+a
The number of bits for the A+α operation is the same as that for address countering, and overflow in the operation is ignored. In this way, the arithmetic operation and the movement of address countering can be correlated. Then, the content of the memory circuit example is changed while constantly comparing the calculation result A and the 1@ of the address counter ttS, and the latest output pulse 1
Outputs 31. The contents of the example memory circuit are changed only at the addresses corresponding to the generation of the output pulse, and the contents of the addresses not corresponding to the generation of the output pulse are not changed.

In FIG. 3, at the initial time, the processing step (101
) reads the contents of the address counter (18) and sets this value as Ac. Further, in the processing step (102),
Enter the value of Ac in C as well. Put 00 value in ■. In processing step (103), the value obtained by adding Ac1Ca is stored in A.

In the judgment step (104), it is judged whether I=0, and initially I
= 0, so in the judgment step (105) A ) A
Check c. If there is no overflow in the operation of Ac+a, it is A) Ac, and if there is an overflow, it is A (Ac) in the decision step (106). If A) Ac, that is, address counter + 18111') fl[ If there is enough time before all become "1", A
The value is stored in the address register t171 in the arithmetic control circuit (1).
Set from In processing step (108), the memory contents for this address are read and this value is set as MD. In a processing step (109), only the MD pitch n is set corresponding to the output signal of the nth book, and in a processing step (110), this result is set in the data register mark from the arithmetic control circuit (1). Thereafter, as previously explained, the contents of the data register 06) are stored in the memory circuit (to) by hardware. Next, in a processing step (111), the value of α is set using the arithmetic control circuit (1).
A series of i corrections is stored, for example, in a memory in the arithmetic control circuit (1). ), in the processing step (112),
In order to temporarily memorize the previous value of A, change this value to B.
Put it in. After that, in the processing step (113), calculate α to A, and put the result in A, 0 judgment step (114)
If the calculation A≦B1, that is, A+α, overflows, if I−I I−1 is not established in processing step (115), I=O is determined in processing step (116). In the processing step (117), the value of the address counter ugJ is read, and in the judgment step (118), if this value is smaller than the previously read value C, that is, all address counter decoy values have passed "0". If so, the judgment step (119
), I=0, and unless I=0, the value of I is not changed. In a processing step (120), this value Ac is put into C. Then, return to the original state and check the magnitude relationship between I=0 and A and Ac. To solve this problem, it is checked whether the 1@ of the address to be set is moved by the address counter (181) or whether the setting is decreased.

Note that if any of the output pulses (13-1) to (13-n) becomes "H" (pulse present), the output of the output valid pulse detection circuit Kasumi is not "H", and the two-person canand gate circuit The output of ■ is r when the inverted reference clock (2b) is “H”.
Become LJ. This becomes a write pulse to the memory circuit (to) via the two gate gate circuit prisoners. At this time,
The address of the memory circuit is I of address counter u81.
There is one in which the output pulse is enabled by EL, and the data is added to the memory circuit after the content of bomb B, ie, "0", is switched by data booster α11. In this way,
The P-3 valley of the address that issued the output pulse is immediately rOJK.
cleared.

In addition, the above actual 21? lI? In 11, only the address that outputs the output pulse D and its contents are shown)LltllJ-Circuit (1) to the memory circuit (to), and the contents of the address where the output pulse date has been output are immediately set to "0". , until the memory read address counter (11111 next reaches its address 111t, the operation g 1tI11-circuit (
From 1), each of the memories may be set to "0".

〔Effect of the invention〕

As described above, this output Ej14Vc bias is achieved by making the valley bit of the memory circuit correspond to each output pulse, and by changing the address corresponding to the time of the fiber memory circuit at a fixed time, the output from the memory [gl path is rlJ of each bit,
rOJ for each pulse No. 16 "h".

Since it is compatible with rLJ, even if multiple sets of output pulses are required, there is no need to prepare multiple sets of pulse width counters, pulse interval counters, etc., and the device can be miniaturized.

[Brief explanation of drawings]

1 is a block diagram of a pulse generator according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the pulse generator of FIG. 1, and FIG. 3 is a block diagram of the pulse generator of FIG. 1. Figure 5 is a timing chart for explaining the operation of the conventional pulse generator, Figure 6 is a diagram of the conventional pulse generator. FIG. 3 is an explanatory diagram of output pulses obtained from the device. (1)...Arithmetic control circuit, (2)...Reference clock generation circuit, (161...Data register, llTl:
...Address register, u81...Address counter, (191...Address switch, ■...Memory write creation circuit, (to)...Memory circuit, (25-1)~
(25-n)...output pulse creation flip-prop,
Mother: Output valid pulse detection circuit, M: Data switch. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1), n bits (n = 1, 2, 3, ... integer), m
A memory circuit with a capacity of words (m = 1, 2.3, ... integer), an address register and an address counter for specifying addresses to the memory circuit, and an output pulse that outputs the contents of the address counter and address register. an address switcher that switches the address of the memory circuit according to whether it is valid or not; a data register that temporarily stores the data in order to designate write data to the memory circuit; 0", an arithmetic control circuit that sets data to the address register and data register and controls the address switching, and a write command signal to the memory circuit based on the data setting command signal and the presence or absence of an output pulse. A memory write creation circuit that creates a memory write circuit, an output pulse creation flip-flop that creates an output pulse by sampling the content read from the memory circuit according to a reference clock, and when any of the output pulses is "H", A pulse generator comprising an output valid pulse detection circuit that determines whether an output pulse is present.