JPH0574098B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a sequential control circuit with conditional judgment using control memory.

<Prior Art> Conventionally, conditional sequential control circuits have been widely used in digital devices whose operations are determined and changed depending on the status of peripheral devices.

FIG. 2 is a block diagram showing an example of the configuration of a conventionally used conditional order control circuit.

In FIG. 2, 201 is a control memory (Control memory).
Store (hereinafter referred to as CS), and outputs a digital value of L bit width to the output lines D ₀ to D L-1 according to the digital value added to the M+N bit address input A ₀ to _{A M+N -1.} do.

Reference numeral 202 denotes an auxiliary memory (Pipeline Register; hereinafter referred to as PLR), which inputs and stores the values applied to the D ₀ to D _L-1 inputs according to the pulses applied to the CK input, and also outputs the values from the output lines Q ₀ to Q Output to _L-1 .

211 is a control output line group of LM bits;
212 is a next address line group of M bit width that specifies the next address of CS 201, and is the output line Q ₀ of PLR 202.
~Q _M-1 is connected to address inputs A ₀ ~ _{A M-1} of CS201. Reference numeral 221 represents a group of N-bit condition input lines applied from peripheral devices, which are connected to address inputs A _M to A _M+N-1 of CS 201, and 222 represents a clock input line applied from the outside.

Next, the operation of the circuit configuration shown in FIG. 2 will be explained.

When a clock pulse is applied to input line 222, the memory contents of PLR 202 are updated and the output line
Output to Q ₀ ~Q _L-1 . Some L-M bits of the output of the PLR 202 are output to the peripheral device from the control output line group 211, and the remaining M bits are output to the next address line group 212.
Then, the M bit of the address input of CS201 is specified. On the other hand, the status is input from the peripheral device through the condition input line group 221, and the N bits of the address input of CS 201 are specified. As a result, CS20
The digital values to be applied to the address inputs A ₀ to _{A M+N-1} of 1 are determined, and in response to this, the CS 201 outputs digital values of L bit width to the output lines D ₀ to D _L-1 . When the next clock pulse is applied to input line 222, PLR 202 updates its memory to the digital value previously output from CS 201.
The values of the control output line group 211 and the next address line group 212 are changed.

By repeating the above operations, a series of predetermined signals are output from the control output line group 211,
Control peripheral devices. This realizes a sequential control circuit.

Here, if the state of the peripheral device changes due to some event, the digital value input from the condition input line group 221 changes. This allows CS
The value of the N bits of the address input of CS201 has changed, and the entire digital value added to the address inputs _A0 to _{A M+N-1} of CS201 has also changed, so the state of the peripheral device has not changed. Compared to the case, CS201 outputs different values at different addresses from the output line D ₀ to
Output to D _L-1 . Upon input of the next clock pulse, the PLR 202 inputs and stores this different value, and outputs it to the control output line group 211 and the next address line group 212. As a result, a series of control output line groups 211
The order of the output signals of the output signal branches into a different order in response to a change in the state of the peripheral device. This forms a sequential control circuit with conditional judgment.

<Problems to be Solved by the Invention> The conditional order judgment control circuit realized by the configuration shown in FIG. 2 described above has the following two problems.

The first point is the difficulty in creating digital values that are preset in the CS 201.

That is, in a circuit like the one shown in FIG. 2 using control memory, each value of the address input lines A ₀ to _{A M+N-1} corresponds to the control output line group and the next address line group in advance. (hereinafter referred to as a program) must be set in advance. When creating this program, care must be taken to avoid errors or unnecessary pulses in the series of data output from the control output line group. However, it is generally impossible to predict when and how the status of peripheral devices will change, so
Of the address input to CS201, N bits are considered to be undefined. Therefore, it is necessary to generate the signals of the control output line group in the assumed order while including such uncertain elements, which makes programming extremely difficult and complicated.

The second point is timing instability.

In CS201, input the address A ₀ ~ _{A M+N-1}
After the address is given, the digital value corresponding to the address is output to the output lines D ₀ to _{D L-1} , and it takes a certain amount of time (hereinafter referred to as access time) until it is finalized. As mentioned earlier, it is generally unknown when and in what form changes in the status of peripheral devices occur.
Therefore, there is a good chance that the state of the peripheral device will change just before the clock input to PLR 202.
In this case, due to a change in the state of the peripheral device,
Part of the address inputs A ₀ to _{A M+N-1} of the CS 201 changes, and thereby the values output to the output lines D ₀ to _{D L-1} also change. And within the access time
When a clock input is applied to PLR202,
There is a risk that the PLR 202 may input and store the undetermined value output from the CS 201 and output an erroneous signal to the control output line group 211. This may cause malfunction.

The present invention was devised in view of the above-mentioned problems, and aims to provide a sequential control circuit with conditional judgment that eliminates programming difficulties and timing instability. There is.

<Means for Solving the Problems> In order to achieve the above object, the sequential control circuit with conditional judgment of the present invention has a control memory that outputs parallel digital values of multiple bit widths according to addresses specified by each part. , an auxiliary memory for storing and outputting parallel digital values output from the control memory by inputting an external control signal; and an auxiliary memory storing and outputting parallel digital values output from the control memory by inputting an external control signal; and a condition memory for output, and is configured such that the storage operations of the 1 to N condition memory devices are controlled by 1 to N bits of the output signal of the auxiliary memory.

<Operation> With the above-described configuration, uncertainty in address designation for the control memory is removed, programming becomes easy, timing instability is eliminated, and there is no fear of malfunction.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

In FIG. 1, 101 is a control memory (Control memory).
Store (hereinafter referred to as CS), and outputs a digital value of L bit width to the output lines D ₀ to D L-1 according to the digital value added to the M+N bit address input A ₀ to _{A M+N -1.} do.

Reference numeral 102 denotes an auxiliary memory (Pipeline Register; hereinafter referred to as PLR), which inputs and stores the values applied to the D ₀ to D _L-1 inputs according to the rising edge of the pulse applied to the CK input, and also outputs the output line Q ₀ ~
Q Output to _L-1 .

111 is a control output line group of L _- M-N bits, 112 is a next address line group of M bit width that specifies the next address of CS101, and the output lines of _CS101 are Connected to address inputs A ₀ to _{A M-1} .

121 is a group of N-bit condition input lines applied from peripheral devices, and 122 is a clock input line applied from the outside.

131 to 13N are D-type flip-flops (hereinafter referred to as
When the two inputs of CK1 and CK2 both become "1", the rising edge causes the value added to the D input to be input and stored, and output to the output line Q.

141 is a group of N-bit wide condition input permission lines, which are connected to DFF1 from the output lines Q _M to Q _M+N-1 of PLR102.
31 to 13N are connected to the corresponding CK2 inputs.

142 is a group of condition lines with a width of N bits, and DFF
The Q outputs of 131 to 13N are connected to address inputs A _M to A _M+N-1 of CS 101.

143 is an inverting amplifier (hereinafter referred to as INV), its input is connected to the clock input line 122, and its output is connected to all clock input lines of DFFs 131 to 13N.
Connected to 1 input.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be explained.

The rising edge of the clock pulse applied to input line 122 updates the memory contents of PLR 102 and outputs them to output lines Q ₀ -Q _L-1 . PLR
A part of the L-M-N bits of the output of 102 is output to the peripheral device from the control output line group 111, and a part of
The bits pass through the condition input permission line group 141 and are output to DFF.
131-13N clock inputs. First, for convenience, it is assumed here that all values of the condition input permission line are "0". The remaining M bits pass through the next address line group 112 and designate the M bits of the address input of CS 101. On the other hand, the storage contents of each of DFFs 131 to 13N specify N bits of the address input of CS 101.

This determines the digital value to be added to the address input A ₀ to _{A M+N-1} of CS101, and accordingly
CS101 is the output line for the digital value of L bit width.
Output to D ₀ ~ _{D L-1} . Next clock input line 12
Due to the rising edge of the clock input to
The stored contents of the PLR 102 are updated to the digital values previously output from the CS 101, and the values of the control output line group 111, the next address line group 112, and the condition input permission line group 141 are changed.

By repeating the above operation, a series of predetermined signals are output from the control output line group 111,
Control peripheral devices. This realizes a sequential control circuit.

Furthermore, when the state of the peripheral device changes due to some event, the value of the corresponding 1 bit in the condition input line group 121 changes. Further, when the signal on the corresponding condition input permission line group 141 becomes "1" and a falling edge of the clock input is applied to the clock input line 122, the corresponding one of the DFFs 131 to 13N updates its memory contents. This results in
The value of the N bit of the address input of CS101 is different from before, and therefore, if the state of the peripheral device does not change, or if the signal of the corresponding condition input permission line 141 is "0" Compared to , CS101 outputs different values at different addresses from output line D ₀ to
Output to D _L-1 . At the next rising edge of the clock input, the PLR 102 inputs and stores this different value, and the control output line group 111, the next address line group 112,
It is output to the condition input permission line group 141.

As a result, the order of the output signals of the series of control output line groups 111 is changed to another different order because the state of the peripheral device changes and the value of the corresponding condition input permission line 141 is "1". It becomes branched into. This forms a sequential control circuit with conditional judgment.

Here, since the signals applied to the address inputs A _M to _{A M+N-1} of the CS101 are the Q outputs of the DFF131 to 13N, that is, the memory contents, the signal applied to the address inputs A M to A M+N-1 of the CS101 is It does not continue to change the value added to the address input A _M to A _M+N-1 . If you want to branch as before, set the value of the corresponding condition input permission line 141 to "1",
DFF13 that corresponds to the contents of peripheral device status changes
I have to import it into i and have it memorized. Conversely, if branching is not desired regardless of the state of the peripheral device, it is sufficient to set the value of the corresponding condition input permission line 141 to "0". Therefore, there is no uncertainty regarding the N-bit width value added to the address inputs A _M to _{A M+N-1} of the CS 101, and the program work for setting data in the CS 101 becomes extremely easy.

Furthermore, the contents of the DFFs 131 to 13N are updated at the timing of the rising edge of the CK1 input, no matter at what timing the status of the peripheral device changes. Here, since all CK1 inputs are supplied from clock input 122 through INV143, DFF131 to 13N
The update of the memory contents of the PLR 102 and PLR 102 are synchronized with a shift of half a clock cycle. As a result, from updating the contents of DFF131 to 13N, PLR
The half-cycle period between 102 content updates is CS
The values of address inputs A ₀ to _{A M+N-1} of CS 101 are fixed, and CS 101 can operate stably. Therefore, the L-bit width data input and stored in the PLR 102 does not include any uncertain elements.

<Effects of the Invention> As described above, according to the present invention, the programming work of the control memory becomes easy, and the timing instability in the operation of the control memory is also eliminated, thereby eliminating the risk of malfunction. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing an example of a conventional sequential circuit with conditional judgment. 101... Control memory, 102... Auxiliary memory,
111...Control output line group, 112...Next address line group, 121...Condition input line group, 122...Clock input line, 131-13N...D-type flip-flop, 141...Condition input permission line group, 142 ……
Condition line group, 143...Inverting amplifier.

Claims (1)

[Scope of Claims] 1. A control memory that outputs parallel digital values of a plurality of bit widths according to an address specified from the outside; and a control memory that stores parallel digital values output from the control memory by inputting an external control signal. an auxiliary memory for outputting, and a condition memory for storing and outputting 1 to N condition signals inputted from a peripheral device by inputting an external control signal; 1. A sequential control circuit with condition judgment, characterized in that it is configured such that storage operations of 1 to N condition storage devices are controlled by 1 to N bits.