JPS61125152A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To relax a stepped in the surface of an insulating layer, and to improve the reliability of a wiring by selectively forming a thermal oxide film into a region, in which there are a number of layers, in the upper surface of a substrate, removing the thermal oxide film to shape a recess and forming the wiring in the recess. CONSTITUTION:A thermal oxide film 9 is formed to a memory cell region 2 section. An silicon nitride layer 8b and an silicon dioxide layer 8a and the oxide film 9 are removed through etching to shape a recess 10. A memory cell, a peripheral cir- cuit and a wiring are formed onto a substrate 1a. Consequently, a stepped section shaped on a boundary section between the region 2 and a pheripheral circuit region 3 is made largely smaller than that in a conventional insulating layer. Accordingly, the reliability of the wiring is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a semiconductor device in which a circuit having a region in which the number of wiring layers differs depending on the position on a semiconductor substrate is formed. Concerning methods for manufacturing integrated circuits.

2. Description of the Related Art As semiconductor integrated circuits (ICs) become more highly integrated, there is a tendency for wiring layers on semiconductor substrates to become multilayered.

At this time, the number of wiring layers is not necessarily the same over the entire area of the board. If there are regions with different numbers of layers, a level difference will occur in the wiring layer that crosses the true area, but it is desirable that the level difference be alleviated when forming wiring.

[Prior Art and Problems to be Solved by the Invention] For example, an example of multilayer wiring in a highly integrated memory IC is shown in FIG. 2, which is a side sectional view.

In the figure, 1 is a silicon (Si) substrate, 2 is a memory cell area, 3 is a peripheral circuit area outside of it, and 4a to 4.
c is an intra-region wiring in the memory cell area 2, 5 is an intra-region wiring in the peripheral circuit area 3, 6 is an insulating layer that insulates the intra-region wirings 4a to 4c and 5, and 7 is an insulating layer between the memory cell area 2 and the peripheral circuit area 3. This is an inter-area wiring that connects the

Since the memory cell area 2 accommodates approximately tens of thousands of memory elements in one cell, the wiring within the area is complicated.
As shown in 4c, they are arranged in three layers. In contrast, it is sufficient to arrange the intra-region wiring 5 in the peripheral circuit region 3 in one layer.

Therefore, a step is formed on the surface of the insulating layer 6 at the boundary between the memory cell region 2 and the peripheral circuit region 3.

This poses a problem in that when forming the inter-area wiring 7, it is difficult to ensure a sufficient thickness for the portion that crosses the step, reducing the reliability of the wiring 7 and, by extension, reducing the reliability of the IC. becomes.

[Means for solving problems]

The above problem is that when forming a circuit having a region where the number of wiring layers differs depending on the position on the semiconductor substrate, a thermal oxide film is selectively formed in the region with a large number of wiring layers on the upper surface of the substrate. This problem is solved by the method of manufacturing a semiconductor device of the present invention, in which a film is removed to form a recess, and then wiring is formed in the recess.

[Effect]

If the depression is formed by the above method, the substrate surface in the area with a large number of wiring layers will be lowered in advance, and the surrounding area will be gently sloped, so that the boundary between the area with many wiring layers and the area with a small number of wiring layers will be It becomes possible to alleviate the level difference on the surface of the insulating layer, which has been a problem in the past.

This makes it possible to ensure a sufficient thickness of the part of the wiring that connects the two-headed areas on the surface of the insulating layer that crosses the step, thereby improving the reliability of the wiring, which in turn improves the reliability of the IC. enable improvement.

〔Example〕

Hereinafter, an embodiment of alleviating the level difference in wiring according to the manufacturing method of the present invention will be described with reference to FIGS.

The IC formed in the process shown in FIG. 1 corresponds to the IC shown in FIG. 2.

Prior to forming a circuit on the Si substrate 1, as shown in Figure (a1), the top surface of the substrate 1 is coated with a thickness of approximately 0.0
A silicon dioxide (Si02) layer 8a with a thickness of 5 μm and a silicon nitride (SiN) layer 8b with a thickness of about 0.1 μm are formed thereon by a normal method such as CVD, and the memory cell region 2 portion of the SiN layer 8b is formed. It is removed by a conventional method such as dry etching.

Next, as shown in FIG. 3('b), a thermal oxide film 9 (component: 5 iOz) having a thickness of about 1 μm, for example, is formed in the memory cell region 2 using the SiN layer 8b as a mask. this is,
For example, a conventional method of heating to about 1000° C. in an oxygen (02) atmosphere may be used.

Next, as shown in the figure (C1), the SiN layer 8b and the Si0
The second layer 8a and the thermal oxide film 9 are removed by etching to form a recess 10.
A semiconductor substrate 1a is formed in which a recess 10 is provided in the substrate 1. This etching is preferably wet etching using phosphoric acid (H3PO4) for the SiN layer 8b and hydrofluoric acid (IF) for the SiO2 layer 8a and the thermal oxide film 9, for example.

The periphery of the depression 10 formed in this way is gently sloped, and the inner surface has no residual stress like the upper surface of the substrate 1 (
And it's smooth.

After that, in the same manner as shown in FIG. 2, if memory cells, peripheral circuits, and wiring are formed on the substrate la, the result will be as shown in FIG. The level difference formed at the boundary between the cell area 2 and the peripheral circuit area 3 is significantly reduced compared to the level difference in the conventional insulating layer 6. Therefore, the inter-area interconnect 7a corresponding to the conventional inter-area interconnect 7 is A sufficient thickness is ensured also in the portion that crosses the step, so that reliability does not deteriorate as in the conventional case.

Note that although the above description has been made using a memory IC as an example, the application of the present invention is not limited to the memory tC.

〔Effect of the invention〕

As explained above, according to the manufacturing method of the present invention, the number of wiring layers varies depending on the position on the semiconductor substrate.

When forming a circuit having different regions, the level difference on the surface of the insulating layer at the boundary between the double-headed areas is alleviated, and a sufficient thickness can be ensured for the portion of the wiring connecting the double-headed areas that crosses the level difference. Therefore, it becomes possible to improve the reliability of the wiring, which in turn has the effect of making it possible to improve the reliability of the IC.

[Brief explanation of drawings]

In the drawings, FIGS. 1(a) to 1(d) are side cross-sectional views in the order of steps schematically showing an example of reducing the level difference in wiring by the manufacturing method of the present invention, and FIG. FIG. 3 is a side sectional view schematically showing an example of a step. In addition, in the figure, 1 and la are semiconductor substrates, 2 is a memory cell area, 3 is a peripheral circuit area, 4a to 4c, and 5 are wiring within the area, 6.6
7a is an insulating layer, 7a is an inter-area wiring, 8a is 5
8b is a SiN layer, 9 is a thermal oxide film, and 10 is a depression. Nel 8

Claims (1)

[Claims] When forming a circuit having a region where the number of wiring layers differs depending on the position on the semiconductor substrate, a thermal oxide film is selectively formed in the region with a large number of wiring layers on the upper surface of the substrate, and the thermal oxide film is removed. 1. A method of manufacturing a semiconductor device, comprising forming a recess and then forming wiring within the recess.