JPH0645315A - Semiconductor device and semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having the structure for preventing soaking of etchant into an IC chip and generation of gap and making free from mechanical damage of scribe in such a semiconductor device as having multilayer wirings and particularly using spin-on glass film for interwiring layer insulating layer. CONSTITUTION:In a semiconductor device having a multilayer wiring, a side wall structure thereof is achieved by the process that an interwiring layer insulating layer 25 including a spin-on glass film 10 is formed in the area surrunded by the scribe line S of IC chips 1A, 1B,... and the cross-section of the spin-on glass film 10 is covered with a surface protection insulating film 19 formed on this interwiringlayer insulating layer 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a semiconductor device having good scribe lines.

[0002]

2. Description of the Related Art Conventionally, a plurality of semiconductor integrated circuits (hereinafter abbreviated as IC) formed on a wafer are cut and separated into individual IC chips in a scribing process. During this scribing process, a width of 100
A scribe line of about μm is formed on the substrate surface, and based on this, each IC chip is cut. This scribe line is obtained by removing the isolation insulating film of the IC element, the insulating film for isolating and insulating the wiring layers laminated in multiple stages, the surface protective film, and the like by means of photoetching or the like. Therefore, the substrate surface is directly exposed.

FIG. 4 shows an IC in a conventional semiconductor device.
It is a partial expanded sectional perspective view near the scribe line before cutting the chip. In the figure, 31A and 31B are IC chips before cutting, respectively, which are formed on a semiconductor substrate 32 made of a semiconductor such as silicon single crystal. The four points on the side wall of the IC chip 31A are respectively P _A ,
Q _A , R _A , and T _A , similarly, four points on the side wall of the IC chip 31B are designated as P _B , Q _B , R _B , and T _B , respectively. However, T
_{Since B} is hidden, it is not shown in the figure. In the figure, four points R _A, T _A, T _B, a region connecting the R _B is a scribe lines SS for separating the IC chip 31A and 31B, the length connecting the point R _A and R _B Is the width of this scribe line SS.

The structure will be described below with reference to FIG. 1. However, since the IC chips 31A and 31B have the same structure, the description will focus on 31A. In addition, in the figure,
Although the portions of the IC chips 31A and 31B are illustrated, in reality, a large number of IC chips are formed on the substrate 32 with a scribe line therebetween. Also I
Since the respective elements constituting the C chips 31A and 31B are the same, A and B after the numbers are omitted unless necessary. Three
3 is an isolation insulating film of the IC element, 34 is a lower CVD film, 3
Reference numeral 5 is a spin-on-glass film formed for planarization, 36 is an upper CVD film, and these wiring layers 35, 36 and 36 constitute a wiring interlayer insulating film layer 38. 37 is a surface protection insulating film formed on the wiring interlayer insulating film layer 38.
These insulating films 33, 34, 35 and 36 are sequentially formed and formed for each insulating film by a thin film forming means and a means such as photoetching. Further, the scribe line SS is simultaneously formed every time each insulating film is formed and patterned. At this time, from the side wall surrounded by four points P _A , Q _A , T _A , and R _A on the IC chip 31A, as shown in FIG. The cross section has an exposed structure. The spin-on-glass film 35 is an oxide film formed by applying and baking a solvent containing a silicon compound as a main component, and is formed thin on the convex portion of the wiring and thick on the concave portion. Usually, there is no wiring near the scribe line SS, and the film thickness of the spin-on-glass film 35 formed here is close to the flat portion.

[0005]

In the structure of the scribe line SS in the conventional example, as described above, the cross section of the spin-on-glass film 35 is exposed. For this reason, there is a problem in that during the wet etching, the etching liquid permeates the spin-on-glass film 35 to form voids. The voids reduce the strength, and during the scribing process, the spin-on-glass film in this portion is severely damaged, causing cracks. As described above, the above-mentioned voids generated in the spin-on-glass film 35 have a problem that the yield of the device is significantly reduced.

The semiconductor device of the present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device capable of eliminating the generation of voids in the spin-on-glass film and increasing the yield in the manufacturing process. It is intended.

[0007]

The semiconductor device of the present invention comprises:
The wiring interlayer insulating film layer including the spin-on-glass film is formed into an IC.
The above-mentioned object is achieved by forming a side wall structure that is formed inside the scribe line of the chip and covers the cross section of the spin-on-glass film with an insulating film formed on this wiring interlayer insulating film layer.

[0008]

FIG. 1 is a partially enlarged sectional perspective view of the vicinity of a scribe line before cutting an IC chip in a first embodiment of a semiconductor device of the present invention. Based on the figure, the structure will be mainly described, and the manufacturing method will be comprehensively described in the second embodiment having a more complicated structure. In the figure, 1A, 1B ... IC chips before cutting are formed on a semiconductor substrate 2 such as a silicon single crystal. Each IC
Since the elements of the chips 1A and 1B are the same, A and B after the numeral are omitted unless otherwise necessary. Reference numeral 4 is an isolation insulating film of an IC element, 9 is a lower CVD oxide film, 10 is a spin-on-glass film used for planarization, and 11 is an upper C film.
The VD oxide film, these wiring layers 9, 10 and 11 constitute a wiring interlayer insulating film layer 25. Reference numeral 19 is a surface protective insulating film.
Further, in the figure, the area connecting the four points marked R _A , T _A , T _B (hidden and invisible), and R _B is the IC chip 1A.
Is a scribe line (which may be referred to as a scribe line area) S for separating 1B and 1B, and points R _A and R
_The length connecting with _B is the width of this scribe line S.

Regarding the structure of this embodiment, the IC chip 1A
I will explain mainly. That is, the spin-on-glass film 10, the lower CVD oxide film 9, and the upper CVD oxide film 11
As shown in the same drawing, the lateral cross section of is formed inside the side end surface of the isolation insulating film 4 of the IC element. As shown in the figure, for each side wall portion of the IC chip 1A,
P _A , Q _A , U _A , V _A , W _A , X _A , and lower C
Against the lateral ends of the VD oxide film 9, subjected to Y _A becomes code.

The surface protection insulating film 19 formed on the upper CVD oxide film 11 has three lateral cross sections of the lower CVD oxide film 9, the spin-on-glass film 10 and the upper CVD oxide film 11. And is formed so as to stay inside by a distance U _A , W _A from the side end surface of the isolation insulating film 4 of the IC element. In the figure, the IC chip 1
Although only the right side of A is covered with this surface protective insulating film 19, in fact, not only the left side but also the side end surfaces on the front side and the back side are also covered. As for the IC chip 1B or another IC chip, as shown in FIG.
The reference numeral corresponding to the case is attached. Also, IC
All the contents described for the chip 1A are the IC chip 1B.
The same holds true for.

As described above, the structural feature of the first embodiment of the semiconductor device of the present invention is that the spin-on-glass film 1 is used.
0 and the lower CVD oxide film 9 and the upper CVD oxide film 1
1 is formed inside the side end portion of the isolation insulating film 4 of the IC element, and the VCD oxide film 1 on the upper side.
The surface protective insulating film 19 formed on the first layer 1 covers the spin-on-glass film 10, the lower side CVD oxide film 9 and the upper side CVD oxide film 11 all over the lateral cross section, and the end portion of the surface protective insulating film 19 also forms the IC element. The point is that the isolation insulating film 4 is formed so as to be located inside the side end portion thereof.

As described above, in this embodiment,
Since the cross-section of the spin-on-glass film is covered with the surface protection insulating film 19, it is possible to prevent the etching solution from entering the spin-on-glass film when the bonding pad is wet-etched on the surface protection insulating film 19. It has the advantage of preventing mechanical damage.

Next, as a second embodiment of the present invention, a more complicated and practical example will be given, and based on this, a manufacturing method will also be described. FIG. 2 is a partially enlarged sectional view of the vicinity of a scribe line before the IC chip is cut in the second embodiment of the semiconductor device of the present invention. In the figure, the same elements as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.
In the figure, 1A is one IC chip, 3 is a thermal oxide film for stabilizing the surface of the semiconductor substrate 2, 5 is a polysilicon electrode constituting a gate portion, 8 is an electrode of a source portion and a drain portion. Certain first aluminum wiring, 9, 10 and 11
Together with the first wiring interlayer insulating film layer 25, and 14, 1
5 and 16 are combined to form the second wiring interlayer insulating film layer 26, 1
Reference numerals 3 and 18 are second and third aluminum wirings that connect the gate portion, the source portion, and the drain portion to other portions.

In this embodiment, the cross sections of the spin-on-glass film 10 of the first wiring interlayer insulating film layer 25 and the spin-on-glass film 15 of the second wiring interlayer insulating film layer 26 are
As is clear from the drawing, the spin-on glass film 15 is covered with the surface protection insulating film 19, and the side end portion of the spin-on-glass film 15 is formed inside the end of the scribe line S. Although this point is a feature of this embodiment, the idea is the same as that of the first embodiment.

Next, a method of manufacturing the semiconductor device of the second embodiment will be described step by step with reference to FIG. Figure 3
3A and 3B are diagrams illustrating a method of manufacturing the semiconductor device of FIG. (1) As shown in FIG. 1A, a thermal oxide film 3 and a nitride film 21 are formed on a semiconductor substrate 2, and then an IC element region C is formed.
Also, the nitride film in the portion other than the scribe line region S is removed.

(2) Using the nitride film 21 as a mask, the portion from which the nitride film has been removed is oxidized to form the isolation insulating film 4 of the IC element (see FIG. 2B). Next, the nitride film 21 in the IC element region C and the scribe line region S is removed.
Next, in the IC element region C, an IC element group is formed on the semiconductor substrate 2 by a known element forming means.
Next, a polysilicon electrode 5 is formed, and a wiring interlayer film 6 for separating from a later-described first aluminum wiring 8 is formed (see FIG. 2B).

(3) Since the semiconductor substrate 2 and the polysilicon electrode 5 are connected to the first aluminum wiring 8, a resist pattern 22 having a predetermined shape as shown in FIG.
To form. Reference numeral 7 shown in FIG. 3C is a contact hole for that purpose. Further, since the wiring interlayer film 6 and the thermal oxide film 3 in the scribe line region S are also removed at the same time, there is no resist pattern on the scribe line region S as shown in FIG. Then, photo etching is performed to form the contact hole 7 and the scribe line S as shown in FIG. Next, the first aluminum wiring 8 is formed by photoetching (FIG. 7C).
reference).

(4) Next, in order to separate the first aluminum wiring 8 from the second aluminum wiring 13 shown in FIG. 8E, the first wiring interlayer insulating film layer 25 is formed on the lower side. CVD oxide film 9, spin-on-glass film 10, upper CVD oxide film 1
The three layers are formed in the order of 1 (see FIG. 3D). Next, in order to form the through hole 12 (see FIG. 8E) that connects the first aluminum wiring 8 and the second aluminum wiring 13, first, a resist pattern 23 is formed (FIG. 7D). reference). The chipped portion D of the resist pattern 23 corresponds to the through hole 12. At this time, the first wiring interlayer insulating film layer 25 in the scribe line region S is removed. The region to be removed is a portion indicated by E in FIG. 7D, that is, a range wider than the width of the scribe line S. . Photoetching is performed to remove the first wiring interlayer insulating film layer 25 in a range wider than the width of the through hole 12 and the scribe line S described above (see (e) in the same figure). Then the second
The aluminum wiring 13 is formed by photoetching (see FIG. 8E).

(5) In order to separate the second aluminum wiring 13 and the third aluminum wiring 18 (see FIG. 9G), a second wiring interlayer insulating film layer is formed on the second aluminum wiring 13. 26
The lower CVD oxide film 14 and spin-on-glass film 1
5, the upper CVD oxide film 16 is formed in the three-layer structure. Next, the second aluminum wiring 13 and the third aluminum wiring 1
In order to form the through hole 17 (see FIG. 9 (g)) for connecting with 8, the resist pattern 24 is first formed as shown in FIG. This resist pattern 24
The resist lacking portion G in the inside corresponds to the through hole 17. At this time, at the same time, the second wiring interlayer insulating film layer 26 in the scribe line area S is removed. The area to be removed is shown by F in FIG. 6F, that is, by FIG. It must be narrower than the width of E. By etching, the wiring interlayer insulating film layer 26 in the portions F and G of the resist pattern 24 shown in FIG.

(6) Next, as shown in FIG. 3G, the third aluminum wiring 18 is formed by photoetching. Next, the insulating film 19 that protects the surface of the third aluminum wiring 18 is formed (see FIG. 9G). Next, the bonding pad 20 shown in FIG. 3H and the scribe line region S are etched at the same time. Therefore, as shown in FIG. 9G, a resist pattern 25 having a predetermined shape is first formed. This resist pattern 2
In FIG. 5, the part of the resist which is indicated by H is for the bonding pad 20 and the part of which is similarly indicated for I is for the scribe region S. The width of the portion indicated by reference numeral I needs to be narrower than the resist pattern F in the previous step so as not to expose the lateral cross section of the spin-on-glass film 15. This is shown in (f) of FIG.
It is also clear from FIG.

(7) By forming the scribe line S by the method described above, as shown in FIG.
The lateral cross-sections of the spin-on-glass films 10 and 15 can be covered with the insulating film 19 formed thereon. Although the above description has been centered on the scribe line on the right side of the IC chip 1A, the scribe line is present not only on the left side but also on the front side and the back side, and the same configuration as described above is used. Needless to say. As described above, also in this embodiment, since the cross-section of the spin-on-glass film is covered with the surface protective oxide film, when the bonding pad is wet-etched on this surface protective oxide film, the etching solution is immersed in the spin-on-glass film. Since it is possible to prevent penetration and also to prevent cracks from occurring, there is an advantage that mechanical damage can be prevented. Further, there is a merit that it can be realized without increasing the number of steps.

[0022]

According to the present invention, the spin-on-glass film is formed on the inner side of the scribe line and the lateral cross section of the spin-on-glass film is covered with the oxide film, so that the etching solution can be prevented from soaking into the IC chip. Generation of voids can be prevented, and a highly reliable semiconductor device can be obtained. Also, when scribing the IC chip, it is not mechanically damaged, so that the IC can be manufactured with a high yield.
It has great industrial value because it does not increase the number of processes.

[0023]

[Brief description of drawings]

1 relates to a first embodiment of a semiconductor device of the present invention, I
It is a partial expanded sectional perspective view near the scribe line before C chip cutting.

FIG. 2 relates to a second embodiment of a semiconductor device of the present invention, I
It is a partial expanded sectional view near the scribe line before C chip cutting.

FIG. 3 is a diagram illustrating a method of manufacturing the semiconductor device of FIG.

FIG. 4 is a partially enlarged cross-sectional perspective view of the vicinity of a scribe line before cutting an IC chip according to a semiconductor device of a conventional example.

[Explanation of symbols]

 1, 1A, 1B IC chip 10, 15 Spin-on-glass film 19 Surface protective insulating film (insulating film) 25 First wiring interlayer insulating film layer (wiring interlayer insulating film layer) 26 Second wiring interlayer insulating film layer (wiring interlayer) Insulating film layer) S scribe line

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 29, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

The structure will be described below with reference to FIG. 1. However, since the IC chips 31A and 31B have the same structure, the description will focus on 31A. In addition, in the figure,
Although the portions of the IC chips 31A and 31B are illustrated, in reality, a large number of IC chips are formed on the substrate 32 with a scribe line therebetween. Also I
Since the respective elements constituting the C chips 31A and 31B are the same, A and B after the numbers are omitted unless necessary. Three
3 is an isolation insulating film of the IC element, 34 is a lower CVD film, 3
Reference numeral 5 is a spin-on-glass film formed for flattening, 36 is an upper CVD film, and these wiring layers 34, 35 and 36 form a wiring interlayer insulating film layer 38. 37 is a surface protection insulating film formed on the wiring interlayer insulating film layer 38.
These insulating films 33, 34, 35, 36, 37 are sequentially formed and formed for each insulating film by a thin film forming means and a means such as photoetching. Further, the scribe line SS is simultaneously formed every time each insulating film is formed and patterned. At this time, from the side wall surrounded by the four points P _A , Q _A , T _A , and R _A on the IC chip 31A, as shown in FIG. The cross section has an exposed structure. The spin-on-glass film 35 is an oxide film formed by applying and baking a solvent containing a silicon compound as a main component, and is formed thin on the convex portion of the wiring and thick on the concave portion.
Normally, there is no wiring near the scribe line SS,
The film thickness of the spin-on-glass film 35 formed here is close to the flat portion.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

The surface protection insulating film 19 formed on the upper CVD oxide film 11 has three lateral cross sections of the lower CVD oxide film 9, the spin-on-glass film 10 and the upper CVD oxide film 11. Is covered with the thickness of the distances U _A and Y _A , and is separated from the side end surface of the isolation insulating film 4 of the IC element by the distance U _A.
It is formed so that only _A and W _A stay inside. In the figure, only the right side of the IC chip 1A is covered with the surface protective insulating film 19, but actually, not only the left side but also the side end surfaces on the front side and the back side are also covered. The IC chip 1B or other IC chips are also assigned the same reference numerals as in the case of 1A, as shown in FIG. Further, all the contents described with respect to the IC chip 1A are similarly applied to the IC chip 1B.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

Next, as a second embodiment of the present invention, a more complicated and practical example will be given, and based on this, a manufacturing method will also be described. FIG. 2 is a partially enlarged sectional view of the vicinity of a scribe line before the IC chip is cut in the second embodiment of the semiconductor device of the present invention. In the figure, the same elements as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.
In the figure, 1A is an IC chip, 3 is a thermal oxide film for forming a MOS transistor, 5 is a polysilicon electrode forming a gate portion, 8 is an electrode of a source portion and a drain portion. Aluminum wirings, 9, 10, and 11 are combined to form a first wiring interlayer insulating film layer 25, and 14, 15 and 16 are combined to form a second wiring interlayer insulating film layer 26, 13 and 18 in a gate portion and a source portion. , Second and third aluminum wirings that connect the drain portion to other portions.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

In this embodiment, the cross sections of the spin-on-glass film 10 of the first wiring interlayer insulating film layer 25 and the spin-on-glass film 15 of the second wiring interlayer insulating film layer 26 are
As is clear from the figure, the surface protection insulating film 19 or the insulating film 19 and the insulating film layer 26 are covered, and the side end of the spin-on-glass film 15 is formed inside the end of the scribe line S. It is configured. Although this point is a feature of this embodiment, the idea is the same as that of the first embodiment.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction content]

(7) By forming the scribe line S by the method described above, as shown in FIG.
The lateral cross section of the spin-on-glass films 10 and 15 can be covered with the insulating film 19 or the insulating film 19 and the insulating film layer 26 formed thereon. Although the above description has been centered on the scribe line on the right side of the IC chip 1A, the scribe line is present not only on the left side but also on the front side and the back side, and the same configuration as described above is used. Needless to say. As described above, also in this embodiment, since the cross-section of the spin-on-glass film is covered with the surface protective oxide film, when the bonding pad is wet-etched on this surface protective oxide film, the etching solution is immersed in the spin-on-glass film. Since it is possible to prevent penetration and also to prevent cracks from occurring, there is an advantage that mechanical damage can be prevented. Further, there is a merit that it can be realized without increasing the number of steps.

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1] ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 29, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

1 relates to a first embodiment of a semiconductor device of the present invention, I
It is a partial expanded sectional perspective view near the scribe line before C chip cutting.

FIG. 2 relates to a second embodiment of a semiconductor device of the present invention, I
It is a partial expanded sectional view near the scribe line before C chip cutting.

FIG. 3 is a diagram illustrating a method of manufacturing the semiconductor device of FIG.

FIG. 4 is a diagram illustrating a method of manufacturing the semiconductor device of FIG.

FIG. 5 is a diagram illustrating a method of manufacturing the semiconductor device of FIG.

FIG. 6 is a partially enlarged cross-sectional perspective view of the vicinity of a scribe line before cutting an IC chip according to a semiconductor device of a conventional example.

[Explanation of reference numerals] 1,1A, 1B IC chip 10,15 Spin-on-glass film 19 Surface protective insulating film (insulating film) 25 First wiring interlayer insulating film layer (wiring interlayer insulating film layer) 26 Second wiring interlayer insulating film Film layer (wiring interlayer insulation film layer) S scribe line

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Added

[Correction content]

[Figure 5]

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Added

[Correction content]

[Figure 6]

Claims (2)

[Claims] 1. A semiconductor device having a multilayer structure including a wiring interlayer insulating film having at least a spin-on-glass film and having a structure that can be divided into each IC chip by a scribe line, and at least faces the scribe line of the spin-on-glass film. A semiconductor device having a side surface covered with a surface protective insulating film. 2. A semiconductor element using an IC chip obtained by dividing the semiconductor device according to claim 1 by the scribe line.