JPS61125049A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS61125049A JPS61125049A JP24660184A JP24660184A JPS61125049A JP S61125049 A JPS61125049 A JP S61125049A JP 24660184 A JP24660184 A JP 24660184A JP 24660184 A JP24660184 A JP 24660184A JP S61125049 A JPS61125049 A JP S61125049A
- Authority
- JP
- Japan
- Prior art keywords
- field plate
- organic film
- integrated circuit
- semiconductor integrated
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔座業上の利用分野〕
本発明は半導体集積回路装置に関し、特に高耐圧素子を
有する半導体集積回路装置の表面保@膜の構造に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of practical application] The present invention relates to a semiconductor integrated circuit device, and more particularly to the structure of a surface protective film of a semiconductor integrated circuit device having a high breakdown voltage element.
従来、この種の半導体集積回路装置は誘電体分離された
クリコン単結晶島に形成された素子間を結ぶ配線部は浮
い絶縁膜で構成され、また素子の耐圧特性を向上させる
ためフィールドプレートを備えた素子が形成される。し
かしフィールドプレートの下には薄い絶縁膜を形成する
必要がある。Conventionally, in this type of semiconductor integrated circuit device, wiring sections connecting elements formed on dielectrically isolated Crycon single-crystal islands are composed of floating insulating films, and are also equipped with field plates to improve the breakdown voltage characteristics of the elements. A device is formed. However, it is necessary to form a thin insulating film under the field plate.
上述した構造の半導体集積回路装置の素子の表面は必然
的に高段差部が生じ、こ\に形成した配線は段差部によ
る細りゃ断線を生じる等の不都合金主じていた。The surface of the element of the semiconductor integrated circuit device having the above-mentioned structure inevitably has a high level difference, and the wiring formed thereon is often disadvantageous in that it becomes thin due to the level difference and breaks.
従って、これを防ぐため生じた段差部の角を削除したり
、段をならすために異種の材料を付与するなどの特殊プ
ロセスの追加を必要とし、そのためプロセスが複雑とな
り、歩留り低下を起こし製造上高価な牛寺体装置となる
という欠点がおった。Therefore, in order to prevent this, it is necessary to add special processes such as removing the corners of the stepped portion or applying a different material to smooth out the steps, which complicates the process, lowers the yield, and reduces manufacturing efficiency. This had the disadvantage that it was an expensive Gyuji body device.
本発明は上記欠点を除去し、表面段差部における配線の
細りゃ断線をなくシ、簡易なプロセスにより形成でき歩
留りがよく高品質な誘電体分離法による高耐圧半導体集
積回路を提供することを目的とする。It is an object of the present invention to eliminate the above-mentioned drawbacks, eliminate thinning and disconnection of wiring at surface step portions, and provide a high-voltage semiconductor integrated circuit using a dielectric separation method that can be formed by a simple process and has a high yield and high quality. shall be.
単結晶島にフィールドプレートを備えた高耐圧素子を形
成して構成される半導体集積回路装置において、基板表
面の段差部およびフィールドプレートを埋め込みかつそ
の表面が平坦になるよう塗布された絶縁性有機皮膜と、
該絶縁性有機皮膜に形成され前記フィールドプレートに
達するスルーホールと、前記絶縁性有機皮膜の上に設け
られた金属配線とを有することにより構成される。In a semiconductor integrated circuit device configured by forming a high-voltage element with a field plate on a single-crystal island, an insulating organic film is applied to embed the stepped portion of the substrate surface and the field plate, and to make the surface flat. and,
It is constructed by having a through hole formed in the insulating organic film and reaching the field plate, and a metal wiring provided on the insulating organic film.
次に、本発明の実施例について、図面を参照して説明す
る。第1図は本発明の一実施例の断面図である。Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of an embodiment of the present invention.
第1図に示すように、多結晶クリコン支持層7に保持さ
れ誘電体分離されたシリコン単結晶島1に高耐圧素子を
通常の不純物拡散などにより素子接合部6を形成する。As shown in FIG. 1, a high breakdown voltage element is formed on a dielectrically isolated silicon single crystal island 1 held by a polycrystalline silicon support layer 7, and an element junction 6 is formed by ordinary impurity diffusion.
次いで薄い酸化膜5を形成し、素子接合部に対し開孔し
、次いでフィールドプレート2を形成する。高耐圧特性
を必要とする半導体集積回路装置の場合、フィールドプ
レート2を設置することにより特性の改善が計られるこ
とは公知であり、フィールドプレート1の下に配される
絶縁膜5は十分にフィールドプレート効果を得るために
薄く作られる。Next, a thin oxide film 5 is formed, holes are opened for the device junctions, and then the field plate 2 is formed. In the case of semiconductor integrated circuit devices that require high withstand voltage characteristics, it is well known that the characteristics can be improved by installing a field plate 2. Made thin to obtain a plate effect.
一方シリコン単結晶島1を越え他の素子へ接続される金
属配線層3の下は局部的な耐圧劣化の生じないように浮
い絶縁膜5′を必要とする。本発明においては、厚い絶
縁膜5′および薄い絶縁膜5によって形成される段差部
に対し、フィールドプレート2を含む段差の低い部分と
を塗布法による絶縁性有機膜4によって埋め込み、かつ
塗布条件の選択により表面を平坦にする。On the other hand, a floating insulating film 5' is required under the metal wiring layer 3 which extends beyond the silicon single crystal island 1 and is connected to other elements to prevent local voltage deterioration. In the present invention, the step portion formed by the thick insulating film 5' and the thin insulating film 5 is filled with the low step part including the field plate 2 with an insulating organic film 4 formed by a coating method, and the coating conditions are Flatten the surface by selection.
なお、用いる絶縁性有機皮膜としては、液状ポリイミド
などを使用すれば、材料の粘度および塗布の条件を適当
に選ぶことに、よシ第2図に示すように、低い段部およ
びフィールドプレート2を埋め込むとともに段差部によ
る表面張力効果により制御された埋め込み状態を実現す
ることが可能となり、次工程のスルーホールの形成を容
易ならしめることができる。In addition, if liquid polyimide or the like is used as the insulating organic film, it is recommended to appropriately select the viscosity of the material and the coating conditions to form a low step and a field plate 2, as shown in Figure 2. It becomes possible to achieve a controlled embedding state due to the surface tension effect of the stepped portion while embedding, and it is possible to facilitate the formation of through holes in the next step.
次いで、第1図に示すようにこのように塗布された絶縁
性有機皮膜において、高耐圧素子上に設置された広い面
積をもつフィールドプレートへの接続部とするためのス
ルーホールを形成する。Next, as shown in FIG. 1, in the insulating organic film thus applied, through holes are formed for connection to a field plate having a wide area installed on the high voltage element.
次いで表面に金属配線材料を付着させバターニングする
ことにより金属配線層3を形成する。以上により本実施
例は完成する。Next, a metal wiring layer 3 is formed by attaching a metal wiring material to the surface and patterning it. With the above steps, this embodiment is completed.
以上説明したように本実施例によれは、形成した絶縁性
有機膜に、フィールドプレート上にスルーホールを容易
に作成でき、かつ絶縁性有機膜による段差の効果を減じ
ることにより素子間を接続する金属配線層3は、高い段
差部を介して他の素子に局部的耐圧劣化なしに接続され
、かつ絶縁性有機膜に埋込まれたフィールドプレートは
薄い絶縁膜を介し十分に効果を発揮することができる。As explained above, in this embodiment, through holes can be easily created on the field plate in the formed insulating organic film, and devices can be connected by reducing the effect of steps caused by the insulating organic film. The metal wiring layer 3 should be connected to other elements through high step portions without local voltage deterioration, and the field plate embedded in the insulating organic film should be fully effective through the thin insulating film. Can be done.
以上説明したように、本発明によれば、表面段差部にお
ける配線の細りゃ断線をなくシ、簡易なプロセスにより
形成でき、歩留りがよく、高品質な誘電体分離法による
高耐圧な半導体集積回路装置を得ることができる。As explained above, according to the present invention, thinning and disconnection of wiring at surface step portions can be eliminated, a semiconductor integrated circuit can be formed by a simple process, has a high yield, and has a high breakdown voltage using a high-quality dielectric separation method. You can get the equipment.
第1図は本発明の一実施例の断面図、第2図は第1図の
実施例の製造工程の絶縁性有機膜の塗布状態を示す一部
工程の断面図である。
1・・・・・・シリコン単結晶島、2・・・・・・フィ
ールドプレート、3・・・・・・金属配線層、4・・・
・・・絶縁性有機皮膜、5・・・・・・薄い絶縁膜、5
/・・・・・・厚い絶縁膜、6・・・・・・素子接合部
、7・・・・・・多結晶シリコン支持層。
代理人 弁理士 内 原 晋、・ニア 、−、\
。FIG. 1 is a cross-sectional view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view of a part of the manufacturing process of the embodiment shown in FIG. 1, showing the coating state of an insulating organic film. 1...Silicon single crystal island, 2...Field plate, 3...Metal wiring layer, 4...
... Insulating organic film, 5 ... Thin insulating film, 5
/...Thick insulating film, 6...Element junction, 7...Polycrystalline silicon support layer. Agent Patent Attorney Susumu Uchihara, Nia , -, \
.
Claims (1)
島にフィールドプレートを備えた高耐圧素子を形成して
構成される半導体集積回路装置において、基板表面の段
差部およびフィールドプレートを埋め込みかつその表面
が平坦になるよう塗布された絶縁性有機皮膜と、該絶縁
性有機皮膜に形成され前記フィールドプレートに達する
スルーホールと、前記絶縁性有機皮膜の上に設けられた
金属配線とを有することを特徴とする半導体集積回路装
置。In a semiconductor integrated circuit device configured by forming a high breakdown voltage element with a field plate on a silicon single crystal island formed on a substrate by a dielectric separation method, the stepped portion of the substrate surface and the field plate are embedded and the surface is It is characterized by having an insulating organic film coated so as to be flat, a through hole formed in the insulating organic film and reaching the field plate, and a metal wiring provided on the insulating organic film. Semiconductor integrated circuit device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24660184A JPS61125049A (en) | 1984-11-21 | 1984-11-21 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24660184A JPS61125049A (en) | 1984-11-21 | 1984-11-21 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61125049A true JPS61125049A (en) | 1986-06-12 |
Family
ID=17150835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24660184A Pending JPS61125049A (en) | 1984-11-21 | 1984-11-21 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61125049A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994025985A1 (en) * | 1993-04-28 | 1994-11-10 | Harris Corporation | Method and semiconductor device with increased maximum terminal voltage |
-
1984
- 1984-11-21 JP JP24660184A patent/JPS61125049A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1994025985A1 (en) * | 1993-04-28 | 1994-11-10 | Harris Corporation | Method and semiconductor device with increased maximum terminal voltage |
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