JPS60244047A - Manufacture of semiconductive ic device - Google Patents

Abstract

PURPOSE:To enable chip size to the reduced and yield rate to improve by a method wherein an uneven part of an oxide film for insulation of a dielectric isolation substrate out of an oxide film on a surface of a semiconductor IC is smoothened and flattened. CONSTITUTION:At first, an oxide film 5 on a surface of a semiconductive IC is formed on a surface of a dielectric isolation substrate 4. Next, solution 12 melted SiO2 system mineral compound, such as glass melted into organic compound is applied on the surface by the spin-on method, so as to fill up enough a recessed hollow 11 of the oxide film on the surface of the semiconductive IC, and levels the surface thereof. Next, after solution 12 is hardened by heat treatment, the semiconductive IC element is formed, adding the process to remove uniformly a part of the oxide film 13 from the ground by means of dry-etching. The semiconductive IC device which is obtained by the dielectric isolation method in such a manner, can remove the problems such as disconnection of wiring at the wiring process and increasing thickness of wiring to prevent thereof, etc., thanks to the smoothing uneven part of an oxide film for insulation and flattening of the surface.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device using a dielectric isolation substrate and having particularly excellent high voltage resistance and high frequency characteristics.

In general, in the manufacture of monolithic integrated circuits, it is necessary to electrically isolate and isolate various components such as transistors and resistors from each other. At present, there are two typical 211f systems: the PN separation system and the induced one-body separation system. The latter method usually uses an oxide film as an insulating material and has advantages over the PN separation force method in that it has less parasitic capacitance and can easily achieve a high breakdown voltage.

A method of manufacturing a semiconductor integrated circuit device using the most typical conventional dielectric isolation method will be sequentially explained with reference to FIGS. 1(a) to 1(e).

First, as shown in FIG. 1(a), a dielectric isolation substrate 4 having a plurality of single-crystal silicon islands 3 insulated from each other by an insulating oxide film 2 in a polycrystalline silicon 1 is manufactured using a known technique. A semiconductor integrated circuit surface oxide film 5 is formed on the surface of this dielectric isolation substrate 4 by thermal oxidation. This semiconductor integrated circuit surface oxide film 5 is usually used in order to prevent inversion of the single crystal silicon surface in a high-voltage planar type semiconductor integrated circuit device.
It is necessary to make an extremely thick oxide film of μm or more. Next, by using a known planar technique or the like, a photolithography step, a diffusion/oxidation step, etc. are carried out to divide the dielectric material. Impurities are introduced into the substrate 4 (1 to 1). Semiconductor integrated circuit elements such as transistors and resistors are formed. 11th! m(b) shows a vertical type npn) run sister 6 formed by the above method. However, for ease of explanation, it is assumed that the monocrystalline silicon islands 3 and 1- of the dielectric isolation substrate 4 have n-type conductivity. Next, as shown in FIG. 1(c), a semiconductor integrated circuit device is formed through a lithography step, a wiring metal deposition step represented by A1, etc. In FIG. 1(c), Reference numerals 7, 8 and 9 respectively indicate the collector electrode, emitter electrode, and base overlap of the vertical type NPN) run sister 6.

The biggest drawback of the high-voltage planar semiconductor integrated device based on the dielectric isolation method described in 1-1 above is shown in Figure 1 (
The surface interface 10 of the insulating oxide film 2 shown in e) forms a concave depression 11, as shown in FIG. 2, which is a partially enlarged view. In general, the oxidation mechanism of oxide film is about 50% on the surface of single crystal or polycrystalline silicon.
Division 5, grows about 45 inches inside. Since there is no reacting excess silicon in the insulating oxide Ill of the dielectric isolation substrate 1- or 1-1, the insulating oxide film 2 hardly grows in the direction perpendicular to the surface of the dielectric isolation substrate. For this reason,
If a surface oxide film of 2 μm or more is grown on a single-crystal silicon surface for safety in terms of the characteristics of a semiconductor integrated circuit device, fI!
A step difference of 1 μm or more is produced in the oxide film for the three edges, and this appears as surface irregularities.

If unevenness occurs in the dielectric isolation substrate in this way.

Problems such as wire breakage occur during the wiring process, and to prevent this, measures must be taken such as making the wiring ring r4.

In this case, it is difficult to miniaturize the wiring due to non-uniform etching in one process of wiring photolithography, resulting in an increase in chip size and a decrease in yield. In FIG. 2, the same components as in FIG. 1 are designated by the same reference numerals 1-.

31 An object of the present invention is to eliminate the above-mentioned defects and reduce the chip size by eliminating unevenness and flattening the insulating oxide film of the dielectric isolation substrate in the surface oxide film of a semiconductor integrated circuit. An object of the present invention is to provide a high-voltage planar type semiconductor integrated circuit device +q that can improve yield.

In order to achieve the above object, the present invention provides a method for forming semiconductor integrated circuit devices such as transistors, resistors, etc. by diffusing and oxidizing impurities in a dielectric separation method, and then forming a semiconductor integrated circuit device through a wiring process. In the process, a thick oxide film is formed on the surface of the dielectric isolation substrate before the wiring process, and then fused glass is deposited on the oxide film.
A solution of 8102-based inorganic compounds dissolved in an organic solvent, such as The method is characterized in that a semiconductor integrated circuit device is formed.

Next, embodiments of the present invention will be described with reference to the drawings.

4- FIGS. 3(a) to 3(d) are partial cross-sectional views showing the manufacturing process of a high breakdown voltage planar semiconductor integrated circuit device using a dielectric separation method according to an embodiment of the present invention. First, Figure 3(a)
, on the surface of a dielectric isolation substrate 40 having a plurality of monocrystalline silicon islands 3 insulated from each other by an insulating oxide film 2 in a polycrystalline silicon 1 manufactured by a known technique,
A semiconductor integrated circuit surface oxide film 5 is formed by thermal oxidation.

This semiconductor integrated circuit surface oxide film 5 is normally required to be a very thick oxide film of 2 μm or more in order to prevent inversion of the quasi-crystalline silicon surface in a high breakdown voltage planar type semiconductor integrated circuit device. Next, the surface of the semiconductor integrated circuit surface oxide film 5 is filled with Si such as molten glass so that the concave depressions 11 are sufficiently filled.
A solution 12 in which an O2-based inorganic compound is dissolved in an organic solvent is applied by a spin-on method to flatten the surface. Next, Figure 3 (
As shown in b), by solidifying the solution 12 applied to the surface of the semiconductor integrated circuit surface oxide film 5 by heat treatment,
The solution 12 transforms into an oxide film 13 having almost the same characteristics as the semiconductor integrated circuit surface oxide film 5. Subsequently, a part of the oxidized layer 13 is uniformly removed from the surface by a plasma etching method using a dry etching device using CFA +02 gas, so that the surface becomes flat.
is obtained. Next, the substrate 14 is formed through a photolithography process, a diffusion/oxidation process, etc. using a known planar technology.
Impurities are introduced into 1- to form semiconductor integrated circuit elements such as transistors and resistors. FIG. 3(c) shows a vertical type npn) run sister 6 formed by the above method. However, for ease of explanation, a case will be described in which the single crystal silicon islands 3 of the dielectric isolation substrate 4 have n-type conductivity. Further, as shown in FIG. 3(d), a semiconductor integrated circuit device is formed through a lithography step and a wiring metal adhesion step represented by e. In FIG. 3(d), 7 and 8 degrees 9 indicate the collector electrode, emitter electrode, and base polarization of the vertical type NPN transistor 6, respectively.

The high-voltage planar semiconductor integrated circuit device obtained in this way can eliminate problems such as disconnection of wiring and increase in wiring thickness during the wiring process, and has advantages such as reduction in chip size and improvement in 1-in. A 4i1s semiconductor integrated circuit device can be produced.

In the above example, the quasi-crystalline silicon islands of the dielectric isolation substrate are described as having n-type conductivity (~, but even islands with p-type conductivity have complementary types of 11-type conductivity and n-type conductivity). Of course, it may be an island, or an island having a high-intensity buried layer for preventing inversion at the interface of the insulation film.

1. As explained above, the semiconductor integrated circuit device using the dielectric isolation substrate obtained by the method of the present invention has no unevenness in the insulating oxide film portion of the dielectric isolation substrate of the semiconductor integrated circuit surface oxide film. In addition to being flat, it is possible to eliminate problems such as wire breakage in the subsequent wiring process and increase in wiring thickness to prevent this problem, resulting in a reduction in chip size and a single improvement. It has excellent effects such as

[Brief explanation of drawings]

Figures 1 (a) to (e) are cross-sectional views showing a conventional dielectric isolation semiconductor integrated circuit device (Mine's!!), and Figure 2 is a partially enlarged cross-sectional view of Figure 1 (c). , Fig. 3(a) to (d)
) is a semiconductor integrated circuit device 7 using the dielectric isolation method of the present invention.
- It is a sectional view showing the manufacturing process of the device. 1... Polycrystalline silicon, 2... Insulating oxide film, 3
...An island of single crystal silicon. 4... Dielectric isolation substrate, 5... Semiconductor integration) single-way surface oxide film, 6... Vertical type NPN transistor, 7... Collector electrode, 8... Emitter electrode, 9... Base electrode, 10... Surface interface of insulating oxide film, 11... Concave depression, 12... Solution of S, 02-based inorganic compound such as molten glass dissolved in organic solvent, 13... oxide film, 14...substrate. Agent Patent Attorney Someyo Rikichi 8- Sun + N Convex d Two ν

Claims (1)

[Claims] A method of forming semiconductor integrated circuit elements such as transistors and resistors by diffusing and oxidizing impurities on a dielectric isolation substrate, and then forming a high-voltage planar semiconductor integrated circuit device using the g-electrical isolation method through a wiring process. Before the wiring process, a thick oxide film is formed on the surface of the dielectric isolation substrate, and then fused glass is deposited on top of the oxide film.
A process in which a solution of a 5iCh-based inorganic compound such as ss) dissolved in an organic solvent is applied by a spin-on method, solidified by heat treatment, and then a part of the oxide film is uniformly removed from the surface by a dry etching method. 1. A method for manufacturing a high-voltage planar semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is formed by adding 1-.