JPS61124196A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPS61124196A
JPS61124196A JP24514784A JP24514784A JPS61124196A JP S61124196 A JPS61124196 A JP S61124196A JP 24514784 A JP24514784 A JP 24514784A JP 24514784 A JP24514784 A JP 24514784A JP S61124196 A JPS61124196 A JP S61124196A
Authority
JP
Japan
Prior art keywords
wiring board
multilayer wiring
copper foil
inner layer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24514784A
Other languages
Japanese (ja)
Inventor
真人 大西
坂田 寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP24514784A priority Critical patent/JPS61124196A/en
Publication of JPS61124196A publication Critical patent/JPS61124196A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、部品作動時にLSIより発生するジュール熱
を効果的に放散させることのできる熱放散性に優れた多
層配線板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multilayer wiring board with excellent heat dissipation properties that can effectively dissipate Joule heat generated by an LSI during operation of components.

従来例の構成とその問題点 近年、プリント配線板は高密度配線、高密度部品実装が
行われ、限られたスペースに数多くのLSIが配置され
るようになってきており、LSIと電子回路よシ発生す
るジュール熱が大きく、この熱処理が問題となっている
。第1図に示すよう2ベー/ な従来の多層配線板では、配線板自身の熱放散性が劣る
ため、この熱処理方法として、LSIに設けた冷却用の
フィンを空冷で強制冷却する方式が用いられてきた。し
かしながら、上記のような方法では十分に熱を放散させ
ることができないという欠点を有していた。一方では、
第2図に示すような熱放散性に優れたメタルコア・プリ
ント配線板が開発されている。これは薄いアルミニウム
板1の表面をエポキシ系・ポリイミド系樹脂またはホー
ローなどの絶縁材2で被覆し、この表面に所望の回路3
とスルホール4をめっきで形成したものである。しかし
ながら、これの配線板では、配線板やスルホールの孔の
周囲が盛り上り、表面平滑性が悪く、反りが発生しやす
い。またホーローを構成する金属酸化物は熱と電界の作
用によシイオン化レマイプレーションが生じる。さらに
メタルコア・プリント配線板では、配線板の大きさも小
さなものに限定され、多層化が難しいなどの欠点を有し
ていた。このため、熱放散性の優れた多層配線板の開発
が望まれていた。
Conventional configurations and their problems In recent years, high-density wiring and high-density component mounting have been implemented on printed wiring boards, and a large number of LSIs have been placed in a limited space. The Joule heat generated is large, and this heat treatment has become a problem. As shown in Figure 1, in a conventional 2-base multilayer wiring board, the heat dissipation of the wiring board itself is poor, so the heat treatment method used is a method in which the cooling fins provided on the LSI are forcedly cooled by air cooling. I've been exposed to it. However, the above method has the disadvantage that heat cannot be sufficiently dissipated. on the one hand,
A metal core printed wiring board with excellent heat dissipation properties as shown in FIG. 2 has been developed. In this method, the surface of a thin aluminum plate 1 is coated with an insulating material 2 such as epoxy/polyimide resin or enamel, and a desired circuit 3 is placed on this surface.
and through holes 4 are formed by plating. However, in this wiring board, the area around the wiring board and the through hole swells, the surface smoothness is poor, and warping is likely to occur. In addition, the metal oxide constituting the enamel undergoes ionization and remaiplication due to the action of heat and electric field. Furthermore, metal core printed wiring boards have disadvantages such as the size of the wiring board being limited to small ones and making multilayering difficult. Therefore, it has been desired to develop a multilayer wiring board with excellent heat dissipation properties.

3ページ 発明の目的 本発明は、このような従来の欠点を除去するものであり
、部品作動時にLSIと回路よ多発生するジュール熱を
効果的に放散させることのできる熱放散性に優れた多層
配線板を提供するものである。
Page 3 Purpose of the Invention The present invention is intended to eliminate such conventional drawbacks, and is to provide a multilayer structure with excellent heat dissipation properties that can effectively dissipate the Joule heat generated in LSI and circuits during component operation. The present invention provides wiring boards.

発明の構成 上記目的を達成するだめに、本発明の多層配線板は、回
路を形成した外層銅箔とスルホールを介して接続した内
層銅箔のうち、電源回路またはアース回路として使用す
る内層鋼箔を配線板端部で露出させ、この露出した内層
銅箔の放熱板とから構成されている。この構成によって
、露出した内層銅箔を強制的に冷却することで、部品作
動時にLSIと回路より発生するジュール熱を効果的に
発散させることとなる。
Structure of the Invention In order to achieve the above object, the multilayer wiring board of the present invention comprises an outer layer copper foil forming a circuit and an inner layer copper foil connected via through holes, an inner layer steel foil used as a power supply circuit or a ground circuit. is exposed at the end of the wiring board, and a heat dissipation plate made of the exposed inner layer copper foil. With this configuration, by forcibly cooling the exposed inner layer copper foil, the Joule heat generated by the LSI and the circuit when the component is operated can be effectively dissipated.

実施例の説明 以下本発明の製造方法の1例を図面を参照して説明する
。第3図に示すように、電源回路またはアース回路とし
て利用した内層回路と放熱板として利用する銅箔部分を
形成した後、内層回路表面と側面を、樹脂との密着力を
向上させるだめの化学的表面処理を行なった内層材69
両面に、エポキシ樹脂を主成分とする接着剤6を塗布し
、片面に銅箔のある外層材7a、7bを重ね合せ、電子
線8を照射することによって接着剤6を硬化させて、第
4図に示すような4層多層配線板9を形成する。このよ
うにして、配線板端部で内層鋼箔を露出させた4層多層
配線板9を容易に形成することができる。第6図は、4
層多層配線板9に孔加工を行い、スルホール1oを形成
し、無電解めつき11を行った多層配線板の断面図を示
すものである。第6図は、レジスト膜12を形成した後
の多層配線板の断面図を示す−ものである。第7図は、
電気銅めっき13.電気半田めつき14を行い、レジス
ト膜8を除去した多層配線板の断面を示すものである。
DESCRIPTION OF EMBODIMENTS An example of the manufacturing method of the present invention will be described below with reference to the drawings. As shown in Figure 3, after forming the inner layer circuit used as a power supply circuit or ground circuit and the copper foil part used as a heat sink, the surface and side surfaces of the inner layer circuit are coated with a chemical to improve adhesion to the resin. Inner layer material 69 with target surface treatment
An adhesive 6 mainly composed of epoxy resin is applied to both sides, outer layer materials 7a and 7b having copper foil on one side are superimposed, and the adhesive 6 is cured by irradiating with an electron beam 8. A four-layer multilayer wiring board 9 as shown in the figure is formed. In this way, the four-layer multilayer wiring board 9 with the inner layer steel foil exposed at the ends of the wiring board can be easily formed. Figure 6 shows 4
This is a cross-sectional view of a multilayer wiring board in which a multilayer wiring board 9 has been subjected to hole processing, through holes 1o have been formed, and electroless plating 11 has been performed. FIG. 6 shows a cross-sectional view of the multilayer wiring board after the resist film 12 has been formed. Figure 7 shows
Electrolytic copper plating 13. This figure shows a cross section of a multilayer wiring board after electrical solder plating 14 has been performed and resist film 8 has been removed.

第8図は、エツチングによ多回路を形成し、フュージン
グを行い、その後ソルダー印刷15を行った多層配線板
の断面図である。第9図は、内層銅箔間のショートを防
ぐとともに、最5ページ 終多層配線板の形にするために外形加工を行って得られ
た、熱放散性に優れた多層印刷配線板の断面図を示すも
のである。
FIG. 8 is a sectional view of a multilayer wiring board on which multiple circuits were formed by etching, fusing was performed, and then solder printing 15 was performed. Figure 9 is a cross-sectional view of a multilayer printed wiring board with excellent heat dissipation, obtained by external processing to prevent short circuits between inner copper foil layers and to form a multilayer wiring board (see page 5). This shows that.

なお、第5図から第8図までは、4層多層配線板9の例
を示したが、6層以上の多層配線板についても同様にし
て、目的の多層配線板を形成することができる。上記の
ようにして得られた本発明の多層配線板は、露出しだ内
層銅箔の放熱板16を強制的に冷却することによって、
第10図に示すように部品作動時にLS117が発生す
るジュール熱は、LSIのリード部18.半田付けされ
たスルホール19.スルホールと電源回路またはアース
回路として使用した内層銅箔の接続部、電源回路または
アース回路として利用した内層銅箔。
Although FIGS. 5 to 8 show an example of a four-layer multilayer wiring board 9, a multilayer wiring board with six or more layers can be formed in the same manner. The multilayer wiring board of the present invention obtained as described above is produced by forcibly cooling the exposed inner layer copper foil heat sink 16.
As shown in FIG. 10, the Joule heat generated by the LS 117 when the component operates is transmitted to the lead portion 18 of the LSI. Soldered through hole 19. The connection between the through hole and the inner layer copper foil used as a power supply circuit or ground circuit, and the inner layer copper foil used as a power supply circuit or ground circuit.

放熱板へと伝わる。このようにしてLSIよ多発生され
たジュール熱を放散させることができる。
It is transmitted to the heat sink. In this way, the Joule heat generated by the LSI can be dissipated.

なお、第10図では放熱板を1箇所にしか示されていな
いが、放熱板を1箇所以上に設けることにより、熱放散
性はさらに優れる。
Although the heat sink is shown at only one location in FIG. 10, the heat dissipation performance is further improved by providing the heat sink at one or more locations.

発明の効果 6ページ 以上のように本発明は、回路を形成した外層銅箔とスル
ホールを介して接続した内層銅箔のうち、電源回路また
はアース回路として使用する内層銅箔を配線板端部で露
出させ、この露出した内層銅箔の放熱板を設けることに
より、部品作動時にLSIよ多発生するジュール熱を効
果的に放散させることができ、その実用的効果は大なる
ものである。
Effects of the Invention As described on page 6 and above, the present invention provides an arrangement in which, of the inner layer copper foil connected to the outer layer copper foil forming the circuit through the through-hole, the inner layer copper foil used as the power supply circuit or the earth circuit is connected to the outer layer copper foil forming the circuit at the edge of the wiring board. By exposing the exposed inner layer copper foil and providing a heat dissipation plate, it is possible to effectively dissipate the Joule heat that is generated more often than in LSI when the component is operated, and its practical effect is great.

【図面の簡単な説明】 第1図は従来の4層多層配線板の断面図、第2図は従来
のメタルコア・プリント配線板の断面図、第3図は本発
明の一実施例における多層配線板の積層方法を示す断面
図、第4図は本発明の積層された4層多層配線板の断面
図、第6図から第8図までは同多層配線板の製造方法を
示す断面図、第9図は同条゛層配線板の断面図、第10
図はLSIを搭載した同多層配線板の断面図である。 7a、7b・・・・・外層材、1o・・・・・スルホー
ル、16・・・・・・放熱板。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第3図 第4図 Ll’)            Co       
    ゝ法       憾      憾 Co             Ch 塚       嶽
[Brief Description of the Drawings] Fig. 1 is a sectional view of a conventional four-layer multilayer wiring board, Fig. 2 is a sectional view of a conventional metal core printed wiring board, and Fig. 3 is a multilayer wiring in an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a method of laminating boards, FIG. 4 is a cross-sectional view of a four-layer multilayer wiring board according to the present invention, and FIGS. Figure 9 is a cross-sectional view of the same layer wiring board, and Figure 10 is
The figure is a cross-sectional view of the same multilayer wiring board on which an LSI is mounted. 7a, 7b...outer layer material, 1o...through hole, 16...heat sink. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 4 Ll') Co
ゝ法 Sorry Sorry Co Ch Tsukatake

Claims (1)

【特許請求の範囲】[Claims]  回路を形成した外層銅箔とスルホールを介して接続し
た内層銅箔のうち、電源回路またはアース回路として使
用する内層銅箔を配線板端部で露出させ、この露出した
内層銅箔を放熱板として利用することを特徴とした多層
配線板。
Of the inner layer copper foil connected via through-holes to the outer layer copper foil that formed the circuit, the inner layer copper foil used as a power supply circuit or ground circuit is exposed at the edge of the wiring board, and this exposed inner layer copper foil is used as a heat sink. A multilayer wiring board characterized by its use.
JP24514784A 1984-11-20 1984-11-20 Multilayer wiring board Pending JPS61124196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24514784A JPS61124196A (en) 1984-11-20 1984-11-20 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24514784A JPS61124196A (en) 1984-11-20 1984-11-20 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPS61124196A true JPS61124196A (en) 1986-06-11

Family

ID=17129318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24514784A Pending JPS61124196A (en) 1984-11-20 1984-11-20 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPS61124196A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02101794A (en) * 1988-10-11 1990-04-13 Matsushita Electric Ind Co Ltd Multilayer printed interconnection board
JP2003515266A (en) * 1999-10-22 2003-04-22 スティルウォーター デザインズ アンド オーディオ インコーポレイテッド Ultra low frequency transducer and loudspeaker having the same
JP2010123708A (en) * 2008-11-19 2010-06-03 Sony Corp Mounting board and semiconductor module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02101794A (en) * 1988-10-11 1990-04-13 Matsushita Electric Ind Co Ltd Multilayer printed interconnection board
JP2003515266A (en) * 1999-10-22 2003-04-22 スティルウォーター デザインズ アンド オーディオ インコーポレイテッド Ultra low frequency transducer and loudspeaker having the same
JP2010123708A (en) * 2008-11-19 2010-06-03 Sony Corp Mounting board and semiconductor module
JP4730426B2 (en) * 2008-11-19 2011-07-20 ソニー株式会社 Mounting substrate and semiconductor module
US8263871B2 (en) 2008-11-19 2012-09-11 Sony Corporation Mount board and semiconductor module

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