JP3956408B2 - Manufacturing method of multilayer wiring board - Google Patents

Manufacturing method of multilayer wiring board Download PDF

Info

Publication number
JP3956408B2
JP3956408B2 JP30849996A JP30849996A JP3956408B2 JP 3956408 B2 JP3956408 B2 JP 3956408B2 JP 30849996 A JP30849996 A JP 30849996A JP 30849996 A JP30849996 A JP 30849996A JP 3956408 B2 JP3956408 B2 JP 3956408B2
Authority
JP
Japan
Prior art keywords
layer
insulating layer
forming
conductor
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30849996A
Other languages
Japanese (ja)
Other versions
JPH10150278A (en
Inventor
和浩 小久保
かおる 藤井
健人 塚本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP30849996A priority Critical patent/JP3956408B2/en
Publication of JPH10150278A publication Critical patent/JPH10150278A/en
Application granted granted Critical
Publication of JP3956408B2 publication Critical patent/JP3956408B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、電子機器等に使用される半導体装置搭載用の多層配線板とその製造方法に係り、特に基板の片面に二層もしくはそれ以上の多層の導体配線層を有し、配線密度が向上した構成の多層配線板とその製造方法に関する。
【0002】
本発明にて言う多層配線板は、半導体集積回路素子(以下、チップと称する)を直接、搭載・接続するタイプの回路基板(一般的に普及している、印刷回路の設けられたプリント配線板)や、チップをリードフレームに搭載・接続した状態での半導体装置を接続する外部回路としてのプリント配線板等を包含する。
【0003】
【従来の技術】
互いに交差するような回路パターンを含む配線板を片面のみで作成するために導体配線層と絶縁層とを交互に積層することで、多層配線板を得て配線密度を向上させることが従来より行なわれている。
【0004】
従来のプリント配線板は実装部品を取り付けた後、動作時の発熱量の多い部品については部品個別にフィンを取り付けていた。
【0005】
また、従来の複合プリント配線板は、プリント配線基板製造過程において内層のパターン層の表面に実装部品を取り付けた後、多層化接着プレスして1枚のプリント配線基板を形成してなるため、実装部品がプリント配線基板に内装されるので放熱性が著しく低下し回路の動作に悪影響を及ぼす。
【0006】
さらに、従来の多層配線板でベース基板に放熱板を用いた場合、放熱板上に絶縁層と導体配線層とを交互に積層することで、多層配線基板上に実装されるチップと放熱板との距離ができてしまう。このため、この放熱板を多層配線板の中央に設ける工夫がされているが、熱の伝達方向が基板と水平方向のみとなってしまうため、発熱量の多い部品に関しては多層配線板の側面に放熱用のフィンなどを取り付ける必要があった。
【0007】
【発明が解決しようとする課題】
従来のプリント配線板は、部品個別に放熱用のフィンを取り付けなければならないため、部品実装コストが高く多くの実装作業時間を要していた。
【0008】
複合プリント配線板においては部品を配線基板に内装するため、放熱用のフィンなどを取り付けることもできず、部品の発熱によって回路動作に悪影響を及ぼす問題があった。
また、表面実装、チップオンボードやTAB等の実装方式を用いた場合、従来の約4倍もの発熱量となるため、放熱量が不足するという問題がある。
【0009】
さらに、従来の多層配線板においては、放熱板上に絶縁層と導体配線層とを交互に積層することで、多層化になればなるほど絶縁層の厚さが増して、多層配線基板上に実装されるチップ、その他の部品と放熱板との距離が増えて、放熱性が著しく低下する。このため、放熱板を多層配線板の中央に設ける工夫がされているが、熱の伝達方向が基板と水平方向のみとなってしまうため、発熱量の多い部品に関しては多層配線板の側面に放熱用のフィンなどを取り付ける必要があることから、部品実装コストが高く多くの実装作業時間を要していた。
【0010】
本発明は、上記問題点に鑑みなされたもので、その目的とするところは、多層配線板内で発生する熱を効率よく外部に放出するための多層配線板の構成及びその製造方法を提供することにある
【0011】
【課題を解決するための手段】
本発明において上記課題を解決するために放熱性向上を目的とした金属基板上に、導体配線層と放熱層とが絶縁層を介して交互に積層されたことを特徴とする多層配線板としたものである。
【0012】
また前記導体配線層面に放熱パターンを設けることを特徴とする多層配線板としたものである。
【0013】
また前記放熱層及び放熱パターンは相互にビアによって電気的及び熱的に接続されており、最終的に前記金属基板に接続されて、金属基板を通して放熱するようにしたものである。
【0014】
請求項1においては、以下の(a)〜(i)の工程を備えることを特徴とする多層配線板の製造方法としたものである。
(a)金属基板上に第1絶縁層を形成する工程。
(b)第1絶縁層を貫通するビアホールを形成し、ビアホール及び第1絶縁層上に導体層を形成し、第1導体配線層を形成する工程。
(c)第2絶縁層を形成し、第1絶縁層及び第2絶縁層を貫通するビアホールを形成する工程。
(d)第2絶縁層上及びビアホールに導体層を形成し、導体層をパターニング処理して第1放熱層を形成する工程。
(e)第3絶縁層を形成し、第3絶縁層を貫通するビアホールと第2絶縁層及び第3絶縁層を貫通するビアホールを形成する工程。
(f)第3絶縁層上及びビアホールに導体層を形成し、第2導体配線層及び第2放熱パターンを形成する工程。
(g)第4絶縁層を形成し、第4絶縁層を貫通するビアホールを形成し、第4絶縁層上及びビアホールに導体層を形成し、導体層をパターニング処理して第2放熱層を形成する工程。
(h)第5絶縁層を形成し、第5絶縁層を貫通するビアホールと第4及び第5絶縁層を貫通するビアホールを形成し、第5絶縁層及びビアホールに導体層を形成し、導体層をパターニング処理して第3導体配線層及び第3放熱パターンを形成する工程。
(i)上記(c)〜(f)の工程を必要回数繰り返して、多層配線板を作製する工程。
【0015】
【発明の実施の形態】
本発明による多層配線板の形成方法は、次に示すものである。
図1は本発明の多層配線板の一実施例の構成を、図2(a)〜(h)は本発明の多層配線板の一実施例の製造工程を示す断面図である。
本発明の多層配線板の基本構成は、導体配線層と絶縁層間に放熱層が、導体配線層面に部分的に放熱パターンが形成されており、放熱層及び放熱パターンは相互にビアにて電気的及び熱的に接続されて、最終的には金属基板に接続されて放熱される。
【0016】
まず、金属基板1上に第1絶縁層2を形成する(図2(a)参照)。
金属基板1は、導電性があり、熱伝導性に優れた材料であれば使用でき、銅板が最も一般的である。
絶縁層の形成方法としては、樹脂溶液をローラーコート法、ディップコート法、スプレーコート法、スピナーコート法、カーテンコート法、スクリーン印刷法等の各種手段を用いて塗布することができる。
絶縁層の材料は、一般の多層配線板に用いられる電気絶縁性を有するものであれば特に制限はない。耐熱性、絶縁性などから、ベンゾシクロブテン(以下BCBと称す)が好適である。
【0017】
第1絶縁層2にビアホールを形成した後導体層を形成し、パターニング処理して第1導体配線層3を形成し、一部の第1導体配線層はビアにて金属基板に接続されてグランド接続される(図2(b)参照)。
ビアホールの形成は、ドリル等の機械加工法、フォトリソグラフィー法、レーザー加工法が利用できるが微細加工性、絶縁層材料の選択幅の広さ及び加工形状の制御容易性等の理由からレーザー加工が一般的である。
導体層は、最初真空蒸着法、スパッタリング法、無電解メッキ法のいずれかの方法にて全面に銅金属の薄膜導体層を形成して、電解銅メッキにて所定の厚さの導体層及びビアを形成する。
導体配線層は、通常のフォトリソグラフィー法にてパターニング処理して形成する。
【0018】
次に、第2絶縁層4及びビアホール5及び導体層を形成した後導体層をパターニング処理して第1放熱層6を形成する(図2(c)、(d)参照)。ここで、第1放熱層6はビア7にて金属基板1に電気的、熱的に接続される。
【0019】
次に、第3絶縁層8及びビアホール9、10及び全面に導体層を上記の方法で形成した後、導体層をパターニング処理して第2導体配線層11及び第2放熱パターン12を形成する(図2(e)、(f)参照)。ここで、第2導体配線層11と第2放熱パターン12は同一面上に混在しているが電気的には絶縁されている。さらに、第2導体配線層11はビア13にて第1導体配線層3に電気的に接続され、第2放熱パターン12はビア14にて第1放熱層6に電気的及び熱的に接続される。
【0020】
同様にして、第4絶縁層15及びビアホールを形成した後全面に導体層を形成し、パターニング処理して第2放熱層16を形成する(図2(g)参照)。
【0021】
同様にして、第5絶縁層18及びビアホールを形成した後全面に導体層を形成し、パターニング処理して第3導体配線層19及び第3放熱パターン20を形成する(図2(h)参照)。
以上の一連の工程により、3層の導体配線層と2層の放熱層及び放熱パターンを有する本発明の多層配線板が得られる。これ以上の多層配線板が必要な場合は図2の(c)〜(f)の工程を必要回数繰り返せばよい。
【0022】
以上のように、本発明の放熱層及び放熱パターンを有する多層配線板は所定の箇所においてビアにて放熱層と放熱パターンとが相互に接続されており、これらが金属基板に接続されていることから、放熱が効率よく行われる。
【0023】
【実施例】
以下、本発明の多層配線板の実施例について、図面を参照しながら説明する。図2(a)〜(h)にその多層配線板の一実施例の製造方法を示す。
【0024】
黒化処理を施した厚さ約400μmの銅の金属基板1上にBCB(ダウケミカル社製)樹脂溶液をスピンコーターにて塗布し、75℃20分間乾燥した後、窒素中で100℃15分、150℃15分、210℃30分間加熱硬化して、約10μm厚の第1絶縁層2を形成した(図2(a)参照)。
【0025】
次に、KrFエキシマレーザー加工機を用いて、0.5J/cm2 のレーザービームを所定の位置に照射して、第1絶縁層2にビアホールを形成した。さらに、第1絶縁層2上にスパッタリング法にて厚み約0.2μmの銅の導体薄膜を形成して、電解銅めっきにより膜厚約10μmの導体層を形成した。
導体層上にネガ型液状レジスト(PMER;東京応化工業(株)製)をディップコータで塗布し、乾燥硬化して感光層を形成し、所定のパターンマスクを介して、約500mJ/cm2 の露光量で露光して、専用の現像液で現像処理して110℃30分加熱乾燥してレジストパターンを形成した。さらに、50℃の塩化第2鉄溶液をスプレーエッチングした後5%の水酸化ナトリウム溶液に浸漬してレジストパターンを剥離して第1導体配線層3を形成した(図2(b)参照)。
【0026】
次に、BCB(ダウケミカル社製)樹脂溶液をスピンコーターにて塗布し、75℃20分間乾燥した後、窒素中で100℃15分、150℃15分、210℃30分間加熱硬化して、約10μm厚の第2絶縁層4を形成した。さらに、KrFエキシマレーザー加工機を用いて、0.5J/cm2 のレーザービームを所定の位置に照射して、第1絶縁層2及び第2絶縁層4に50μmφのビアホール5を形成した(図2(c)参照)。
【0027】
次に、上記の導体層形成と同様の方法で約10μmの導体層を形成し、上記と同様な方法でパターニング処理して第1放熱層6を形成した。ここで、第1放熱層6はビア7にて金属基板1に電気的及び熱的に接続される(図2(d)参照)。
【0028】
次に、上記の第2絶縁層4と同様の方法で第3絶縁層8を形成した。さらに、上記と同様な方法でビアホール9及び10を形成した(図2(e)参照)。
【0029】
次に、上記の導体層形成と同様の方法で約10μmの導体層を形成し、上記と同様な方法でパターニング処理して第2導体配線層11及び第2放熱パターン12を形成した(図2(f)参照)。ここで、第2導体配線層11はビア13にて第1導体配線層3に電気的に接続され、第2放熱パターン12はビア14にて第1放熱層6に電気的及び熱的に接続される。
【0030】
次に、上記の第2絶縁層と同様の方法で第4絶縁層15及びビアホールを形成した。さらに、上記の導体層形成と同様の方法で約10μmの導体層を形成し、上記と同様な方法でパターニング処理して第2放熱層16を形成した(図2(g)参照)。ここで、第2放熱層16はビア17にて第2放熱パターン12に電気的及び熱的に接続される。
【0031】
次に、上記の第2絶縁層と同様の方法で第5絶縁層18及びビアホールを形成した。さらに、上記の導体層形成と同様の方法で約10μmの導体層を形成し、上記と同様な方法でパターニング処理して第3導体配線層19及び第3放熱パターン20を形成した(図2(h)参照)。ここで、第3導体配線層19はビア21にて第2導体配線層11に電気的に接続され、第3放熱パターン20はビア22にて第2放熱層6に電気的及び熱的に接続される。
以上の一連の工程により、3層の導体配線層と2層の放熱層及び放熱パターンを有する本発明の多層配線板が得られた。
【0032】
【発明の効果】
本発明の多層配線板の構成にすることにより、チップにて発生した熱は、放熱層及び放熱パターンからビアを通して金属基板へと流れる様な熱の回路を作製することができ、金属基板より放熱できる。
また、放熱用フィンなどを設ける必要もないので基板の小型化を可能とした多層配線板を得ることができる。
さらに、前記放熱層がグランドに接続されて導電性パターンがストリップ構造となるためクロストークもなく電気的特性も向上する。
【図面の簡単な説明】
【図1】本発明の多層配線板の一実施例の構成を示す断面図である。
【図2】(a)〜(h)は、本発明の多層配線板の一実施例の製造方法を示す工程断面図である。
【符号の説明】
1……金属基板
2……第1絶縁層
3……第1導体配線層
4……第2絶縁層
5、9、10……ビアホール
6……第1放熱層
7、13、14、17、21、22……ビア
8……第3絶縁層
11……第2導体配線層
12……第2放熱パターン
15……第4絶縁層
16……第2放熱層
18……第5絶縁層
19……第3導体配線層
20……第3放熱パターン
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer wiring board for mounting a semiconductor device used in an electronic device and the like, and a method for manufacturing the same. In particular, it has two or more multilayered conductor wiring layers on one side of a substrate to improve wiring density. The present invention relates to a multilayer wiring board having the above structure and a method for manufacturing the same.
[0002]
The multilayer wiring board referred to in the present invention is a circuit board of a type on which a semiconductor integrated circuit element (hereinafter referred to as a chip) is directly mounted / connected (a printed wiring board provided with a printed circuit, which is widely used). And a printed wiring board as an external circuit for connecting the semiconductor device with the chip mounted and connected to the lead frame.
[0003]
[Prior art]
In order to create a wiring board containing circuit patterns that cross each other on only one side, it is conventionally performed to obtain a multilayer wiring board and improve wiring density by alternately laminating conductor wiring layers and insulating layers. It is.
[0004]
In conventional printed wiring boards, after mounting components, fins are individually attached to components that generate a large amount of heat during operation.
[0005]
In addition, the conventional composite printed wiring board is formed by mounting a mounting component on the surface of the inner pattern layer in the printed wiring board manufacturing process and then forming a single printed wiring board by multi-layer adhesive pressing. Since the components are built in the printed wiring board, the heat dissipation is remarkably reduced and the circuit operation is adversely affected.
[0006]
Further, when a heat sink is used as a base substrate in a conventional multilayer wiring board, by alternately laminating insulating layers and conductor wiring layers on the heat sink, chips mounted on the multilayer wiring board and the heat sink The distance is made. For this reason, the heat radiating plate has been devised to be provided in the center of the multilayer wiring board. However, since the heat transfer direction is only in the horizontal direction with respect to the substrate, the parts that generate a large amount of heat are placed on the side of the multilayer wiring board. It was necessary to attach fins for heat dissipation.
[0007]
[Problems to be solved by the invention]
Since the conventional printed wiring board has to be provided with fins for heat radiation for each component, the component mounting cost is high and a lot of mounting work time is required.
[0008]
In the composite printed wiring board, since the components are mounted on the wiring board, it is not possible to attach fins for heat dissipation or the like, and there is a problem that the circuit operation is adversely affected by the heat generated by the components.
In addition, when a mounting method such as surface mounting, chip-on-board, or TAB is used, the amount of heat generated is about four times that of the conventional method, resulting in a problem of insufficient heat dissipation.
[0009]
Furthermore, in conventional multilayer wiring boards, insulating layers and conductor wiring layers are alternately stacked on the heat sink, so that the thickness of the insulating layer increases as the number of layers increases, and the multilayer wiring board is mounted on the multilayer wiring board. The distance between the chip and other components and the heat radiating plate is increased, and the heat dissipation is remarkably reduced. For this reason, a heat radiating plate has been devised in the center of the multilayer wiring board. However, since the heat transfer direction is only in the horizontal direction with respect to the board, heat is dissipated on the side of the multilayer wiring board for parts that generate a large amount of heat. Since it is necessary to attach fins for the purpose, the component mounting cost is high and a lot of mounting work time is required.
[0010]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a structure of a multilayer wiring board for efficiently releasing the heat generated in the multilayer wiring board to the outside and a method for manufacturing the same. There is a thing [0011]
[Means for Solving the Problems]
In order to solve the above problems in the present invention, on a metal substrate for the purpose of heat dissipation enhancement, and the multilayer wiring board and a conductor interconnect layer heat dissipation layer is characterized by being alternately laminated through an insulating layer It is a thing.
[0012]
Further , the present invention is a multilayer wiring board characterized in that a heat radiation pattern is provided on the conductor wiring layer surface.
[0013]
Further, the heat dissipation layer and the heat radiation pattern is electrically and thermally connected by a via to each other, it is ultimately connected to the metal substrate, in which so as to radiate through the metal substrate.
[0014]
According to a first aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board, comprising the following steps (a) to (i).
(A) A step of forming a first insulating layer on a metal substrate.
(B) forming a via hole penetrating the first insulating layer, forming a conductor layer on the via hole and the first insulating layer, and forming a first conductor wiring layer;
(C) forming a second insulating layer and forming a via hole penetrating the first insulating layer and the second insulating layer;
(D) A step of forming a conductive layer on the second insulating layer and in the via hole, and patterning the conductive layer to form a first heat dissipation layer.
(E) forming a third insulating layer and forming a via hole penetrating the third insulating layer and a via hole penetrating the second insulating layer and the third insulating layer;
(F) A step of forming a conductor layer on the third insulating layer and in the via hole, and forming a second conductor wiring layer and a second heat radiation pattern.
(G) Forming a fourth insulating layer, forming a via hole penetrating the fourth insulating layer, forming a conductor layer on the fourth insulating layer and in the via hole, and patterning the conductor layer to form a second heat dissipation layer Process.
(H) forming a fifth insulating layer, forming a via hole penetrating the fifth insulating layer and a via hole penetrating the fourth and fifth insulating layers, and forming a conductor layer in the fifth insulating layer and the via hole; Forming a third conductor wiring layer and a third heat radiation pattern by patterning.
(I) A step of producing a multilayer wiring board by repeating the steps (c) to (f) as many times as necessary.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
A method for forming a multilayer wiring board according to the present invention is as follows.
FIG. 1 is a cross-sectional view showing a configuration of an embodiment of the multilayer wiring board of the present invention, and FIGS. 2A to 2H are cross-sectional views showing a manufacturing process of the embodiment of the multilayer wiring board of the present invention.
The basic structure of the multilayer wiring board of the present invention is that a heat dissipation layer is formed between the conductor wiring layer and the insulating layer, and a heat dissipation pattern is partially formed on the surface of the conductor wiring layer. And thermally connected, and finally connected to the metal substrate to dissipate heat.
[0016]
First, the first insulating layer 2 is formed on the metal substrate 1 (see FIG. 2A).
The metal substrate 1 can be used as long as it is conductive and has excellent thermal conductivity, and a copper plate is the most common.
As a method for forming the insulating layer, the resin solution can be applied using various means such as a roller coating method, a dip coating method, a spray coating method, a spinner coating method, a curtain coating method, and a screen printing method.
The material of the insulating layer is not particularly limited as long as it has electrical insulation used for a general multilayer wiring board. Benzocyclobutene (hereinafter referred to as BCB) is preferred from the standpoint of heat resistance and insulation.
[0017]
After forming a via hole in the first insulating layer 2, a conductor layer is formed, and patterning is performed to form a first conductor wiring layer 3. A part of the first conductor wiring layer is connected to a metal substrate through a via and grounded. They are connected (see FIG. 2B).
For the formation of via holes, machining methods such as drills, photolithography methods, and laser processing methods can be used. However, laser processing is not possible due to reasons such as fine processability, wide selection of insulating layer materials, and ease of control of the processing shape. It is common.
The conductor layer is formed by first forming a copper metal thin film conductor layer on the entire surface by any one of a vacuum deposition method, a sputtering method, and an electroless plating method, and a conductor layer and a via having a predetermined thickness by electrolytic copper plating. Form.
The conductor wiring layer is formed by patterning by a normal photolithography method.
[0018]
Next, after forming the second insulating layer 4, the via hole 5, and the conductor layer, the conductor layer is patterned to form the first heat radiation layer 6 (see FIGS. 2C and 2D). Here, the first heat dissipation layer 6 is electrically and thermally connected to the metal substrate 1 through the via 7.
[0019]
Next, a conductor layer is formed on the third insulating layer 8 and the via holes 9 and 10 and the entire surface by the above method, and then the conductor layer is patterned to form the second conductor wiring layer 11 and the second heat radiation pattern 12 ( (Refer FIG.2 (e) and (f)). Here, the second conductor wiring layer 11 and the second heat radiation pattern 12 are mixed on the same surface, but are electrically insulated. Further, the second conductor wiring layer 11 is electrically connected to the first conductor wiring layer 3 through a via 13, and the second heat radiation pattern 12 is electrically and thermally connected to the first heat radiation layer 6 through a via 14. The
[0020]
Similarly, after forming the fourth insulating layer 15 and the via hole, a conductor layer is formed on the entire surface and patterned to form the second heat dissipation layer 16 (see FIG. 2G).
[0021]
Similarly, after forming the fifth insulating layer 18 and the via hole, a conductor layer is formed on the entire surface, and patterned to form a third conductor wiring layer 19 and a third heat radiation pattern 20 (see FIG. 2H). .
Through the above series of steps, the multilayer wiring board of the present invention having three conductor wiring layers, two heat dissipation layers and a heat dissipation pattern is obtained. If more multilayer wiring boards are required, the steps (c) to (f) in FIG. 2 may be repeated as many times as necessary.
[0022]
As described above, in the multilayer wiring board having the heat dissipation layer and the heat dissipation pattern of the present invention, the heat dissipation layer and the heat dissipation pattern are connected to each other by vias at predetermined locations, and these are connected to the metal substrate. Therefore, heat dissipation is performed efficiently.
[0023]
【Example】
Embodiments of a multilayer wiring board according to the present invention will be described below with reference to the drawings. 2A to 2H show a manufacturing method of an embodiment of the multilayer wiring board.
[0024]
BCB (manufactured by Dow Chemical) resin solution was applied on a black metal substrate 1 having a thickness of about 400 μm by a spin coater, dried at 75 ° C. for 20 minutes, and then in nitrogen at 100 ° C. for 15 minutes. The first insulating layer 2 having a thickness of about 10 μm was formed by heating and curing at 150 ° C. for 15 minutes and 210 ° C. for 30 minutes (see FIG. 2A).
[0025]
Next, a via hole was formed in the first insulating layer 2 by irradiating a predetermined position with a laser beam of 0.5 J / cm 2 using a KrF excimer laser processing machine. Further, a copper conductor thin film having a thickness of about 0.2 μm was formed on the first insulating layer 2 by sputtering, and a conductor layer having a thickness of about 10 μm was formed by electrolytic copper plating.
A negative liquid resist (PMER; manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the conductor layer with a dip coater, dried and cured to form a photosensitive layer, and is passed through a predetermined pattern mask to give about 500 mJ / cm 2 . The resist pattern was formed by exposing with an exposure amount, developing with a dedicated developer, and heating and drying at 110 ° C. for 30 minutes. Further, the ferric chloride solution at 50 ° C. was spray-etched and then immersed in a 5% sodium hydroxide solution to peel off the resist pattern to form the first conductor wiring layer 3 (see FIG. 2B).
[0026]
Next, a BCB (Dow Chemical Co.) resin solution was applied with a spin coater and dried at 75 ° C. for 20 minutes, and then heated and cured in nitrogen at 100 ° C. for 15 minutes, 150 ° C. for 15 minutes, and 210 ° C. for 30 minutes. A second insulating layer 4 having a thickness of about 10 μm was formed. Further, using a KrF excimer laser processing machine, a laser beam of 0.5 J / cm 2 was irradiated to a predetermined position to form a via hole 5 of 50 μmφ in the first insulating layer 2 and the second insulating layer 4 (FIG. 2 (c)).
[0027]
Next, a conductor layer having a thickness of about 10 μm was formed by the same method as that for forming the conductor layer, and the first heat dissipation layer 6 was formed by patterning using the same method as described above. Here, the first heat dissipation layer 6 is electrically and thermally connected to the metal substrate 1 through the via 7 (see FIG. 2D).
[0028]
Next, the third insulating layer 8 was formed by the same method as the second insulating layer 4 described above. Further, via holes 9 and 10 were formed by the same method as described above (see FIG. 2E).
[0029]
Next, a conductor layer having a thickness of about 10 μm was formed by the same method as that for forming the conductor layer, and the second conductor wiring layer 11 and the second heat radiation pattern 12 were formed by patterning by the same method as described above (FIG. 2). (Refer to (f)). Here, the second conductor wiring layer 11 is electrically connected to the first conductor wiring layer 3 through a via 13, and the second heat radiation pattern 12 is electrically and thermally connected to the first heat radiation layer 6 through a via 14. Is done.
[0030]
Next, the 4th insulating layer 15 and the via hole were formed by the method similar to said 2nd insulating layer. Further, a conductor layer having a thickness of about 10 μm was formed by the same method as that for forming the conductor layer, and the second heat radiation layer 16 was formed by patterning using the same method as described above (see FIG. 2G). Here, the second heat radiation layer 16 is electrically and thermally connected to the second heat radiation pattern 12 through the vias 17.
[0031]
Next, a fifth insulating layer 18 and a via hole were formed by the same method as that for the second insulating layer. Further, a conductor layer having a thickness of about 10 μm was formed by the same method as that for forming the conductor layer, and the third conductor wiring layer 19 and the third heat radiation pattern 20 were formed by patterning by the same method as described above (FIG. 2 ( h)). Here, the third conductor wiring layer 19 is electrically connected to the second conductor wiring layer 11 via the via 21, and the third heat radiation pattern 20 is electrically and thermally connected to the second heat radiation layer 6 via the via 22. Is done.
Through the above series of steps, the multilayer wiring board of the present invention having three conductor wiring layers, two heat radiation layers and a heat radiation pattern was obtained.
[0032]
【The invention's effect】
With the configuration of the multilayer wiring board of the present invention, it is possible to produce a circuit in which the heat generated in the chip flows from the heat radiation layer and the heat radiation pattern to the metal substrate through the via, and the heat radiation from the metal substrate. it can.
In addition, since it is not necessary to provide heat-dissipating fins, a multilayer wiring board capable of reducing the size of the substrate can be obtained.
Furthermore, since the heat dissipation layer is connected to the ground and the conductive pattern has a strip structure, there is no crosstalk and the electrical characteristics are improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of an embodiment of a multilayer wiring board according to the present invention.
FIGS. 2A to 2H are process cross-sectional views illustrating a manufacturing method of an embodiment of a multilayer wiring board according to the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Metal substrate 2 ... 1st insulating layer 3 ... 1st conductor wiring layer 4 ... 2nd insulating layers 5, 9, 10 ... Via hole 6 ... 1st thermal radiation layer 7, 13, 14, 17, 21, 22... Via 8... Third insulating layer 11... Second conductor wiring layer 12... Second heat radiation pattern 15. ... Third conductor wiring layer 20 ... Third heat dissipation pattern

Claims (1)

以下の工程を備えることを特徴とする多層配線板の製造方法。
(a)金属基板上に第1絶縁層を形成する工程。
(b)第1絶縁層を貫通するビアホールを形成し、ビアホール及び第1絶縁層上に導体層を形成し、第1導体配線層を形成する工程。
(c)第2絶縁層を形成し、第1絶縁層及び第2絶縁層を貫通するビアホールを形成する工程。
(d)第2絶縁層上及びビアホールに導体層を形成し、導体層をパターニング処理して第1放熱層を形成する工程。
(e)第3絶縁層を形成し、第3絶縁層を貫通するビアホールと第2絶縁層及び第3絶縁層を貫通するビアホールを形成する工程。
(f)第3絶縁層上及びビアホールに導体層を形成し、第2導体配線層及び第2放熱パターンを形成する工程。
(g)第4絶縁層を形成し、第4絶縁層を貫通するビアホールを形成し、第4絶縁層上及びビアホールに導体層を形成し、導体層をパターニング処理して第2放熱層を形成する工程。
(h)第5絶縁層を形成し、第5絶縁層を貫通するビアホールと第4及び第5絶縁層を貫通するビアホールを形成し、第5絶縁層及びビアホールに導体層を形成し、導体層をパターニング処理して第3導体配線層及び第3放熱パターンを形成する工程。
(i)上記(c)〜(f)の工程を必要回数繰り返して、多層配線板を作製する工程。
The manufacturing method of the multilayer wiring board characterized by including the following processes.
(A) A step of forming a first insulating layer on a metal substrate.
(B) forming a via hole penetrating the first insulating layer, forming a conductor layer on the via hole and the first insulating layer, and forming a first conductor wiring layer;
(C) forming a second insulating layer and forming a via hole penetrating the first insulating layer and the second insulating layer;
(D) A step of forming a conductive layer on the second insulating layer and in the via hole, and patterning the conductive layer to form a first heat dissipation layer.
(E) forming a third insulating layer and forming a via hole penetrating the third insulating layer and a via hole penetrating the second insulating layer and the third insulating layer;
(F) A step of forming a conductor layer on the third insulating layer and in the via hole, and forming a second conductor wiring layer and a second heat radiation pattern.
(G) Forming a fourth insulating layer, forming a via hole penetrating the fourth insulating layer, forming a conductor layer on the fourth insulating layer and in the via hole, and patterning the conductor layer to form a second heat dissipation layer Process.
(H) forming a fifth insulating layer, forming a via hole penetrating the fifth insulating layer and a via hole penetrating the fourth and fifth insulating layers, and forming a conductor layer in the fifth insulating layer and the via hole; Forming a third conductor wiring layer and a third heat radiation pattern by patterning.
(I) A step of producing a multilayer wiring board by repeating the steps (c) to (f) as many times as necessary.
JP30849996A 1996-11-19 1996-11-19 Manufacturing method of multilayer wiring board Expired - Fee Related JP3956408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30849996A JP3956408B2 (en) 1996-11-19 1996-11-19 Manufacturing method of multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30849996A JP3956408B2 (en) 1996-11-19 1996-11-19 Manufacturing method of multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH10150278A JPH10150278A (en) 1998-06-02
JP3956408B2 true JP3956408B2 (en) 2007-08-08

Family

ID=17981759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30849996A Expired - Fee Related JP3956408B2 (en) 1996-11-19 1996-11-19 Manufacturing method of multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3956408B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420937B1 (en) * 2000-08-29 2002-07-16 Matsushita Electric Industrial Co., Ltd. Voltage controlled oscillator with power amplifier
TWI275333B (en) 2003-12-05 2007-03-01 Ind Tech Res Inst Method for forming metal wire by microdispensing
CN100428871C (en) * 2003-12-19 2008-10-22 财团法人工业技术研究院 Method for forming plain conductor pattern by means of ink-jet
JP4916235B2 (en) * 2006-06-29 2012-04-11 日東電工株式会社 Printed circuit board

Also Published As

Publication number Publication date
JPH10150278A (en) 1998-06-02

Similar Documents

Publication Publication Date Title
US5985760A (en) Method for manufacturing a high density electronic circuit assembly
JP3297879B2 (en) Integrated circuit package formed continuously
US6618940B2 (en) Fine pitch circuitization with filled plated through holes
US6268016B1 (en) Manufacturing computer systems with fine line circuitized substrates
JP3666955B2 (en) Method for manufacturing flexible circuit board
JP3953122B2 (en) Circuit card and manufacturing method thereof
JPH09116267A (en) Manufacture of multilayer circuit board with via hole, and chip carrier and its manufacture
JP2007081409A (en) Printed circuit board having fine pattern and method for manufacturing the same
JP3956408B2 (en) Manufacturing method of multilayer wiring board
US6110650A (en) Method of making a circuitized substrate
JPH09312471A (en) Multilayer wiring board and its manufacturing method
JP3598525B2 (en) Method of manufacturing multilayer board for mounting electronic components
JP2003124637A (en) Multilayer wiring board
US6671950B2 (en) Multi-layer circuit assembly and process for preparing the same
JP2001217511A (en) Heat-conductive substrate and its manufacturing method
JP2003142829A (en) Multi-layered wiring board and its manufacturing method
US20020127494A1 (en) Process for preparing a multi-layer circuit assembly
US20020124398A1 (en) Multi-layer circuit assembly and process for preparing the same
KR100342335B1 (en) Resin laminated wiring sheet, wiring structure using the same, and production method thereof
JP2622848B2 (en) Manufacturing method of printed wiring board
JP2000307217A (en) Forming method of wiring pattern and semiconductor device
JPH0532919B2 (en)
JPH06252529A (en) Manufacture of printed wiring board
JPH10126062A (en) Multilayer wiring board
JP3648753B2 (en) Wiring board manufacturing method

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060523

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060724

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070123

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070322

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070417

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070430

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110518

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110518

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120518

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120518

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130518

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140518

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees