JPS61121466A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61121466A JPS61121466A JP59244278A JP24427884A JPS61121466A JP S61121466 A JPS61121466 A JP S61121466A JP 59244278 A JP59244278 A JP 59244278A JP 24427884 A JP24427884 A JP 24427884A JP S61121466 A JPS61121466 A JP S61121466A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- electrode
- epitaxial
- bipolar transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 8
- 238000002955 isolation Methods 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- 230000010354 integration Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910002076 stabilized zirconia Inorganic materials 0.000 description 2
- 101100002917 Caenorhabditis elegans ash-2 gene Proteins 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- WLQSSCFYCXIQDZ-UHFFFAOYSA-N arsanyl Chemical compound [AsH2] WLQSSCFYCXIQDZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
Abstract
Description
【発明の詳細な説明】
（イ）発明の目的
〔産業上の利用分野〕
この発明は半導体装置に関し、詳しくは高速化・高集積
化に好適なバイポーラトランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION (a) Object of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a bipolar transistor suitable for high speed and high integration.
従来から、ハイポ−ラトランジスタには、ＰＮ接合方式
と酸化膜分離方式とがあるのが知られている。Conventionally, it has been known that hyperpolar transistors include a PN junction type and an oxide film separation type.
このバイポーラトランジスタは、近年、高速化・高集積
化が進められている大規模集積回路（ＬＳＩ）及び超Ｌ
ＳＩ（ＶＬＳＩ）に用いられるが、前記ＰＮ接合分離方
式では、寄生容量の減少化や微細化に限界があるため、
高速化や高密度化を実施するのは非常に難かしく、一方
散化膜分離方式では、サブミクロン加工の領域に入ると
ＰＮ接合分離方式と同様に高速化・高密度化ができなく
なると考えられている。また、バイポーラトランジスタ
の基板にサファイヤ基板を用いて、上記欠点を解決する
方法も検討されているが、サファイヤ基板の価格が高く
、しかもシリコン半導体のエピタキシャル膜の電気的特
性や欠陥の数が多いためバイポーラ素子などのデバイス
には適用されていないのが実状である。This bipolar transistor is used in large-scale integrated circuits (LSI) and ultra-Large integrated circuits, which are becoming faster and more highly integrated in recent years.
Although it is used for SI (VLSI), the PN junction isolation method has limitations in reducing parasitic capacitance and miniaturization.
It is extremely difficult to achieve higher speeds and higher densities, and on the other hand, with the dispersion membrane separation method, we believe that once we enter the area of submicron processing, we will no longer be able to achieve higher speeds and higher densities, similar to the PN junction separation method. It is being In addition, a method of solving the above drawbacks by using a sapphire substrate as the substrate of a bipolar transistor is being considered, but the cost of the sapphire substrate is high, and the electrical characteristics of the silicon semiconductor epitaxial film and the number of defects are large. The reality is that it has not been applied to devices such as bipolar elements.
この発明は以上の事情に鑑みなされたもので、その主要
な目的は半導体装置内部に、エミッタ電極を共通とした
差動増幅機能を有する一対のバイポーラトランジスタ回
路を設けるとともにこの回路の各素子を絶縁して、半導
体装置の高速化・高集積化を図ることにある。This invention was made in view of the above circumstances, and its main purpose is to provide a pair of bipolar transistor circuits with a common emitter electrode and a differential amplification function inside a semiconductor device, and to insulate each element of this circuit. The objective is to achieve higher speed and higher integration of semiconductor devices.
（ロ）発明の構成
この発明は、シリコン結晶基板上に酸化物単結晶からな
る第１の絶縁膜を介して第１のエピタキシャル層が形成
され、さらにこの第１のエピタキシャル層の上面に第２
の絶縁膜を介して第２のエピタキシャル層が形成され、
この第２のエピタキシャル層には一つのエミ・ンタ電極
とこれを共通とした一対のバイポーラトランジスタ回路
が形成され、第２の絶縁膜には、エミッタ電極取出し用
の電極層と前記バイポーラトランジスタ回路における活
性層に対応する部位に開口部がそれぞれ設けられ、これ
により前記エミッタ電極とバイポーラトランジスタ回路
の各電極とが絶縁されて構成されたことを特徴とする半
導体装置である。(B) Structure of the Invention In the present invention, a first epitaxial layer is formed on a silicon crystal substrate with a first insulating film made of an oxide single crystal interposed therebetween, and a second epitaxial layer is further formed on the upper surface of the first epitaxial layer.
A second epitaxial layer is formed through the insulating film,
In this second epitaxial layer, one emitter/interelectrode and a pair of bipolar transistor circuits using this in common are formed, and in the second insulating film, an electrode layer for taking out the emitter electrode and a pair of bipolar transistor circuits using this in common are formed. The semiconductor device is characterized in that openings are provided in portions corresponding to the active layer, whereby the emitter electrode and each electrode of the bipolar transistor circuit are insulated.
すなわち、この発明は一対のバイポーラトランジスタ回
路及び絶縁層によって半導体装置の高速化・高集積化を
実現することにある。That is, the object of the present invention is to realize higher speed and higher integration of a semiconductor device by using a pair of bipolar transistor circuits and an insulating layer.
以下第１図及び第２図に基づ〈実施例に基づいてこの発
明を詳述する。なお、これによってこの発明が限定され
るものではない。The present invention will be described in detail below based on embodiments with reference to FIGS. 1 and 2. Note that this invention is not limited to this.
第１図（ａ） （ｂ）は半導体装置（Ｓ）の縦断面図及
びその構成図で、第２図は半導体装置（Ｓ）の製造工程
を示す図である。FIGS. 1(a) and 1(b) are longitudinal cross-sectional views and configuration diagrams of the semiconductor device (S), and FIG. 2 is a diagram showing the manufacturing process of the semiconductor device (S).
第２図（ａｌにおいて、（１）はシリコン単結晶基板、
（２）は第１の酸化物単結晶膜からなる絶縁膜である。In Figure 2 (al), (1) is a silicon single crystal substrate,
(2) is an insulating film made of a first oxide single crystal film.
この絶縁膜（２）は、安定化ジルコニア膜（ＺｒＯｚ
Ｏ，８・Ｙ２０！ ０．２． Ｚｒ（ｈ Ｏ，８・Ｍｇ
Ｏ０，２）をスパッタ、有機金属化学気相堆積法（ＭＯ
ＣＶＤ）、イオン化クラスタビーム法（ＩＣＢ）、原子
層エピタキシャル法（ＡＬＥ）、イオンプレーテング法
等で形成したものである。This insulating film (2) is a stabilized zirconia film (ZrOz
O,8・Y20! 0.2. Zr(h O,8・Mg
O0,2) was sputtered and metalorganic chemical vapor deposition (MO
CVD), ionized cluster beam method (ICB), atomic layer epitaxial method (ALE), ion plating method, etc.
まず、第１の絶縁膜（′２）の上面に、シリコンのエピ
タキシャル装置によりモノシラン（ＳｉＨ４）とアルシ
ン（ＡｓＨ２）を原料として、第１のエピタキシャル層
としてのシリコンのエピタキシャルｎ中層（３）を０．
３〜１μの範囲で形成する。そして、このエピタキシャ
ルｎ中層（３）に、第２図（ｂ）に示すように第１の絶
縁膜（２）形成方法と同様な方法で第２の絶縁膜（４）
としての酸化物単結晶である安定化ジルコニア膜を形成
する。なお、この膜（４）は減圧化学気相成長法（ＬＰ
ＧＶＤ）により形成された二酸化ケイ素（ＳｉＯｚ）の
酸化膜であってもよい。この絶縁１ｉ （４１は、反応
性イオンエツチング法（ＲＩＥ）によりバイポーラトラ
ンジスタ回路として必要な活性領域ｆ５１． （５ａ）
や、エミッタ共通電極部（８）（第１図ｔａ＋参照）に
当る各箇所が所定のパターンにエツチング処理され開口
されている。（１８）〜（２０）はその開口部である。First, a silicon epitaxial intermediate layer (3) as a first epitaxial layer is formed on the upper surface of the first insulating film ('2) using a silicon epitaxial device using monosilane (SiH4) and arsine (AsH2) as raw materials. ．．
It is formed in the range of 3 to 1 μm. Then, as shown in FIG. 2(b), a second insulating film (4) is formed on this epitaxial n-middle layer (3) by the same method as the first insulating film (2).
A stabilized zirconia film, which is an oxide single crystal, is formed. Note that this film (4) was produced using low pressure chemical vapor deposition (LP).
It may be an oxide film of silicon dioxide (SiOz) formed by GVD). This insulation 1i (41 is an active region f51. (5a) necessary for a bipolar transistor circuit by reactive ion etching (RIE).
Also, each location corresponding to the emitter common electrode portion (8) (see ta+ in FIG. 1) is etched into a predetermined pattern and opened. (18) to (20) are the openings thereof.
次いで、絶縁膜（４）の上面に第２のエピタキシャル層
としてのシリコンのエピタキシャルｎ層（１２）を所定
の膜厚で形成する。（第２図（Ｃ）参照）。Next, an epitaxial n-layer (12) of silicon as a second epitaxial layer is formed with a predetermined thickness on the upper surface of the insulating film (4). (See Figure 2(C)).
次に、第２図（ｄ）に示すようにエピタキシャルｎＦｉ
（１２）の外表面に薄い酸化膜（１３）を形成し、そ
の後、イオン注入法により酸化膜（１３）を通してバイ
ポーラトランジスタ回路の活性層であるベース電極層（
５１，（５ａ）及びコレクタｎ層（６１，（６ａ）を順
次形成する。又ベース電極数り出し用箇所にｐ中層のベ
ース電極層（７）、 （７ａ）を一対形成するとともに
、エミッタ電極の取り出し用の個所には高濃度のヒ素（
Ａｓ）を打込みｎ＋層のエミッタ電極層（８）を形成す
る。Next, as shown in FIG. 2(d), epitaxial nFi
A thin oxide film (13) is formed on the outer surface of the bipolar transistor circuit (12), and then the base electrode layer (13), which is the active layer of the bipolar transistor circuit, is passed through the oxide film (13) by ion implantation.
51, (5a) and the collector n layer (61, (6a)) are formed in sequence. Also, a pair of p-middle base electrode layers (7), (7a) are formed at the location for counting the base electrode, and the emitter electrode There is a high concentration of arsenic (
As) is implanted to form an n+ layer emitter electrode layer (8).
次いで、第２図（ｅ）に示す如く、所定のパターンに従
って、エミッタ電極層（８）とベース電極層（７）。Next, as shown in FIG. 2(e), an emitter electrode layer (8) and a base electrode layer (7) are formed according to a predetermined pattern.
ベース電極層（７）とコレクタｎ ｍ （６１、コレク
タｎ層（６ａ）とベース電極Ｍ（７ａ）、バイポーラト
ランジスタ回路（Ｔ１）と（Ｔ２）等の各部の分離用孔
及びデバイス全体の素子分離用の孔をエピタキシャルｎ
ｉ （１２）内に穿け、その上から全体に素子分離用の
絶縁層（１４）をＬＰＧＶＤにより形成する。なお、こ
の層（１４）は酸化膜からなる。Base electrode layer (7) and collector n m (61, collector n layer (6a) and base electrode M (7a), isolation holes for each part such as bipolar transistor circuits (T1) and (T2), and element isolation for the entire device The holes for epitaxial n
i (12), and an insulating layer (14) for element isolation is formed on the entire surface by LPGVD. Note that this layer (14) is made of an oxide film.
その後表面を平坦化技術により平坦化し、第２図（ｆ）
に示す様に、共通のエミッタ電極（１１）の窓（１５）
、前記（Ｔ１）のベース電極（９）の窓（１６） 、前
記（Ｔ１）のコレクタ電極α０）の窓（１７） 、前記
（Ｔ２）のコレクタ電極（１０ａ）の窓（１７ａ） 、
前記（Ｔ２）のベース電極（９ａ）の窓（１６）等の窓
あけをＲＩＥにより順次処理する。After that, the surface is flattened by flattening technology, as shown in Fig. 2(f).
As shown in the window (15) of the common emitter electrode (11)
, the window (16) of the base electrode (9) of (T1), the window (17) of the collector electrode α0) of (T1), the window (17a) of the collector electrode (10a) of (T2),
Opening of the window (16) of the base electrode (9a) and the like in (T2) is sequentially performed by RIE.
最後に、全面にわたって電極のポリシリコンもしくは金
属電極を形成後、所定のパターンに従ってエツチングし
てデバイス処理工程が完了し、第１図ｆａ）の半導体装
置（Ｓ）が製造される。Finally, after forming polysilicon or metal electrodes over the entire surface, etching is performed according to a predetermined pattern to complete the device processing step, and the semiconductor device (S) shown in FIG. 1fa is manufactured.
この装置（Ｓ）は、その内部にエミッタ電極（１１）を
共通としたバイポーラトランジスタ回路（Ｔｔ ） （
Ｔ２ ）を２個内蔵し、差動増幅機能を所持しているの
で（Ｔ１）のベース電極（９）と（Ｔ２）のベース電極
（９ａ）に信号を入れることにより動作する。This device (S) has a bipolar transistor circuit (Tt) (
Since it has two built-in T2) and has a differential amplification function, it operates by inputting a signal to the base electrode (9) of (T1) and the base electrode (9a) of (T2).
以上のごとく半導体装置（Ｓ）を構成することによって
、ＥＣＬ回路（Ｅｍｉｔｔｅｒ ｃｏｕｐｌｅｄ ｌｏ
ｇｉｃ）に最も必要とする半導体装置の一部を容易に達
成することができ、その上従来のバイポーラトランジス
タ回路はコレクタ接地型が多いけれど、この発明はエミ
ッタ接地型であるため、従来のものより作り方や工程を
簡素化することができる。しかも、一対のバイポーラト
ランジスタ回路の各素子が完全にアイソレーション（絶
縁）されているため高速化や高集積化を実現することが
できる。さらに、この装置（Ｓ）は、バイポーラトラン
ジスタ回路が対称型に形成されているため、エミッタや
コレクタの不純物濃度を変えることにより任意に接地方
式や回路を変えることが可能である。また、この発明は
ｎｐｎ型のバイポーラトランジスタに限ることなく、ｐ
ｎｐ型のバイポーラトランジスタについても適用出来る
ことは言うまでもない。By configuring the semiconductor device (S) as described above, an ECL circuit (Emitter coupled lo
It is possible to easily achieve a part of the semiconductor device most needed for gic), and in addition, conventional bipolar transistor circuits are often of the collector-grounded type, but this invention is of the emitter-grounded type, so it is more efficient than the conventional one. The method and process can be simplified. Moreover, since each element of the pair of bipolar transistor circuits is completely isolated, high speed and high integration can be achieved. Furthermore, since this device (S) has a symmetrical bipolar transistor circuit, it is possible to arbitrarily change the grounding system and circuit by changing the impurity concentration of the emitter and collector. Furthermore, the present invention is not limited to npn-type bipolar transistors;
Needless to say, the present invention can also be applied to np type bipolar transistors.
（ハ）発明の効果
この発明は、第２の絶縁膜を介して二層のシリコンのエ
ピタキシャル層を有し、これらの層のうち上層側の層に
一対のバイポーラトランジスタ回路を形成するとともに
、この回路の各電極とエミッタ電極とが絶縁されて構成
されたものであるから、高速化・高集積化が実現でき、
しかも小型化することができ、その上素子分離が容易と
なるとともに装置の製作工程を簡略化することができる
効果を奏する。(c) Effects of the invention This invention has two epitaxial layers of silicon with a second insulating film interposed therebetween, and forms a pair of bipolar transistor circuits in the upper layer of these layers. Since each electrode of the circuit and the emitter electrode are insulated, high speed and high integration can be realized.
Furthermore, it is possible to reduce the size, and furthermore, it is possible to easily separate elements and to simplify the manufacturing process of the device.
【図面の簡単な説明】
第１図（ａ） （ｂ）はこの発明に係る半導体装置の一
実一施例の原理を示す説明図及びその記号図、第２図（
ａｌ〜（ｆｌはその製造工程を示すに所図原理断與Ｓで
ちる。
（Ｓｒ−半導体装置、（Ｔｔ ） （Ｔ２ ） −バイ
ポーラトランジスタ回路、（ＩＬ−シリコン単結晶基板
、（２Ｌ−一一第１の絶縁膜、（３）・・−エピタキシ
ャルｎ中層（第１のエピタキシャル層） 、（４１−第
２の絶縁膜、（１２）−一エピタキシャル層（第２のエ
ピタキシートル層） 、（１８）〜（２０）−・−開口
部。
代理人 弁理士 野 河 信 太 部￥
第２図
（ａ）[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) and 1(b) are explanatory diagrams and symbolic diagrams thereof showing the principle of one embodiment of a semiconductor device according to the present invention, and FIG.
(Sr-semiconductor device, (Tt) (T2)-bipolar transistor circuit, (IL-silicon single crystal substrate, (2L-11) First insulating film, (3) - epitaxial n middle layer (first epitaxial layer), (41 - second insulating film, (12) - epitaxial layer (second epitaxial layer), (18) )～(20)-・-Opening. Agent Patent Attorney Nobuhito Nogawa Figure 2 (a)
Claims (1)
絶縁膜を介して第１のエピタキシャル層が形成され、さ
らにこの第１のエピタキシャル層の上面に第２の絶縁膜
を介して第２のエピタキシャル層が形成され、この第２
のエピタキシャル層には一つのエミッタ電極とこれを共
通とした一対のバイポーラトランジスタ回路が形成され
、第２の絶縁膜には、エミッタ電極取出し用の電極層と
前記バイポーラトランジスタ回路における活性層に対応
する部位に開口部がそれぞれ設けられ、これにより前記
エミッタ電極とバイポーラトランジスタ回路の各電極と
が絶縁されて構成されたことを特徴とする半導体装置。1. A first epitaxial layer is formed on a silicon crystal substrate with a first insulating film made of an oxide single crystal interposed therebetween, and a second epitaxial layer is formed on the upper surface of this first epitaxial layer with a second insulating film interposed therebetween. an epitaxial layer is formed, and this second
One emitter electrode and a pair of bipolar transistor circuits using this in common are formed in the epitaxial layer, and the second insulating film has an electrode layer for taking out the emitter electrode and an active layer corresponding to the bipolar transistor circuit. 1. A semiconductor device, characterized in that openings are provided at each portion, whereby the emitter electrode and each electrode of the bipolar transistor circuit are insulated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59244278A JPS61121466A (en) | 1984-11-19 | 1984-11-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59244278A JPS61121466A (en) | 1984-11-19 | 1984-11-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61121466A true JPS61121466A (en) | 1986-06-09 |
| JPH0467786B2 JPH0467786B2 (en) | 1992-10-29 |
Family
ID=17116364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59244278A Granted JPS61121466A (en) | 1984-11-19 | 1984-11-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121466A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7829971B2 (en) | 2007-12-14 | 2010-11-09 | Denso Corporation | Semiconductor apparatus |
| US8148809B2 (en) | 2009-01-15 | 2012-04-03 | Denso Corporation | Semiconductor device, method for manufacturing the same, and multilayer substrate having the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57112044A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Semiconductor device |
-
1984
- 1984-11-19 JP JP59244278A patent/JPS61121466A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57112044A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7829971B2 (en) | 2007-12-14 | 2010-11-09 | Denso Corporation | Semiconductor apparatus |
| US8148809B2 (en) | 2009-01-15 | 2012-04-03 | Denso Corporation | Semiconductor device, method for manufacturing the same, and multilayer substrate having the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0467786B2 (en) | 1992-10-29 |
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