JPH01278070A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the occupied area of a transistor, and realize fine structure and cost reduction by forming regions from the first to the third becoming an emitter, a base and a collector in an island-type single crystal semiconductor layer arranged on an insulator substrate. CONSTITUTION:An insulator substrate 11 is used as a substrate, on which an island-type single crystal semiconductor layer 17 is arranged, and the first - the third regions 17c-17a becoming an emitter, a base and a collector are formed. A first conductive film 12 and a second conductive film 14, which are mutually isolated by an insulative film 13, are formed as leading-out electrodes for the first region 17c and the second region 17b. Thereby, the occupied area of a transistor can be decreased, and the generation of parasitic capacitance can be reduced. Further, since the insulator substrate 11 is used as the substrate, fine structure is realized and a low cost semiconductor device, whose operating performance is improved, is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device having a vertical bipolar transistor structure, and particularly to a semiconductor device having a vertical bipolar transistor structure. This invention relates to a semiconductor device with improved operating speed.

[Prior Art] Conventionally, a vertical NPN bipolar transistor has been constructed as shown in FIG. That is, an n-type collector resistance compensation region 5 is provided in an n-type epitaxial layer (collector region) 3 surrounded by an n-type buried N2 and an insulating film 4 provided on a p-type silicon substrate 1. and p-type base region 7
A highly doped p-type graft base region 6 and a highly doped n-type emitter region 8 are provided. In addition, a collector resistance compensation region 5, a graft base region 6 and an emitter region 8
Openings 9a and 9b for electrode extraction are provided on each surface of the electrode.

9c are provided, and each electrode 10 is provided in these openings 9a to 90. Note that 4a is an isolation insulating film, 4b
is a p-type channel cut region.

[Problems to be Solved by the Invention] In the conventional transistor structure described above, a photolithography process is required for forming each diffusion region and the like. Therefore, in order to realize extremely fine transistors, alignment accuracy becomes a problem. Considering this alignment accuracy, it is necessary to perform operations such as enlarging the margin between the base region 7 and the emitter region 8, for example.

However, this increases the joint surface area between the base and the collector, causing an increase in the joint capacitance.

Further, actual transistor operation is performed only in the area immediately below and in the vicinity of the emitter region 8.

The other part is the area required for electrode attachment,
Therefore, all of this region has an adverse effect on transistor operation.

For example, a pn junction is formed between the n-type buried layer 2 and the p-type silicon substrate 1, so that a junction capacitance jLcaub is parasitic. Furthermore, since the area of the external base region becomes larger than the area of the emitter region 8, the external base parasitic capacitance C8B'' and the parasitic resistance rbb' increase significantly. In order to use the layer 2, a low concentration epitaxial layer 3, a high concentration collector resistance compensation region 5, an isolation insulating film 4a, and a channel cut region 4b are required. The number of photolithography steps increases, and the cost also increases.

For this reason, the conventionally structured npn bipolar transistor has a large number of regions other than the region that operates as an original transistor (intrinsic transistor region), which reduces performance and greatly hinders miniaturization.

The present invention has been made in view of such problems, and includes:
In addition to preventing the generation of parasitic capacitance, the area other than the intrinsic transistor area can be reduced, and the number of photolithography steps can be significantly reduced, allowing for miniaturization and cost reduction, as well as improved performance. The purpose is to provide semiconductor devices.

[Means for Solving the Problems] A semiconductor device according to the present invention includes an insulating substrate, and a first region, a second region, and a third region that form a pn junction with each other on the upper surface of the insulating substrate. an island-shaped single crystal semiconductor layer which is stacked and has a side wall surface substantially perpendicular to the upper surface of the insulating substrate; and an island-shaped single crystal semiconductor layer which is provided on the insulating substrate and at least partially contacts the first region. a first conductive film; a second conductive film provided on the first conductive film via an insulating film and at least partially in contact with the second region; a first electrode electrically connected to the second conductive film, a second electrode electrically connected to the third region, and a third electrode electrically connected to the third region. It is characterized by

[Function] In the semiconductor device of the present invention, an insulating substrate is used as the substrate, and the lead electrodes from the intrinsic transistor region to the first electrode and the second electrode in the island-like single crystal semiconductor layer are connected to each other by an insulating film. separated first
Because the conductive film and the second conductive film are provided, there is no parasitic junction capacitance, and the first to third regions that become the emitter, base, and collector are formed as an island on an insulating substrate. Since these regions are formed in a single-crystalline semiconductor layer, these regions can be formed in a self-aligned manner, and therefore the area occupied by the transistor can be extremely reduced. Furthermore, the buried layer, channel cut region, and isolation insulating film required in the conventional structure become unnecessary.

[Example] Next, an example of the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 is a vertical cross-sectional view showing an npn transistor according to an embodiment of the present invention. In FIG. On this insulating substrate 11, an island-shaped single crystal silicon layer 17 is provided which includes an n-type collector region 17λ, a p-type base region 17b, and an n-type emitter region 17c. The sidewalls of this island-shaped single crystal silicon layer 17 are substantially perpendicular to the surface of the substrate 11. Further, on the insulating substrate 11, a first conductive film 12 made of a polysilicon film, a first insulating film 13 made of an oxide film, and a second insulating film made of a polysilicon film are formed around the island-shaped single crystal silicon layer 17. A conductive film 14 and a second insulating film 15 made of an oxide film are sequentially laminated. Each end face of the first conductive film 12, first insulating film 13, second conductive film 14, and second insulating film 15 is provided so as to be in contact with the side wall of the island-shaped single crystal silicon layer 17, respectively. ing. The first insulating film 13 and the second insulating film p
An opening 20a is provided at a position away from the island-shaped single crystal silicon layer 17 of A15 so as to reach the first conductive film 12. Further, an opening 20b is provided in the second insulating film 15 so as to reach the second conductive film 14.

A collector electrode 21a, a base electrode 21b, and an emitter electrode 21c made of an aluminum (AjI) film are patterned on the upper surfaces of the openings 20a, 20b, and the island-shaped single crystal silicon layer 17, respectively.

The first conductive film 12 made of the polysilicon film serves as an extraction electrode for the collector region 17a, and is made of polysilicon in order to reduce the contact resistance between the island-shaped single crystal silicon layer 17 and the polysilicon film. The film is doped with a high concentration of n-type impurity (eg, arsenic). Also,
The second conductive film 14 serves as an extraction electrode for the base region 17b, and is also a polysilicon film doped with a high concentration p-type impurity (for example, boron).

Further, the oxide film that is the second insulating film 15 contains phosphorus to smooth the surface shape and facilitate reflow.

Next, a method for manufacturing the npn bipolar transistor having the above structure will be explained.

First, as shown in FIG. 2(a), CVD (Ch
emicaf Vapor Deposition
) method to deposit approximately 5,000 polysilicon films, and arsenic atoms were added to the entire surface using the ion implantation method.
By doping two or more and then patterning into a predetermined shape using a known photoetching method,
A first conductive film 12 is formed. Thereafter, approximately 3000 layers of oxide film, which is the first insulating film 13, is deposited over the entire surface using the CVD method.

Next, as shown in FIG. 2(b), a second conductive film 1 containing boron atoms at a high concentration is formed by the same method as described above.
About 3,000 people deposited a polysilicon film of No. 4. Subsequently, approximately 3,000 PSG films were deposited on this polysilicon film to form a second insulating film 15, and then heated at 900°C to 10°C.
Heat treatment is performed at 00°C.

Next, as shown in FIG. 2C, the second insulating film 15 and the second conductive film 14 are etched from the upper layer using the -resist film 19 as an etching mask using a reactive ion etching (RIE) method. , the first insulating film 13 and the first conductive film 1
2 is sequentially etched to form an opening 18 that reaches the insulating substrate 11 and has a vertical side wall surface 16. Here, the second insulating film 15 and the first insulating film 13 made of an oxide film are etched with gas plasma mainly composed of C2F6 gas, and the second conductive film 14 and the first insulating film made of a polysilicon film are etched. The first conductive film 12 is etched using gas plasma containing 5iCII4 as a main component.

Next, after removing the resist film 19 using 02 plasma or the like,
5iH2Cρ2゜H2 at a temperature of 800"C to 950℃
, HCρ, a single crystal silicon film is selectively epitaxially grown only on the insulating substrate 11. As a result, the opening 18 is filled with single crystal silicon as shown in FIG. 2(d), and as a result,
An island-shaped single crystal silicon layer 17 is formed. In this epitaxial growth process, PH is introduced into the gas to form an n-type collector region 17a, and B2H
6 gas is introduced to form a p-type base region 17b on the collector region 17a, and finally, AsH3 gas is introduced to form an n-type emitter region 17 on the base region 17b.
form c.

Next, the first conductive film 12 for collector and base extraction
and openings 20 for electrodes reaching the second conductive film 14, respectively.
a, 20b are formed. After that, the electrodes 21a, 21b,
21c, the vertical rl p shown in FIG.
An n bipolar transistor is completed.

Next, a comparison will be made between the thus obtained npn bipolar transistor of this example and a transistor having a conventional structure. First, assume that the area of the emitter region 8 in the conventional transistor shown in FIG. 5 is approximately equal to the area of the opening 9b, and consider the case where the opening 18 of the transistor shown in FIG. 1 is provided with this area. In this case, in a transistor with a conventional structure, the areas of the base region 7 and the collector region are several times to several tens of times larger than the area of the emitter region 8.
It will double. On the other hand, in the transistor of this embodiment, the area of the emitter region 17c is the same as that of the base region 17c.
b and the area of the collector region 17a. Therefore, in this embodiment, the area occupied by the transistor is extremely small, being one to several tenths of the conventional area.

In addition, since a transistor with a conventional structure requires an external base region and a buried layer 2, the external base parasitic capacitance CC
B' and junction capacitance Ctub were parasitic. On the other hand, in the transistor of this example, the first
Since the first conductive film 12 and the second conductive film 14 separated by the insulating film 13 are used, and the insulating substrate 11 is used as the substrate, almost no parasitic capacitance occurs.

It is true that a capacitor structure is formed between the first conductive film 12 and the second conductive film 14 in the transistor of this embodiment as well, but it is insignificant compared to the junction capacitance.

Furthermore, since the transistor of this embodiment uses the insulating substrate 11, the buried layer 2, element isolation insulating film 4a, and channel cut region 4b required in conventional transistors are completely unnecessary. . In addition, the photolithography process required for manufacturing is only 5 times in the example, compared to 9 to 10 times in the conventional process.
Photolithography steps are significantly reduced.

Furthermore, in this embodiment, each region of the emitter, base, and collector is positioned in a self-aligned manner.
Intrinsic transistors can be formed in just one photolithography process.

Next, as another embodiment of the present invention, the area of the emitter region can be further reduced compared to the above embodiment.
A structure that can reduce the junction capacitance between bases will be explained.

FIG. 3 is a longitudinal sectional view showing the structure, and the difference from the above embodiment is that the sidewall film 22a is self-aligned on the sidewall surface of the second insulating film 15 protruding onto the base region 17b. An emitter region 170° is formed with approximately the same area as the inner area of this sidewall film 22a.

Next, the manufacturing method of this example will be explained. Figure 4 (a
) is a diagram showing steps corresponding to the steps in the middle of the transition from (C) to (d) in FIG. 2, and shows a state in which the p-type base region 17b has been formed. In this state, as shown in Figure 4 (
As shown in b), Si3 is applied as the third insulating film 22 over the entire surface.
The N4 film is grown and then etched back by reactive ion etching to form the sidewall film 22a in a self-aligned manner. Thereafter, the arsenic atom is heated, for example, at 50 KeV and at a dose of I x 1016C1n.
”Ion implantation under the condition of -2 and heating at 900℃ to 1000℃
By performing heat treatment, an emitter region of 170° is formed.

Thereafter, by forming electrodes through the same steps as in the embodiment shown in FIG. 2, a transistor having the structure shown in FIG. 3 is obtained.

Here, if the thickness of the second insulating film 15 protruding above the base region 17b and the thickness of the third insulating film 22 in FIG. 4(a) are appropriately selected, the width of the sidewall film 22a can be increased. Since it can be controlled to some extent, the emitter region 17
The area of c° can be reduced to some extent.

In the embodiments shown in FIGS. 1 and 2 described above, a magnesia spinel single crystal substrate was used as the insulating substrate 11, but the present invention is not limited to this, and single crystal silicon Other materials may be used as long as the substrate has approximately the same lattice constant as the substrate and can withstand heat treatment at about 1000°C.

[Effects of the Invention] As described above in detail, according to the semiconductor device according to the present invention, an insulating substrate is used as the substrate, an island-shaped single crystal semiconductor layer is provided on the upper surface of the insulating substrate, and the island-shaped single crystal semiconductor layer is provided on the upper surface of the insulating substrate. A first layer is formed on the single crystal semiconductor layer to become the emitter, base and collector, respectively.
．． In addition to forming the second and third regions, the first conductive film and the second conductive film, which are separated from each other by an insulating film, are formed as extraction electrodes for the first and second regions. , emitter and other regions can be formed in a self-aligned manner, the area occupied by the transistor can be significantly reduced, and the generation of parasitic capacitance can be reduced. In addition, since an insulating substrate is used as the substrate, there is no need for buried layers, insulating films for element isolation, etc. that were required in conventional structures, and furthermore, the number of photolithography steps can be significantly reduced. Therefore, it is possible to realize a low-cost semiconductor device that can be miniaturized and has improved operating performance.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view of an npn bipolar transistor according to an embodiment of the present invention, FIGS. 2(a) to (d) are vertical cross-sectional views showing the manufacturing process of the above transistor, and FIG. 4(a) and 4(b) are longitudinal sectional views showing the manufacturing process of the transistor shown in FIG. 3, and FIG. 5 is a longitudinal sectional view showing the conventional npn bipolar transistor. 1; Silicon substrate; 3; Epitaxial layer; 7; Base region; 8; Emitter region; 10, 21a. 21b, 21c; electrode, 11; insulator substrate, 12; first
conductive film, 13; first insulating film, 14; second conductive film,
15; second insulating film, 16; side wall surface, 17; island-shaped single crystal silicon layer, 17a; collector region, 17b; base region, 17c; emitter region, 22; third insulating film, 22
a; sidewall film 11; cruel body toad @ 17a; collector region 12: first conductive film 17b; base region 13: first insulating film 17C;
Emitter region 14: second conductor ta 2
1a; collector electrode 15; second electrode
21b: base electrode 16; bond 1g 1 side
21c; Emi Tsuta@唖17; Island-shaped single crystal silicon layer FIG. 1 (a) (b) FIG. 2 11: Insulator substrate 15; Second insulating film 12
; First conductive film 16; Side wall surface 13; First conductive film 17: Island-shaped single crystal silicon layer 14; Second conductive film 17Q; Collector region 17b; Base region 17c; Emitter region (c) (d ) Figure 2

Claims (1)

[Claims] (1) An insulator substrate and a pin on the top surface of this insulator substrate.
an island-shaped single crystal semiconductor layer in which a first region, a second region, and a third region forming an n-junction are laminated and have a side wall surface substantially perpendicular to the upper surface of the insulating substrate; a first conductive film provided on the insulating substrate and at least partially in contact with the first region; a first conductive film provided on the first conductive film via an insulating film and at least in contact with the second region; a second conductive film partially in contact with the first conductive film, a first electrode electrically connected to the first conductive film, and a second electrode electrically connected to the second conductive film; A semiconductor device comprising: a third electrode electrically connected to the third region.