JPS61121374A - Surface light-emitting element and manufacture thereof - Google Patents
Surface light-emitting element and manufacture thereofInfo
- Publication number
- JPS61121374A JPS61121374A JP59242662A JP24266284A JPS61121374A JP S61121374 A JPS61121374 A JP S61121374A JP 59242662 A JP59242662 A JP 59242662A JP 24266284 A JP24266284 A JP 24266284A JP S61121374 A JPS61121374 A JP S61121374A
- Authority
- JP
- Japan
- Prior art keywords
- light
- light emitting
- layer
- emitting
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000000926 separation method Methods 0.000 claims description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000000470 constituent Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 5
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 238000002310 reflectometry Methods 0.000 abstract 4
- 238000000034 method Methods 0.000 description 7
- 238000000605 extraction Methods 0.000 description 6
- 238000007740 vapor deposition Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 239000013307 optical fiber Substances 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 229910020776 SixNy Inorganic materials 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
- VLCQZHSMCYCDJL-UHFFFAOYSA-N tribenuron methyl Chemical compound COC(=O)C1=CC=CC=C1S(=O)(=O)NC(=O)N(C)C1=NC(C)=NC(OC)=N1 VLCQZHSMCYCDJL-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は光通信用、情報処理用の光源に使用して好適
な面発光素子、特にＧａ１ｎＡｓＰ／ＩｎＰ系面発光素
子及びそめ製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a surface emitting device suitable for use as a light source for optical communication and information processing, particularly a Ga1nAsP/InP surface emitting device and a method for manufacturing the surface emitting device.
（従来の技術）
光通信用の種々の構成の面発光素子が提案されかつ実用
化されている。第３図にこのような従来の面発光素子の
構造の一例を断面図で示す（文献： ＩＥＥＥ ＪＯυ
ＲＮＡＬ ＯＦ ＱＵＡＮＴＵＭ ＥＬＥＣＴＯＮＩＣ
：Ｓ 、 ＱＥ−１７［１７］、（ＦＥＢＲＵＡＲＹ
１！３８１））。(Prior Art) Surface emitting devices of various configurations for optical communication have been proposed and put into practical use. Figure 3 shows a cross-sectional view of an example of the structure of such a conventional surface emitting device (Reference: IEEE JOυ
RNAL OF QUANTUM ELECTRONIC
:S, QE-17 [17], (FEBRUARY
1!381)).
この従来の発光素子は、ｎ −ＩｎＰ基板３０の一方の
基板面３０ａ ｋにｎ −１ｎＰ層３１、発光層として
のＩｎＧａＡｓＰ層３２、ｐ −ＩｎＰ層３３及びコン
タクト層としての、亜鉛Ｚｎがドープされたｐ −Ｉｎ
ＧａＡｓＰ 層３４とが順次にエビタ午シャル成長によ
り形成されている。さらに、このコンタクト層３４上に
電流流路を制限するための穴３５を有する、例えば５ｉ
０２からなる絶縁層３８が蒸着により設けられていて、
この絶縁層３８上にはＰ側電極３７が蒸着により形成さ
れている。さらに、他方の基板面ｌｂ上には光取り出し
用の窓３８を有するｎ側電極３３が蒸着により形成され
ている。This conventional light-emitting element has an n-1nP layer 31, an InGaAsP layer 32 as a light-emitting layer, a p-InP layer 33, and a contact layer doped with zinc Zn on one substrate surface 30ak of an n-InP substrate 30. Tap-In
A GaAsP layer 34 is sequentially formed by vertical growth. Further, the contact layer 34 has a hole 35 for restricting the current flow path, for example, 5i.
An insulating layer 38 made of 02 is provided by vapor deposition,
A P-side electrode 37 is formed on this insulating layer 38 by vapor deposition. Further, on the other substrate surface lb, an n-side electrode 33 having a window 38 for light extraction is formed by vapor deposition.
このような構造において、ｐ側電極３７から注入された
電流は絶縁ｊｉｊ３Ｂの穴３５を通り、発光層３２の中
央部付近の発光領域３２ａに導入され、ここで発光を生
じ、発光した光は上側の各層３１．３０を通り、光取り
出し窓３８内の発光面３０ａから放出される。In such a structure, the current injected from the p-side electrode 37 passes through the hole 35 of the insulator 3B and is introduced into the light emitting region 32a near the center of the light emitting layer 32, where light is emitted, and the emitted light is directed to the upper side. The light passes through each of the layers 31 and 30 and is emitted from the light emitting surface 30a within the light extraction window 38.
（発明が解決しようとする問題点）
ところで、光通信用光源としての面発光素子は、光の漏
洩損失を少なくしかつ効率を高めるために１発光径が小
さいこと及び光の拡がり角が小さいことが要求されてい
る。(Problems to be Solved by the Invention) Incidentally, surface emitting elements used as light sources for optical communication have a small emission diameter and a small light spreading angle in order to reduce light leakage loss and increase efficiency. is required.
しかしながら、第３図に示す従来の発光素子においては
、絶縁層３Ｂで狭められた電流が他方の基板面３０ｂに
設けられたｎ側電極３９に向って末広がり状に流れるの
で、発光領域３２ａへの電流集中が怒く、従って、発光
径が大きくなると共に、光の拡がり角が大きくなって発
光パターンが台形状となってしまう、これがため１発光
素子を光ファイバーと結合させた時、光の損失が大きい
という欠点があった。However, in the conventional light-emitting device shown in FIG. 3, the current narrowed by the insulating layer 3B flows in a divergent manner toward the n-side electrode 39 provided on the other substrate surface 30b, so that the current flows toward the light-emitting region 32a. Current concentration increases, and as a result, as the emission diameter increases, the spread angle of light increases, resulting in a trapezoidal emission pattern.As a result, when one light emitting element is coupled to an optical fiber, light loss increases. It had the disadvantage of being large.
また、使用しているオーミック電極材料による反射が小
さいため、発光面３０ａとは反対方向へ進んだ光はほと
んど全て損失光となっていた。In addition, since reflection by the ohmic electrode material used is small, almost all of the light traveling in the direction opposite to the light emitting surface 30a becomes lost light.
さらに、発光径を小さくするために、絶縁層３４の電流
狭窄の穴３５を更に小さくすることも行われているが、
その場合には、熱抵抗が大きくなるため、素子自体が熱
破損を来たしてしまうという欠点があった。Furthermore, in order to reduce the emission diameter, the hole 35 for current confinement in the insulating layer 34 is also made smaller.
In that case, the thermal resistance increases, resulting in the element itself being damaged by heat.
この発明の目的は、このような従来の発光素子が有する
欠点を除去し、低電流でファイバーに効率良く光入力さ
せることが出来る面発光素子及びその製造方法を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a surface emitting device and a method for manufacturing the same, which eliminates the drawbacks of conventional light emitting devices and allows light to be efficiently input to a fiber with low current.
（問題点を解決するための手段）
この出願の第一の発明は、半導体基板ｌの一方の基板面
１ａの上側に発光層３を具え、他方の基板面１ｂを発光
面とした面発光素子において、この素子の発光面１０と
は反対側の裏面側から発光層３を突き抜ける深さでこの
発光領域３ａの周囲に設けられた環状の分離溝５と、こ
の分離溝５の壁面上及びこの分離溝５に囲まれた裏面上
に設けられた高反射率絶縁層６と、前述の発光面１０上
に設けられた低反射率絶縁層１１とを具えることを特徴
とする。(Means for Solving the Problems) The first invention of this application is a surface emitting element that includes a light emitting layer 3 on the upper side of one substrate surface 1a of a semiconductor substrate l, and uses the other substrate surface 1b as a light emitting surface. , an annular separation groove 5 is provided around the light-emitting region 3a with a depth penetrating the light-emitting layer 3 from the back surface side opposite to the light-emitting surface 10 of this element, and on the wall surface of the separation groove 5 and on the wall surface of the separation groove 5. It is characterized by comprising a high reflectance insulating layer 6 provided on the back surface surrounded by the separation groove 5 and a low reflectance insulating layer 11 provided on the above-mentioned light emitting surface 10.
この出願の第二の発明は、基板ｌの一方の基板面ｌａ上
に発光層を含む複数の素子構成層（２，３，４）を順次
に成長させる工程と、
この素子構成層（２，３，４）の表面４ａから発光層３
を突き抜ける深さにまで、この発光層３の発光領域３ａ
の周囲に、環状の分離溝５を設ける工程と、
この分離溝５の壁面上及びこの分離溝５により囲まれた
素子構成層（２，３，４）の表面の電極形成領域４ｂ以
外の領域上に高反射率絶縁層６を設ける工程と、
前述の発光面１０を画成する一方の電極９を前述の基板
１の他方の基板面ｌｂ上に形成する工程と、他方の電極
７を前述の電極形成領域４ｂ及び高反射率絶縁層６上に
被着する工程と。A second invention of this application includes a step of sequentially growing a plurality of element constituent layers (2, 3, 4) including a light emitting layer on one substrate surface la of a substrate l; 3, 4) from the surface 4a of the light emitting layer 3
The light emitting region 3a of this light emitting layer 3 reaches a depth that penetrates the
a step of providing an annular separation groove 5 around the separation groove 5; and a region other than the electrode formation region 4b on the wall surface of the separation groove 5 and on the surface of the element constituent layers (2, 3, 4) surrounded by the separation groove 5; a step of providing a high reflectance insulating layer 6 thereon; a step of forming one electrode 9 that defines the light emitting surface 10 described above on the other substrate surface lb of the substrate 1 described above; and a step of depositing it on the electrode forming region 4b and the high reflectance insulating layer 6.
前述の発光面１０上に低反射率絶縁層１１を被着する工
程と
を含むことを特徴とする。The method is characterized in that it includes a step of depositing a low reflectance insulating layer 11 on the light emitting surface 10 described above.
（作用）
この発明の発光素子の構造では、発光領域３ａの周辺を
取囲む分離溝（エア会アイソレーション）５が形成され
ているので、注入電流は発光領域３ｄに集中して流れ、
従って、発光効率が高まり、かつ、発光領域３ａを狭め
て発光径を小さくすることが出来る。(Function) In the structure of the light emitting element of the present invention, since the isolation groove (air isolation) 5 surrounding the periphery of the light emitting region 3a is formed, the injected current flows concentratedly in the light emitting region 3d.
Therefore, the light emitting efficiency is increased, and the light emitting area 3a can be narrowed to reduce the light emitting diameter.
また、分離溝５の壁面上及び発光面１０とは反対側の素
子裏面上に高反射率絶縁層６が設けられているので、発
光領域３ａから発光面１０とは反対側及び横方向に向っ
た光をほとんど反射させ、しかも、発光面１０には低反
射率絶縁層１１を具えているので、光出力を高効率で取
り出せることが出来る。Furthermore, since the high reflectance insulating layer 6 is provided on the wall surface of the separation groove 5 and on the back surface of the element on the opposite side to the light emitting surface 10, the high reflectance insulating layer 6 is provided on the wall surface of the separation groove 5 and on the back surface of the element on the opposite side to the light emitting surface 10. In addition, since the light emitting surface 10 is provided with the low reflectance insulating layer 11, the light output can be extracted with high efficiency.
また、このような構造により、光は発光面ｌＯの中央部
に多く集中するので、光の拡がり角が従来よりも著しく
小さくなり１発光パターンは中央部で発光強度の強い山
形となるため、光ファイバーとの結合効率が良い。In addition, with this structure, the light is concentrated in the center of the light emitting surface lO, so the spread angle of the light is significantly smaller than before, and one light emission pattern becomes a mountain shape with strong light emission intensity in the center, so the optical fiber Good coupling efficiency with
（実施例）
以下、図面を参照して、この発明の発光素子の一実施例
を説明する。(Example) Hereinafter, an example of the light emitting element of the present invention will be described with reference to the drawings.
第１図はこの発明の面発光素子の一実施例を概略的に示
す断面図、第２図（Ａ）〜（Ｅ）はその製造工程図であ
る。これら図において、断面を表わす八戸−ング等を省
略すると共に、各構成成分の形状寸法及び配置関係はこ
の発明の構成が理解出来る程度に概略的に示しである。FIG. 1 is a cross-sectional view schematically showing an embodiment of a surface emitting device of the present invention, and FIGS. 2(A) to 2(E) are manufacturing process diagrams thereof. In these figures, Hachinohe rings and the like representing cross sections are omitted, and the dimensions and arrangement relationships of each component are shown schematically to the extent that the structure of the present invention can be understood.
先ず、発光素子の構造につき説明する。First, the structure of the light emitting element will be explained.
基板としてｐ −ＩＪＩＰ基板１を用い、その一方の基
板面ｌａ上にｐ−１ｎＰバー／ ７７層２、ｐ −Ｇａ
ＩｎＡｓＰ発光層３、ｎ −ｒｎＰコンタクト層４等の
素子構成層が順次積層形成されている。A p-IJIP substrate 1 is used as a substrate, and a p-1nP bar/77 layer 2 and a p-Ga layer are formed on one substrate surface la.
Element constituent layers such as an InAsP light emitting layer 3 and an n-rnP contact layer 4 are sequentially stacked.
この発光！＃３の中央部分の発光領域３ａの周辺部分に
は、素子の裏面側からすなわちコンタクト層４の表面４
ａから発光層３を突き抜けた深さまで、環状の分離溝５
が形成されていて、この分離溝５により、発光領域３ａ
を発光層３の他の領域から狭い領域内に分離している。This luminescence! The peripheral part of the light emitting region 3a in the central part of #3 is exposed to the surface 4 of the contact layer 4 from the back side of the element.
The annular separation groove 5 extends from a to the depth that penetrates the light emitting layer 3.
is formed, and the light emitting region 3a is separated by the separation groove 5.
is separated from other regions of the light emitting layer 3 within a narrow region.
少なくともこの分離溝５の壁面上及び分離溝５の内側の
コンタクト層４の表面軸の電極形成領域４ｂを除いた部
分上にＣｅ０１Ｓｉ０２ 、 ＳｉｘＮｙ或いはその他
の好適な高反射率絶縁層（膜ともいう）６が被着されて
いて、電流を中央の発光領域３ａに集中させると共に、
発光して発光面とは反対方向及び横方向に進んだ光をほ
ぼ完全に反射させて発光面から効率良く放出させるよう
になしている。この高反射率絶縁層６の反射率は例えば
少なくとも８０〜８５％以上とするのが好適である。At least on the wall surface of this separation trench 5 and on the surface axis of the contact layer 4 inside the separation trench 5 excluding the electrode formation region 4b, a high reflectance insulating layer (also referred to as a film) of Ce01Si02, SixNy or other suitable high reflectance layer is applied. 6 is deposited to concentrate the current in the central light emitting region 3a, and
The light emitted and traveling in the opposite direction and sideways to the light emitting surface is almost completely reflected and efficiently emitted from the light emitting surface. The reflectance of this high reflectance insulating layer 6 is preferably at least 80 to 85%, for example.
上述した電極形成領域４ｂに他方の電極７であるオーミ
ック電極を有している。このオーミック電極７とコンタ
クト層４との界面が粗面となるので、この電極領域４ｂ
はこの表面４ａの周辺部に環状に形成しである。光取り
出し窓８を有する一方の電極９であるオーミック電極を
基板１の他方の基板面ｌｂ上に設けて、この窓８に露出
した基板面１ｂが発光面１０となる。An ohmic electrode, which is the other electrode 7, is provided in the electrode formation region 4b described above. Since the interface between this ohmic electrode 7 and the contact layer 4 becomes a rough surface, this electrode region 4b
is formed in a ring shape around the surface 4a. An ohmic electrode, which is one electrode 9 having a light extraction window 8, is provided on the other substrate surface lb of the substrate 1, and the substrate surface 1b exposed to the window 8 becomes the light emitting surface 10.
また、発光面１０には低反射率綿ｔ＆層１１が被着形成
されており、これがため、この発光面ｌＯでの反射損失
を少なくすることが出来る。この低反射率絶縁層１１は
例えば１０％以下の反射率とし、高反射率絶縁層６と同
一の材料で形成することが出来。Further, a low reflectance cotton T& layer 11 is formed on the light emitting surface 10, and therefore reflection loss at the light emitting surface 10 can be reduced. The low reflectance insulating layer 11 has a reflectance of, for example, 10% or less, and can be formed of the same material as the high reflectance insulating layer 6.
その場合、通常行われていると同様に、膜厚を調整する
ことにより低反射率とすることが出来る。In that case, the reflectance can be made low by adjusting the film thickness, as is usually done.
次に、この面発光素子の製造方法の一実施例につき説明
する。Next, an example of a method for manufacturing this surface emitting device will be described.
先ず、ｐ −ＩｎＰ基板１の基板面ｌａ上に、素子を構
成する各層であるｐ −１ｎＰバッファ層？、ｐ−Ｇａ
ｌｎＡｓＰ発光層３、ｎ−ＩｎＰ：Ｉンタクト層４を順
次に適当な成長方法、好ましくは液相エピタキシャル成
長方法で、連続的に結晶成長させる（第２図（Ａ） ）
。First, on the substrate surface la of the p-InP substrate 1, a p-1nP buffer layer, which is each layer constituting the device, is formed. , p-Ga
The lnAsP light-emitting layer 3 and the n-InP:I intact layer 4 are successively crystal-grown using an appropriate growth method, preferably a liquid phase epitaxial growth method (FIG. 2(A)).
.
次に、適当な発光径となるように残存させた発光領域３
ａの周囲であって、コンタクト層４の表面４ａから、発
光層３を突き抜ける深さに、基板面に垂直な方向から見
て環状の分離溝５をエツチング形成する（第２図（Ｂ）
） 、この場合１発光径を例えばｌＯ〜４０Ｊｊ、ｍ
程度とするのが好適である。Next, the light emitting region 3 is left to have an appropriate light emitting diameter.
A ring-shaped separation groove 5 is formed by etching around the contact layer 4 from the surface 4a of the contact layer 4 to a depth that penetrates the light emitting layer 3 when viewed from the direction perpendicular to the substrate surface (FIG. 2(B)).
), in this case, one emission diameter is, for example, lO~40Jj, m
It is preferable to set it as approximately.
次に、この分ａｂｗｓの内部の壁面上及びコンタクト層
の表面４ｄ上に高反射率絶縁層６を蒸着等により被着形
成し、続いて、分ａ溝５に囲まれたコンタクト層４の表
面４ａの周辺部分に電極形成領域４ｂをエツチングして
設け、その部分の表面４ａを露出させる（第２図（Ｃ）
）。この場合、分離溝５の壁面上と、分離窓５の内側の
表面４ａ上の周辺部にのみ環状に高反射率絶縁層６を被
着形成しても良い、尚、第２図（Ｃ）は第２図（Ｄ）の
Ｉ−Ｉ線上の断面図で、第２図（Ｄ）は平面図である。Next, a high reflectance insulating layer 6 is formed by vapor deposition or the like on the inner wall surface of the abws and the surface 4d of the contact layer, and then the surface of the contact layer 4 surrounded by the abws 5 is formed. An electrode formation region 4b is provided by etching around the peripheral portion of the electrode formation region 4a, and the surface 4a of that portion is exposed (FIG. 2(C)).
). In this case, the high reflectance insulating layer 6 may be formed in an annular manner only on the wall surface of the separation groove 5 and the periphery of the inner surface 4a of the separation window 5, as shown in FIG. 2(C). 2(D) is a sectional view taken along line II in FIG. 2(D), and FIG. 2(D) is a plan view.
さらに、この電極形成領域４ｂ及び高反射率絶縁層６上
にｎ側オーミック電極７を蒸着し、基板１の他方の基板
面ｌｂ上に光取り出し窓ｌＯを有するｐ側オーミック電
極９を蒸着する（第２図（Ｅ） ） 。Further, an n-side ohmic electrode 7 is deposited on the electrode formation region 4b and the high reflectance insulating layer 6, and a p-side ohmic electrode 9 having a light extraction window IO is deposited on the other substrate surface lb of the substrate 1 ( Figure 2 (E)).
そして、最後に、光取り出し窓８から露出している発光
面１０上に低反射率絶縁層１１を蒸着等により形成し、
オーミック電極７及び９の金属化処理を行って（第２図
（Ｇ））、この工程を終了する。Finally, a low reflectance insulating layer 11 is formed by vapor deposition or the like on the light emitting surface 10 exposed through the light extraction window 8.
This step is completed by metallizing the ohmic electrodes 7 and 9 (FIG. 2(G)).
この発明は上述した実施例にのみに限定されるものでは
ない０例えば、素子を構成する各層の導電型を上述した
実施例の場合とは反対導電型とすることが出来る。The present invention is not limited to the embodiments described above. For example, the conductivity type of each layer constituting the element can be made to be the opposite conductivity type to that in the embodiments described above.
また、素子構成層として上述した各層以外の層を含んで
いても良い。Further, layers other than the above-mentioned layers may be included as element constituent layers.
さらに、上述した絶縁層、各電極及び高反射率層の製造
工程は任意適切にその順序を変更しても良い。Furthermore, the order of the above-described manufacturing steps for the insulating layer, each electrode, and the high reflectance layer may be changed as desired.
（発明の効果）
上述した説明かうも明らかなように、この発明の面発光
素子によれば、発光領域の周辺を取囲む絶縁層を具える
分離溝（エア・アイソレーション）により、電流狭窄が
行われて注入電流は発光領域に集中して流れ、従って、
発光効率が高まり、かつ、発光領域を狭めて発光径を小
さくすることが出来る。(Effects of the Invention) As is clear from the above explanation, according to the surface emitting device of the present invention, current confinement is prevented by the isolation groove (air isolation) provided with the insulating layer surrounding the periphery of the light emitting region. The injection current flows concentrated in the light emitting region, and therefore,
The luminous efficiency can be increased, and the luminous area can be narrowed to reduce the luminous diameter.
また、分離溝内はもとより、発光面とは反対側の裏面に
も高反射率絶縁層を具えているので、発光面とは反対側
及び横方向に向った光をほとんど反射させ、しかも、発
光面には低反射率絶縁層を具えているので、発光面での
反射損失は低減し、よって、光出力を高効率で取り出せ
ることが出来る。In addition, a high-reflectance insulating layer is provided not only inside the separation groove but also on the back surface opposite to the light-emitting surface, so that most of the light directed to the side opposite to the light-emitting surface and in the lateral direction is reflected. Since the surface is provided with a low-reflectance insulating layer, reflection loss at the light emitting surface is reduced, so that light output can be extracted with high efficiency.
また、光は発光面の中央部多く集中するので。Also, most of the light is concentrated in the center of the light emitting surface.
光の拡がり角が従来よりも著しく小さくなり、発光パタ
ーンは中央部で発光強度の強い山形となるため、光ファ
イバーとの結合効率が良い。The spread angle of the light is significantly smaller than in the past, and the light emitting pattern becomes a mountain shape with strong light emission intensity in the center, so the coupling efficiency with the optical fiber is good.
さらに、電流通路を狭めない構造であるので、従来のよ
うな熱破損を来すおそれがない。Furthermore, since the structure does not narrow the current path, there is no risk of thermal damage as in the conventional case.
このような面発光素子は発光ダイオード、超輻射ダイオ
ード、レーザとして用いることが出来、光通信用、情報
処理用の光源に適用して好適である。Such surface emitting elements can be used as light emitting diodes, superradiation diodes, and lasers, and are suitable for application to light sources for optical communication and information processing.
第１図はこの発明の面発光素子の構造の一実施例を示す
路線的断面図。
第２図（Ａ）〜（Ｅ）はこの発明の面発光素子の製造工
程の一実施例を説明するための工程図、第３図は従来の
面発光素子の構造を説明するための断面図である。
１ ・” Ｐ −ｒｎＰ基板、 １ａ、１ ｂ ・・・
基板面２・・・ｐ−ＩｎＰバッファ層
３−−− ｐ −ＧａＩｎＡｓＰ発光層３ａ・・・発光
領域、 ４・・・ｎ −ＩｎＰコンタクト層４ａ・
・・コンタクト層の表面
４ｂ・・・電極形成領域
５・・・分離溝、 ６・・・高反射率絶縁層７．
９・・・電極、 ８・・・光取り出し窓ｌＯ・・
・発光面、 １１・・・低反射率絶縁層。
特許出願人 沖電気工業株式会社代理人 弁理
士 大 垣 孝 、セｌり）′：入゛・ｑ−
”１６．・−
第１図
／ ： Ｐ−１ｎＰ基ａ ｓ ：ｓａｔ
／ｄ、／＃：基ＵＬ山 ６：漏す１牢他軸
層２ ： ｐ４ｎＰバーｑ７ア４
７ コ ６Ｊ ： Ｐ−（ｔａｒπＡｓＰ発光
層 ８ 九１艮り土し＋ｔ・Ｊａ−発光ａ坂
ｑ 電極４ ’ ｎ−１ｎＰ’２＞タク
ト、ｌ ｆＯ：％ｆｔｒｌＪ４針ｆＪ４ＨＡ４
１宵ｚｔｉ、 ｌｆ： イ収Ａ辷」１
丁噸巨遥４−嬶）ｉ第２図FIG. 1 is a cross-sectional view showing an embodiment of the structure of a surface emitting device according to the present invention. FIGS. 2(A) to (E) are process diagrams for explaining one embodiment of the manufacturing process of a surface emitting device of the present invention, and FIG. 3 is a sectional view for explaining the structure of a conventional surface emitting device. It is. 1.”P-rnP substrate, 1a, 1b...
Substrate surface 2...p-InP buffer layer 3---p-GaInAsP light emitting layer 3a...light emitting region, 4...n-InP contact layer 4a.
...Surface 4b of contact layer...Electrode formation region 5...Separation groove, 6...High reflectance insulating layer 7.
9... Electrode, 8... Light extraction window lO...
- Light emitting surface, 11...low reflectance insulating layer. Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Takashi Ogaki, Selling)': Enter゛・q−
"16.--Figure 1/: P-1nP group a s : sat
/d, /#: base UL mountain 6: leak 1 layer other axis layer 2: p4nP bar q7 a 4
7 Ko 6J: P-(tarπAsP light-emitting layer 8 91 Tsuri soil + t・Ja- light emitting a slope
q electrode 4'n-1nP'2>tact, l fO:%ftrlJ4 needle fJ4HA4
1st night, lf: 1.
Dingxian Jyoyo 4-嬶)i Figure 2
Claims (1)
他方の基板面を発光面とした面発光素子において、該素
子の発光面とは反対側の裏面側から前記発光層を突き抜
ける深さで該発光領域の周囲に設けられた環状の分離溝
と、該分離溝の壁面上及び該分離溝に囲まれた裏面上に
設けられた高反射率絶縁層と、前記発光面上に設けられ
た低反射率絶縁層とを具えることを特徴とする面発光素
子。 ２、半導体基板の一方の基板面の上側に発光層を具え、
他方の基板面を発光面とした面発光素子を製造するに当
り、 基板の一方の基板面上に発光層を含む複数の素子構成層
を順次に成長させる工程と、 該素子構成層の表面から前記発光層を突き抜ける深さに
まで、該発光層の発光領域の周囲に、環状の分離溝を設
ける工程と、 該分離溝の壁面上及び前記分離溝により囲まれた素子構
成層の表面の電極形成領域以外の領域上に高反射率絶縁
層を設ける工程と、 前記発光面を画成する一方の電極を前記基板の他方の基
板面上に形成する工程と、 他方の電極を前記電極形成領域及び高反射率絶縁層上に
被着する工程と、 前記発光面上に低反射率絶縁層を被着する工程と を含むことを特徴とする面発光素子の製造方法。[Claims] 1. A light-emitting layer is provided on the upper side of one substrate surface of the semiconductor substrate,
In a surface emitting device with the other substrate surface as a light emitting surface, an annular separation groove provided around the light emitting region with a depth that penetrates the light emitting layer from the back side opposite to the light emitting surface of the device; A surface comprising a high reflectance insulating layer provided on the wall surface of the separation groove and a back surface surrounded by the separation groove, and a low reflectance insulating layer provided on the light emitting surface. Light emitting element. 2. A light emitting layer is provided on the upper side of one substrate surface of the semiconductor substrate,
In manufacturing a surface emitting device with the other substrate surface as a light emitting surface, there are a step of sequentially growing a plurality of device constituent layers including a light emitting layer on one substrate surface of the substrate, and a step of growing a plurality of device constituent layers including a light emitting layer on one substrate surface, and a step of providing an annular separation groove around the light-emitting region of the light-emitting layer to a depth that penetrates the light-emitting layer; and an electrode on the wall surface of the separation groove and on the surface of the element-constituting layer surrounded by the separation groove. a step of providing a high reflectance insulating layer on a region other than the formation region; a step of forming one electrode that defines the light emitting surface on the other substrate surface of the substrate; and a step of forming the other electrode in the electrode formation region. and a step of depositing a high reflectance insulating layer on the light emitting surface, and a step of depositing a low reflectance insulating layer on the light emitting surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59242662A JPS61121374A (en) | 1984-11-17 | 1984-11-17 | Surface light-emitting element and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59242662A JPS61121374A (en) | 1984-11-17 | 1984-11-17 | Surface light-emitting element and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61121374A true JPS61121374A (en) | 1986-06-09 |
Family
ID=17092372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59242662A Pending JPS61121374A (en) | 1984-11-17 | 1984-11-17 | Surface light-emitting element and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121374A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03163883A (en) * | 1989-11-22 | 1991-07-15 | Daido Steel Co Ltd | Light-emitting diode with optical reflection layer |
-
1984
- 1984-11-17 JP JP59242662A patent/JPS61121374A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03163883A (en) * | 1989-11-22 | 1991-07-15 | Daido Steel Co Ltd | Light-emitting diode with optical reflection layer |
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